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Pierre Ossmand129bce2006-03-24 03:18:17 -08001/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
Pierre Ossman643f7202006-09-30 23:27:52 -07007 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
Pierre Ossmand129bce2006-03-24 03:18:17 -080010 */
11
Pierre Ossmand129bce2006-03-24 03:18:17 -080012#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
18#include <linux/mmc/protocol.h>
19
20#include <asm/scatterlist.h>
21
22#include "sdhci.h"
23
24#define DRIVER_NAME "sdhci"
Pierre Ossman2c5f3942006-06-30 02:22:32 -070025#define DRIVER_VERSION "0.12"
Pierre Ossmand129bce2006-03-24 03:18:17 -080026
27#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
28
Pierre Ossmand129bce2006-03-24 03:18:17 -080029#define DBG(f, x...) \
Russell Kingc6563172006-03-29 09:30:20 +010030 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
Pierre Ossmand129bce2006-03-24 03:18:17 -080031
Pierre Ossman67435272006-06-30 02:22:31 -070032static unsigned int debug_nodma = 0;
33static unsigned int debug_forcedma = 0;
Pierre Ossmandf673b22006-06-30 02:22:31 -070034static unsigned int debug_quirks = 0;
Pierre Ossman67435272006-06-30 02:22:31 -070035
Pierre Ossman645289d2006-06-30 02:22:33 -070036#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
Pierre Ossman98608072006-06-30 02:22:34 -070037#define SDHCI_QUIRK_FORCE_DMA (1<<1)
Pierre Ossman8a4da142006-10-04 02:15:40 -070038/* Controller doesn't like some resets when there is no card inserted. */
39#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
Darren Salt9e9dc5f2007-01-27 15:32:31 +010040#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
Pierre Ossman645289d2006-06-30 02:22:33 -070041
Pierre Ossmand129bce2006-03-24 03:18:17 -080042static const struct pci_device_id pci_ids[] __devinitdata = {
Pierre Ossman645289d2006-06-30 02:22:33 -070043 {
44 .vendor = PCI_VENDOR_ID_RICOH,
45 .device = PCI_DEVICE_ID_RICOH_R5C822,
46 .subvendor = PCI_VENDOR_ID_IBM,
47 .subdevice = PCI_ANY_ID,
Pierre Ossman98608072006-06-30 02:22:34 -070048 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
49 SDHCI_QUIRK_FORCE_DMA,
50 },
51
52 {
53 .vendor = PCI_VENDOR_ID_RICOH,
54 .device = PCI_DEVICE_ID_RICOH_R5C822,
55 .subvendor = PCI_ANY_ID,
56 .subdevice = PCI_ANY_ID,
Pierre Ossman8a4da142006-10-04 02:15:40 -070057 .driver_data = SDHCI_QUIRK_FORCE_DMA |
58 SDHCI_QUIRK_NO_CARD_NO_RESET,
Pierre Ossman98608072006-06-30 02:22:34 -070059 },
60
61 {
62 .vendor = PCI_VENDOR_ID_TI,
63 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
64 .subvendor = PCI_ANY_ID,
65 .subdevice = PCI_ANY_ID,
66 .driver_data = SDHCI_QUIRK_FORCE_DMA,
Pierre Ossman645289d2006-06-30 02:22:33 -070067 },
68
Darren Salt9e9dc5f2007-01-27 15:32:31 +010069 {
70 .vendor = PCI_VENDOR_ID_ENE,
71 .device = PCI_DEVICE_ID_ENE_CB712_SD,
72 .subvendor = PCI_ANY_ID,
73 .subdevice = PCI_ANY_ID,
74 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
75 },
76
Pierre Ossman645289d2006-06-30 02:22:33 -070077 { /* Generic SD host controller */
78 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
79 },
80
Pierre Ossmand129bce2006-03-24 03:18:17 -080081 { /* end: all zeroes */ },
82};
83
84MODULE_DEVICE_TABLE(pci, pci_ids);
85
86static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
87static void sdhci_finish_data(struct sdhci_host *);
88
89static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
90static void sdhci_finish_command(struct sdhci_host *);
91
92static void sdhci_dumpregs(struct sdhci_host *host)
93{
94 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
95
96 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
97 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
98 readw(host->ioaddr + SDHCI_HOST_VERSION));
99 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
100 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
101 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
102 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
103 readl(host->ioaddr + SDHCI_ARGUMENT),
104 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
105 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
106 readl(host->ioaddr + SDHCI_PRESENT_STATE),
107 readb(host->ioaddr + SDHCI_HOST_CONTROL));
108 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
109 readb(host->ioaddr + SDHCI_POWER_CONTROL),
110 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
111 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
112 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
113 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
114 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
115 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
116 readl(host->ioaddr + SDHCI_INT_STATUS));
117 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
118 readl(host->ioaddr + SDHCI_INT_ENABLE),
119 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
120 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
121 readw(host->ioaddr + SDHCI_ACMD12_ERR),
122 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
123 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_CAPABILITIES),
125 readl(host->ioaddr + SDHCI_MAX_CURRENT));
126
127 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
136static void sdhci_reset(struct sdhci_host *host, u8 mask)
137{
Pierre Ossmane16514d82006-06-30 02:22:24 -0700138 unsigned long timeout;
139
Pierre Ossman8a4da142006-10-04 02:15:40 -0700140 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
141 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
142 SDHCI_CARD_PRESENT))
143 return;
144 }
145
Pierre Ossmand129bce2006-03-24 03:18:17 -0800146 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
147
Pierre Ossmane16514d82006-06-30 02:22:24 -0700148 if (mask & SDHCI_RESET_ALL)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800149 host->clock = 0;
150
Pierre Ossmane16514d82006-06-30 02:22:24 -0700151 /* Wait max 100 ms */
152 timeout = 100;
153
154 /* hw clears the bit when it's done */
155 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
156 if (timeout == 0) {
157 printk(KERN_ERR "%s: Reset 0x%x never completed. "
158 "Please report this to " BUGMAIL ".\n",
159 mmc_hostname(host->mmc), (int)mask);
160 sdhci_dumpregs(host);
161 return;
162 }
163 timeout--;
164 mdelay(1);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800165 }
166}
167
168static void sdhci_init(struct sdhci_host *host)
169{
170 u32 intmask;
171
172 sdhci_reset(host, SDHCI_RESET_ALL);
173
Pierre Ossman3192a282006-06-30 02:22:26 -0700174 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
175 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
176 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
177 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100178 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
Pierre Ossman3192a282006-06-30 02:22:26 -0700179 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800180
181 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
182 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800183}
184
185static void sdhci_activate_led(struct sdhci_host *host)
186{
187 u8 ctrl;
188
189 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
190 ctrl |= SDHCI_CTRL_LED;
191 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
192}
193
194static void sdhci_deactivate_led(struct sdhci_host *host)
195{
196 u8 ctrl;
197
198 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
199 ctrl &= ~SDHCI_CTRL_LED;
200 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
201}
202
203/*****************************************************************************\
204 * *
205 * Core functions *
206 * *
207\*****************************************************************************/
208
209static inline char* sdhci_kmap_sg(struct sdhci_host* host)
210{
211 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
212 return host->mapped_sg + host->cur_sg->offset;
213}
214
215static inline void sdhci_kunmap_sg(struct sdhci_host* host)
216{
217 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
218}
219
220static inline int sdhci_next_sg(struct sdhci_host* host)
221{
222 /*
223 * Skip to next SG entry.
224 */
225 host->cur_sg++;
226 host->num_sg--;
227
228 /*
229 * Any entries left?
230 */
231 if (host->num_sg > 0) {
232 host->offset = 0;
233 host->remain = host->cur_sg->length;
234 }
235
236 return host->num_sg;
237}
238
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100239static void sdhci_read_block_pio(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800240{
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100241 int blksize, chunk_remain;
242 u32 data;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800243 char *buffer;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100244 int size;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800245
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100246 DBG("PIO reading\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800247
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100248 blksize = host->data->blksz;
249 chunk_remain = 0;
250 data = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800251
252 buffer = sdhci_kmap_sg(host) + host->offset;
253
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100254 while (blksize) {
255 if (chunk_remain == 0) {
256 data = readl(host->ioaddr + SDHCI_BUFFER);
257 chunk_remain = min(blksize, 4);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800258 }
259
Pierre Ossmand129bce2006-03-24 03:18:17 -0800260 size = min(host->size, host->remain);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100261 size = min(size, chunk_remain);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800262
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100263 chunk_remain -= size;
264 blksize -= size;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800265 host->offset += size;
266 host->remain -= size;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800267 host->size -= size;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100268 while (size) {
269 *buffer = data & 0xFF;
270 buffer++;
271 data >>= 8;
272 size--;
273 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800274
275 if (host->remain == 0) {
276 sdhci_kunmap_sg(host);
277 if (sdhci_next_sg(host) == 0) {
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100278 BUG_ON(blksize != 0);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800279 return;
280 }
281 buffer = sdhci_kmap_sg(host);
282 }
283 }
284
285 sdhci_kunmap_sg(host);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100286}
Pierre Ossmand129bce2006-03-24 03:18:17 -0800287
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100288static void sdhci_write_block_pio(struct sdhci_host *host)
289{
290 int blksize, chunk_remain;
291 u32 data;
292 char *buffer;
293 int bytes, size;
294
295 DBG("PIO writing\n");
296
297 blksize = host->data->blksz;
298 chunk_remain = 4;
299 data = 0;
300
301 bytes = 0;
302 buffer = sdhci_kmap_sg(host) + host->offset;
303
304 while (blksize) {
305 size = min(host->size, host->remain);
306 size = min(size, chunk_remain);
307
308 chunk_remain -= size;
309 blksize -= size;
310 host->offset += size;
311 host->remain -= size;
312 host->size -= size;
313 while (size) {
314 data >>= 8;
315 data |= (u32)*buffer << 24;
316 buffer++;
317 size--;
318 }
319
320 if (chunk_remain == 0) {
321 writel(data, host->ioaddr + SDHCI_BUFFER);
322 chunk_remain = min(blksize, 4);
323 }
324
325 if (host->remain == 0) {
326 sdhci_kunmap_sg(host);
327 if (sdhci_next_sg(host) == 0) {
328 BUG_ON(blksize != 0);
329 return;
330 }
331 buffer = sdhci_kmap_sg(host);
332 }
333 }
334
335 sdhci_kunmap_sg(host);
336}
337
338static void sdhci_transfer_pio(struct sdhci_host *host)
339{
340 u32 mask;
341
342 BUG_ON(!host->data);
343
344 if (host->size == 0)
345 return;
346
347 if (host->data->flags & MMC_DATA_READ)
348 mask = SDHCI_DATA_AVAILABLE;
349 else
350 mask = SDHCI_SPACE_AVAILABLE;
351
352 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
353 if (host->data->flags & MMC_DATA_READ)
354 sdhci_read_block_pio(host);
355 else
356 sdhci_write_block_pio(host);
357
358 if (host->size == 0)
359 break;
360
361 BUG_ON(host->num_sg == 0);
362 }
363
364 DBG("PIO transfer complete.\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800365}
366
367static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
368{
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700369 u8 count;
370 unsigned target_timeout, current_timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800371
372 WARN_ON(host->data);
373
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700374 if (data == NULL)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800375 return;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800376
377 DBG("blksz %04x blks %04x flags %08x\n",
Russell Kinga3fd4a12006-06-04 17:51:15 +0100378 data->blksz, data->blocks, data->flags);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800379 DBG("tsac %d ms nsac %d clk\n",
380 data->timeout_ns / 1000000, data->timeout_clks);
381
Pierre Ossmanbab76962006-07-02 16:51:35 +0100382 /* Sanity checks */
383 BUG_ON(data->blksz * data->blocks > 524288);
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +0100384 BUG_ON(data->blksz > host->mmc->max_blk_size);
Pierre Ossman1d676e02006-07-02 16:52:10 +0100385 BUG_ON(data->blocks > 65535);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800386
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700387 /* timeout in us */
388 target_timeout = data->timeout_ns / 1000 +
389 data->timeout_clks / host->clock;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800390
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700391 /*
392 * Figure out needed cycles.
393 * We do this in steps in order to fit inside a 32 bit int.
394 * The first step is the minimum timeout, which will have a
395 * minimum resolution of 6 bits:
396 * (1) 2^13*1000 > 2^22,
397 * (2) host->timeout_clk < 2^16
398 * =>
399 * (1) / (2) > 2^6
400 */
401 count = 0;
402 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
403 while (current_timeout < target_timeout) {
404 count++;
405 current_timeout <<= 1;
406 if (count >= 0xF)
407 break;
408 }
409
410 if (count >= 0xF) {
411 printk(KERN_WARNING "%s: Too large timeout requested!\n",
412 mmc_hostname(host->mmc));
413 count = 0xE;
414 }
415
416 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800417
418 if (host->flags & SDHCI_USE_DMA) {
419 int count;
420
421 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
422 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
423 BUG_ON(count != 1);
424
425 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
426 } else {
Russell Kinga3fd4a12006-06-04 17:51:15 +0100427 host->size = data->blksz * data->blocks;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800428
429 host->cur_sg = data->sg;
430 host->num_sg = data->sg_len;
431
432 host->offset = 0;
433 host->remain = host->cur_sg->length;
434 }
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700435
Pierre Ossmanbab76962006-07-02 16:51:35 +0100436 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
437 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
438 host->ioaddr + SDHCI_BLOCK_SIZE);
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700439 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
440}
441
442static void sdhci_set_transfer_mode(struct sdhci_host *host,
443 struct mmc_data *data)
444{
445 u16 mode;
446
447 WARN_ON(host->data);
448
449 if (data == NULL)
450 return;
451
452 mode = SDHCI_TRNS_BLK_CNT_EN;
453 if (data->blocks > 1)
454 mode |= SDHCI_TRNS_MULTI;
455 if (data->flags & MMC_DATA_READ)
456 mode |= SDHCI_TRNS_READ;
457 if (host->flags & SDHCI_USE_DMA)
458 mode |= SDHCI_TRNS_DMA;
459
460 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800461}
462
463static void sdhci_finish_data(struct sdhci_host *host)
464{
465 struct mmc_data *data;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800466 u16 blocks;
467
468 BUG_ON(!host->data);
469
470 data = host->data;
471 host->data = NULL;
472
473 if (host->flags & SDHCI_USE_DMA) {
474 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
475 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800476 }
477
478 /*
479 * Controller doesn't count down when in single block mode.
480 */
481 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
482 blocks = 0;
483 else
484 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
Russell Kinga3fd4a12006-06-04 17:51:15 +0100485 data->bytes_xfered = data->blksz * (data->blocks - blocks);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800486
487 if ((data->error == MMC_ERR_NONE) && blocks) {
488 printk(KERN_ERR "%s: Controller signalled completion even "
489 "though there were blocks left. Please report this "
490 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
491 data->error = MMC_ERR_FAILED;
Pierre Ossman4cca56c2006-06-30 02:22:34 -0700492 } else if (host->size != 0) {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800493 printk(KERN_ERR "%s: %d bytes were left untransferred. "
494 "Please report this to " BUGMAIL ".\n",
495 mmc_hostname(host->mmc), host->size);
496 data->error = MMC_ERR_FAILED;
497 }
498
499 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
500
501 if (data->stop) {
502 /*
503 * The controller needs a reset of internal state machines
504 * upon error conditions.
505 */
506 if (data->error != MMC_ERR_NONE) {
507 sdhci_reset(host, SDHCI_RESET_CMD);
508 sdhci_reset(host, SDHCI_RESET_DATA);
509 }
510
511 sdhci_send_command(host, data->stop);
512 } else
513 tasklet_schedule(&host->finish_tasklet);
514}
515
516static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
517{
518 int flags;
Pierre Ossmanfd2208d2006-06-30 02:22:28 -0700519 u32 mask;
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700520 unsigned long timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800521
522 WARN_ON(host->cmd);
523
524 DBG("Sending cmd (%x)\n", cmd->opcode);
525
526 /* Wait max 10 ms */
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700527 timeout = 10;
Pierre Ossmanfd2208d2006-06-30 02:22:28 -0700528
529 mask = SDHCI_CMD_INHIBIT;
530 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
531 mask |= SDHCI_DATA_INHIBIT;
532
533 /* We shouldn't wait for data inihibit for stop commands, even
534 though they might use busy signaling */
535 if (host->mrq->data && (cmd == host->mrq->data->stop))
536 mask &= ~SDHCI_DATA_INHIBIT;
537
538 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700539 if (timeout == 0) {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800540 printk(KERN_ERR "%s: Controller never released "
Pierre Ossmanfd2208d2006-06-30 02:22:28 -0700541 "inhibit bit(s). Please report this to "
Pierre Ossmand129bce2006-03-24 03:18:17 -0800542 BUGMAIL ".\n", mmc_hostname(host->mmc));
543 sdhci_dumpregs(host);
544 cmd->error = MMC_ERR_FAILED;
545 tasklet_schedule(&host->finish_tasklet);
546 return;
547 }
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700548 timeout--;
549 mdelay(1);
550 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800551
552 mod_timer(&host->timer, jiffies + 10 * HZ);
553
554 host->cmd = cmd;
555
556 sdhci_prepare_data(host, cmd->data);
557
558 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
559
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700560 sdhci_set_transfer_mode(host, cmd->data);
561
Pierre Ossmand129bce2006-03-24 03:18:17 -0800562 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
563 printk(KERN_ERR "%s: Unsupported response type! "
564 "Please report this to " BUGMAIL ".\n",
565 mmc_hostname(host->mmc));
566 cmd->error = MMC_ERR_INVALID;
567 tasklet_schedule(&host->finish_tasklet);
568 return;
569 }
570
571 if (!(cmd->flags & MMC_RSP_PRESENT))
572 flags = SDHCI_CMD_RESP_NONE;
573 else if (cmd->flags & MMC_RSP_136)
574 flags = SDHCI_CMD_RESP_LONG;
575 else if (cmd->flags & MMC_RSP_BUSY)
576 flags = SDHCI_CMD_RESP_SHORT_BUSY;
577 else
578 flags = SDHCI_CMD_RESP_SHORT;
579
580 if (cmd->flags & MMC_RSP_CRC)
581 flags |= SDHCI_CMD_CRC;
582 if (cmd->flags & MMC_RSP_OPCODE)
583 flags |= SDHCI_CMD_INDEX;
584 if (cmd->data)
585 flags |= SDHCI_CMD_DATA;
586
Pierre Ossmanfb61e282006-07-11 21:06:48 +0200587 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
Pierre Ossmand129bce2006-03-24 03:18:17 -0800588 host->ioaddr + SDHCI_COMMAND);
589}
590
591static void sdhci_finish_command(struct sdhci_host *host)
592{
593 int i;
594
595 BUG_ON(host->cmd == NULL);
596
597 if (host->cmd->flags & MMC_RSP_PRESENT) {
598 if (host->cmd->flags & MMC_RSP_136) {
599 /* CRC is stripped so we need to do some shifting. */
600 for (i = 0;i < 4;i++) {
601 host->cmd->resp[i] = readl(host->ioaddr +
602 SDHCI_RESPONSE + (3-i)*4) << 8;
603 if (i != 3)
604 host->cmd->resp[i] |=
605 readb(host->ioaddr +
606 SDHCI_RESPONSE + (3-i)*4-1);
607 }
608 } else {
609 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
610 }
611 }
612
613 host->cmd->error = MMC_ERR_NONE;
614
615 DBG("Ending cmd (%x)\n", host->cmd->opcode);
616
Pierre Ossman3192a282006-06-30 02:22:26 -0700617 if (host->cmd->data)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800618 host->data = host->cmd->data;
Pierre Ossman3192a282006-06-30 02:22:26 -0700619 else
Pierre Ossmand129bce2006-03-24 03:18:17 -0800620 tasklet_schedule(&host->finish_tasklet);
621
622 host->cmd = NULL;
623}
624
625static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
626{
627 int div;
Pierre Ossman077df882006-11-08 23:06:35 +0100628 u8 ctrl;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800629 u16 clk;
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700630 unsigned long timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800631
632 if (clock == host->clock)
633 return;
634
635 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
636
Pierre Ossman077df882006-11-08 23:06:35 +0100637 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
638 if (clock > 25000000)
639 ctrl |= SDHCI_CTRL_HISPD;
640 else
641 ctrl &= ~SDHCI_CTRL_HISPD;
642 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
643
Pierre Ossmand129bce2006-03-24 03:18:17 -0800644 if (clock == 0)
645 goto out;
646
647 for (div = 1;div < 256;div *= 2) {
648 if ((host->max_clk / div) <= clock)
649 break;
650 }
651 div >>= 1;
652
653 clk = div << SDHCI_DIVIDER_SHIFT;
654 clk |= SDHCI_CLOCK_INT_EN;
655 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
656
657 /* Wait max 10 ms */
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700658 timeout = 10;
659 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
660 & SDHCI_CLOCK_INT_STABLE)) {
661 if (timeout == 0) {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800662 printk(KERN_ERR "%s: Internal clock never stabilised. "
663 "Please report this to " BUGMAIL ".\n",
664 mmc_hostname(host->mmc));
665 sdhci_dumpregs(host);
666 return;
667 }
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700668 timeout--;
669 mdelay(1);
670 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800671
672 clk |= SDHCI_CLOCK_CARD_EN;
673 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
674
675out:
676 host->clock = clock;
677}
678
Pierre Ossman146ad662006-06-30 02:22:23 -0700679static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
680{
681 u8 pwr;
682
683 if (host->power == power)
684 return;
685
Darren Salt9e9dc5f2007-01-27 15:32:31 +0100686 if (power == (unsigned short)-1) {
687 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
Pierre Ossman146ad662006-06-30 02:22:23 -0700688 goto out;
Darren Salt9e9dc5f2007-01-27 15:32:31 +0100689 }
690
691 /*
692 * Spec says that we should clear the power reg before setting
693 * a new value. Some controllers don't seem to like this though.
694 */
695 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
696 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
Pierre Ossman146ad662006-06-30 02:22:23 -0700697
698 pwr = SDHCI_POWER_ON;
699
700 switch (power) {
701 case MMC_VDD_170:
702 case MMC_VDD_180:
703 case MMC_VDD_190:
704 pwr |= SDHCI_POWER_180;
705 break;
706 case MMC_VDD_290:
707 case MMC_VDD_300:
708 case MMC_VDD_310:
709 pwr |= SDHCI_POWER_300;
710 break;
711 case MMC_VDD_320:
712 case MMC_VDD_330:
713 case MMC_VDD_340:
714 pwr |= SDHCI_POWER_330;
715 break;
716 default:
717 BUG();
718 }
719
720 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
721
722out:
723 host->power = power;
724}
725
Pierre Ossmand129bce2006-03-24 03:18:17 -0800726/*****************************************************************************\
727 * *
728 * MMC callbacks *
729 * *
730\*****************************************************************************/
731
732static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
733{
734 struct sdhci_host *host;
735 unsigned long flags;
736
737 host = mmc_priv(mmc);
738
739 spin_lock_irqsave(&host->lock, flags);
740
741 WARN_ON(host->mrq != NULL);
742
743 sdhci_activate_led(host);
744
745 host->mrq = mrq;
746
747 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
748 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
749 tasklet_schedule(&host->finish_tasklet);
750 } else
751 sdhci_send_command(host, mrq->cmd);
752
Pierre Ossman5f25a662006-10-04 02:15:39 -0700753 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -0800754 spin_unlock_irqrestore(&host->lock, flags);
755}
756
757static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
758{
759 struct sdhci_host *host;
760 unsigned long flags;
761 u8 ctrl;
762
763 host = mmc_priv(mmc);
764
765 spin_lock_irqsave(&host->lock, flags);
766
Pierre Ossmand129bce2006-03-24 03:18:17 -0800767 /*
768 * Reset the chip on each power off.
769 * Should clear out any weird states.
770 */
771 if (ios->power_mode == MMC_POWER_OFF) {
772 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800773 sdhci_init(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800774 }
775
776 sdhci_set_clock(host, ios->clock);
777
778 if (ios->power_mode == MMC_POWER_OFF)
Pierre Ossman146ad662006-06-30 02:22:23 -0700779 sdhci_set_power(host, -1);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800780 else
Pierre Ossman146ad662006-06-30 02:22:23 -0700781 sdhci_set_power(host, ios->vdd);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800782
783 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
784 if (ios->bus_width == MMC_BUS_WIDTH_4)
785 ctrl |= SDHCI_CTRL_4BITBUS;
786 else
787 ctrl &= ~SDHCI_CTRL_4BITBUS;
788 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
789
Pierre Ossman5f25a662006-10-04 02:15:39 -0700790 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -0800791 spin_unlock_irqrestore(&host->lock, flags);
792}
793
794static int sdhci_get_ro(struct mmc_host *mmc)
795{
796 struct sdhci_host *host;
797 unsigned long flags;
798 int present;
799
800 host = mmc_priv(mmc);
801
802 spin_lock_irqsave(&host->lock, flags);
803
804 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
805
806 spin_unlock_irqrestore(&host->lock, flags);
807
808 return !(present & SDHCI_WRITE_PROTECT);
809}
810
David Brownellab7aefd2006-11-12 17:55:30 -0800811static const struct mmc_host_ops sdhci_ops = {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800812 .request = sdhci_request,
813 .set_ios = sdhci_set_ios,
814 .get_ro = sdhci_get_ro,
815};
816
817/*****************************************************************************\
818 * *
819 * Tasklets *
820 * *
821\*****************************************************************************/
822
823static void sdhci_tasklet_card(unsigned long param)
824{
825 struct sdhci_host *host;
826 unsigned long flags;
827
828 host = (struct sdhci_host*)param;
829
830 spin_lock_irqsave(&host->lock, flags);
831
832 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
833 if (host->mrq) {
834 printk(KERN_ERR "%s: Card removed during transfer!\n",
835 mmc_hostname(host->mmc));
836 printk(KERN_ERR "%s: Resetting controller.\n",
837 mmc_hostname(host->mmc));
838
839 sdhci_reset(host, SDHCI_RESET_CMD);
840 sdhci_reset(host, SDHCI_RESET_DATA);
841
842 host->mrq->cmd->error = MMC_ERR_FAILED;
843 tasklet_schedule(&host->finish_tasklet);
844 }
845 }
846
847 spin_unlock_irqrestore(&host->lock, flags);
848
849 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
850}
851
852static void sdhci_tasklet_finish(unsigned long param)
853{
854 struct sdhci_host *host;
855 unsigned long flags;
856 struct mmc_request *mrq;
857
858 host = (struct sdhci_host*)param;
859
860 spin_lock_irqsave(&host->lock, flags);
861
862 del_timer(&host->timer);
863
864 mrq = host->mrq;
865
866 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
867
868 /*
869 * The controller needs a reset of internal state machines
870 * upon error conditions.
871 */
872 if ((mrq->cmd->error != MMC_ERR_NONE) ||
873 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
874 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
Pierre Ossman645289d2006-06-30 02:22:33 -0700875
876 /* Some controllers need this kick or reset won't work here */
877 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
878 unsigned int clock;
879
880 /* This is to force an update */
881 clock = host->clock;
882 host->clock = 0;
883 sdhci_set_clock(host, clock);
884 }
885
886 /* Spec says we should do both at the same time, but Ricoh
887 controllers do not like that. */
Pierre Ossmand129bce2006-03-24 03:18:17 -0800888 sdhci_reset(host, SDHCI_RESET_CMD);
889 sdhci_reset(host, SDHCI_RESET_DATA);
890 }
891
892 host->mrq = NULL;
893 host->cmd = NULL;
894 host->data = NULL;
895
896 sdhci_deactivate_led(host);
897
Pierre Ossman5f25a662006-10-04 02:15:39 -0700898 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -0800899 spin_unlock_irqrestore(&host->lock, flags);
900
901 mmc_request_done(host->mmc, mrq);
902}
903
904static void sdhci_timeout_timer(unsigned long data)
905{
906 struct sdhci_host *host;
907 unsigned long flags;
908
909 host = (struct sdhci_host*)data;
910
911 spin_lock_irqsave(&host->lock, flags);
912
913 if (host->mrq) {
914 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
915 "Please report this to " BUGMAIL ".\n",
916 mmc_hostname(host->mmc));
917 sdhci_dumpregs(host);
918
919 if (host->data) {
920 host->data->error = MMC_ERR_TIMEOUT;
921 sdhci_finish_data(host);
922 } else {
923 if (host->cmd)
924 host->cmd->error = MMC_ERR_TIMEOUT;
925 else
926 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
927
928 tasklet_schedule(&host->finish_tasklet);
929 }
930 }
931
Pierre Ossman5f25a662006-10-04 02:15:39 -0700932 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -0800933 spin_unlock_irqrestore(&host->lock, flags);
934}
935
936/*****************************************************************************\
937 * *
938 * Interrupt handling *
939 * *
940\*****************************************************************************/
941
942static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
943{
944 BUG_ON(intmask == 0);
945
946 if (!host->cmd) {
947 printk(KERN_ERR "%s: Got command interrupt even though no "
948 "command operation was in progress.\n",
949 mmc_hostname(host->mmc));
950 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
951 mmc_hostname(host->mmc));
952 sdhci_dumpregs(host);
953 return;
954 }
955
956 if (intmask & SDHCI_INT_RESPONSE)
957 sdhci_finish_command(host);
958 else {
959 if (intmask & SDHCI_INT_TIMEOUT)
960 host->cmd->error = MMC_ERR_TIMEOUT;
961 else if (intmask & SDHCI_INT_CRC)
962 host->cmd->error = MMC_ERR_BADCRC;
963 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
964 host->cmd->error = MMC_ERR_FAILED;
965 else
966 host->cmd->error = MMC_ERR_INVALID;
967
968 tasklet_schedule(&host->finish_tasklet);
969 }
970}
971
972static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
973{
974 BUG_ON(intmask == 0);
975
976 if (!host->data) {
977 /*
978 * A data end interrupt is sent together with the response
979 * for the stop command.
980 */
981 if (intmask & SDHCI_INT_DATA_END)
982 return;
983
984 printk(KERN_ERR "%s: Got data interrupt even though no "
985 "data operation was in progress.\n",
986 mmc_hostname(host->mmc));
987 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
988 mmc_hostname(host->mmc));
989 sdhci_dumpregs(host);
990
991 return;
992 }
993
994 if (intmask & SDHCI_INT_DATA_TIMEOUT)
995 host->data->error = MMC_ERR_TIMEOUT;
996 else if (intmask & SDHCI_INT_DATA_CRC)
997 host->data->error = MMC_ERR_BADCRC;
998 else if (intmask & SDHCI_INT_DATA_END_BIT)
999 host->data->error = MMC_ERR_FAILED;
1000
1001 if (host->data->error != MMC_ERR_NONE)
1002 sdhci_finish_data(host);
1003 else {
Pierre Ossmana406f5a2006-07-02 16:50:59 +01001004 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
Pierre Ossmand129bce2006-03-24 03:18:17 -08001005 sdhci_transfer_pio(host);
1006
1007 if (intmask & SDHCI_INT_DATA_END)
1008 sdhci_finish_data(host);
1009 }
1010}
1011
David Howells7d12e782006-10-05 14:55:46 +01001012static irqreturn_t sdhci_irq(int irq, void *dev_id)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001013{
1014 irqreturn_t result;
1015 struct sdhci_host* host = dev_id;
1016 u32 intmask;
1017
1018 spin_lock(&host->lock);
1019
1020 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1021
1022 if (!intmask) {
1023 result = IRQ_NONE;
1024 goto out;
1025 }
1026
1027 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1028
Pierre Ossman3192a282006-06-30 02:22:26 -07001029 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1030 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1031 host->ioaddr + SDHCI_INT_STATUS);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001032 tasklet_schedule(&host->card_tasklet);
Pierre Ossman3192a282006-06-30 02:22:26 -07001033 }
1034
1035 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001036
1037 if (intmask & SDHCI_INT_CMD_MASK) {
Pierre Ossmand129bce2006-03-24 03:18:17 -08001038 writel(intmask & SDHCI_INT_CMD_MASK,
1039 host->ioaddr + SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07001040 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001041 }
1042
1043 if (intmask & SDHCI_INT_DATA_MASK) {
Pierre Ossmand129bce2006-03-24 03:18:17 -08001044 writel(intmask & SDHCI_INT_DATA_MASK,
1045 host->ioaddr + SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07001046 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001047 }
1048
1049 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1050
Pierre Ossmand129bce2006-03-24 03:18:17 -08001051 if (intmask & SDHCI_INT_BUS_POWER) {
Pierre Ossman3192a282006-06-30 02:22:26 -07001052 printk(KERN_ERR "%s: Card is consuming too much power!\n",
Pierre Ossmand129bce2006-03-24 03:18:17 -08001053 mmc_hostname(host->mmc));
Pierre Ossman3192a282006-06-30 02:22:26 -07001054 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001055 }
1056
Pierre Ossman3192a282006-06-30 02:22:26 -07001057 intmask &= SDHCI_INT_BUS_POWER;
1058
1059 if (intmask) {
1060 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
Pierre Ossmand129bce2006-03-24 03:18:17 -08001061 "report this to " BUGMAIL ".\n",
Pierre Ossman3192a282006-06-30 02:22:26 -07001062 mmc_hostname(host->mmc), intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001063 sdhci_dumpregs(host);
1064
Pierre Ossmand129bce2006-03-24 03:18:17 -08001065 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07001066 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001067
1068 result = IRQ_HANDLED;
1069
Pierre Ossman5f25a662006-10-04 02:15:39 -07001070 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08001071out:
1072 spin_unlock(&host->lock);
1073
1074 return result;
1075}
1076
1077/*****************************************************************************\
1078 * *
1079 * Suspend/resume *
1080 * *
1081\*****************************************************************************/
1082
1083#ifdef CONFIG_PM
1084
1085static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1086{
1087 struct sdhci_chip *chip;
1088 int i, ret;
1089
1090 chip = pci_get_drvdata(pdev);
1091 if (!chip)
1092 return 0;
1093
1094 DBG("Suspending...\n");
1095
1096 for (i = 0;i < chip->num_slots;i++) {
1097 if (!chip->hosts[i])
1098 continue;
1099 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1100 if (ret) {
1101 for (i--;i >= 0;i--)
1102 mmc_resume_host(chip->hosts[i]->mmc);
1103 return ret;
1104 }
1105 }
1106
1107 pci_save_state(pdev);
1108 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1109 pci_disable_device(pdev);
1110 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1111
1112 return 0;
1113}
1114
1115static int sdhci_resume (struct pci_dev *pdev)
1116{
1117 struct sdhci_chip *chip;
1118 int i, ret;
1119
1120 chip = pci_get_drvdata(pdev);
1121 if (!chip)
1122 return 0;
1123
1124 DBG("Resuming...\n");
1125
1126 pci_set_power_state(pdev, PCI_D0);
1127 pci_restore_state(pdev);
1128 pci_enable_device(pdev);
1129
1130 for (i = 0;i < chip->num_slots;i++) {
1131 if (!chip->hosts[i])
1132 continue;
1133 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1134 pci_set_master(pdev);
1135 sdhci_init(chip->hosts[i]);
Pierre Ossman5f25a662006-10-04 02:15:39 -07001136 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08001137 ret = mmc_resume_host(chip->hosts[i]->mmc);
1138 if (ret)
1139 return ret;
1140 }
1141
1142 return 0;
1143}
1144
1145#else /* CONFIG_PM */
1146
1147#define sdhci_suspend NULL
1148#define sdhci_resume NULL
1149
1150#endif /* CONFIG_PM */
1151
1152/*****************************************************************************\
1153 * *
1154 * Device probing/removal *
1155 * *
1156\*****************************************************************************/
1157
1158static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1159{
1160 int ret;
Pierre Ossman4a965502006-06-30 02:22:29 -07001161 unsigned int version;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001162 struct sdhci_chip *chip;
1163 struct mmc_host *mmc;
1164 struct sdhci_host *host;
1165
1166 u8 first_bar;
1167 unsigned int caps;
1168
1169 chip = pci_get_drvdata(pdev);
1170 BUG_ON(!chip);
1171
1172 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1173 if (ret)
1174 return ret;
1175
1176 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1177
1178 if (first_bar > 5) {
1179 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1180 return -ENODEV;
1181 }
1182
1183 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1184 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1185 return -ENODEV;
1186 }
1187
1188 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
Pierre Ossmana98087c2006-12-07 19:17:20 +01001189 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1190 "You may experience problems.\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -08001191 }
1192
Pierre Ossman67435272006-06-30 02:22:31 -07001193 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1194 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1195 return -ENODEV;
1196 }
1197
1198 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1199 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1200 return -ENODEV;
1201 }
1202
Pierre Ossmand129bce2006-03-24 03:18:17 -08001203 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1204 if (!mmc)
1205 return -ENOMEM;
1206
1207 host = mmc_priv(mmc);
1208 host->mmc = mmc;
1209
Pierre Ossman8a4da142006-10-04 02:15:40 -07001210 host->chip = chip;
1211 chip->hosts[slot] = host;
1212
Pierre Ossmand129bce2006-03-24 03:18:17 -08001213 host->bar = first_bar + slot;
1214
1215 host->addr = pci_resource_start(pdev, host->bar);
1216 host->irq = pdev->irq;
1217
1218 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1219
1220 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1221
1222 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1223 if (ret)
1224 goto free;
1225
1226 host->ioaddr = ioremap_nocache(host->addr,
1227 pci_resource_len(pdev, host->bar));
1228 if (!host->ioaddr) {
1229 ret = -ENOMEM;
1230 goto release;
1231 }
1232
Pierre Ossmand96649e2006-06-30 02:22:30 -07001233 sdhci_reset(host, SDHCI_RESET_ALL);
1234
Pierre Ossman4a965502006-06-30 02:22:29 -07001235 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1236 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1237 if (version != 0) {
1238 printk(KERN_ERR "%s: Unknown controller version (%d). "
Pierre Ossman8b1b2182006-07-11 21:07:10 +02001239 "You may experience problems.\n", host->slot_descr,
Pierre Ossman4a965502006-06-30 02:22:29 -07001240 version);
Pierre Ossman4a965502006-06-30 02:22:29 -07001241 }
1242
Pierre Ossmand129bce2006-03-24 03:18:17 -08001243 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1244
Pierre Ossman67435272006-06-30 02:22:31 -07001245 if (debug_nodma)
1246 DBG("DMA forced off\n");
1247 else if (debug_forcedma) {
1248 DBG("DMA forced on\n");
1249 host->flags |= SDHCI_USE_DMA;
Pierre Ossman98608072006-06-30 02:22:34 -07001250 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1251 host->flags |= SDHCI_USE_DMA;
1252 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
Pierre Ossman67435272006-06-30 02:22:31 -07001253 DBG("Controller doesn't have DMA interface\n");
1254 else if (!(caps & SDHCI_CAN_DO_DMA))
1255 DBG("Controller doesn't have DMA capability\n");
1256 else
Pierre Ossmand129bce2006-03-24 03:18:17 -08001257 host->flags |= SDHCI_USE_DMA;
1258
1259 if (host->flags & SDHCI_USE_DMA) {
1260 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1261 printk(KERN_WARNING "%s: No suitable DMA available. "
1262 "Falling back to PIO.\n", host->slot_descr);
1263 host->flags &= ~SDHCI_USE_DMA;
1264 }
1265 }
1266
1267 if (host->flags & SDHCI_USE_DMA)
1268 pci_set_master(pdev);
1269 else /* XXX: Hack to get MMC layer to avoid highmem */
1270 pdev->dma_mask = 0;
1271
Pierre Ossman8ef1a142006-06-30 02:22:21 -07001272 host->max_clk =
1273 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1274 if (host->max_clk == 0) {
1275 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1276 "frequency.\n", host->slot_descr);
1277 ret = -ENODEV;
1278 goto unmap;
1279 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001280 host->max_clk *= 1000000;
1281
Pierre Ossman1c8cde92006-06-30 02:22:25 -07001282 host->timeout_clk =
1283 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1284 if (host->timeout_clk == 0) {
1285 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1286 "frequency.\n", host->slot_descr);
1287 ret = -ENODEV;
1288 goto unmap;
1289 }
1290 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1291 host->timeout_clk *= 1000;
1292
Pierre Ossmand129bce2006-03-24 03:18:17 -08001293 /*
1294 * Set host parameters.
1295 */
1296 mmc->ops = &sdhci_ops;
1297 mmc->f_min = host->max_clk / 256;
1298 mmc->f_max = host->max_clk;
Russell King42431ac2006-09-24 10:44:09 +01001299 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001300
Pierre Ossman146ad662006-06-30 02:22:23 -07001301 mmc->ocr_avail = 0;
1302 if (caps & SDHCI_CAN_VDD_330)
1303 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1304 else if (caps & SDHCI_CAN_VDD_300)
1305 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1306 else if (caps & SDHCI_CAN_VDD_180)
1307 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1308
Pierre Ossman077df882006-11-08 23:06:35 +01001309 if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
1310 printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
1311 " but no high speed support.\n",
1312 host->slot_descr);
1313 mmc->f_max = 25000000;
1314 }
1315
Pierre Ossman146ad662006-06-30 02:22:23 -07001316 if (mmc->ocr_avail == 0) {
1317 printk(KERN_ERR "%s: Hardware doesn't report any "
1318 "support voltages.\n", host->slot_descr);
1319 ret = -ENODEV;
1320 goto unmap;
1321 }
1322
Pierre Ossmand129bce2006-03-24 03:18:17 -08001323 spin_lock_init(&host->lock);
1324
1325 /*
1326 * Maximum number of segments. Hardware cannot do scatter lists.
1327 */
1328 if (host->flags & SDHCI_USE_DMA)
1329 mmc->max_hw_segs = 1;
1330 else
1331 mmc->max_hw_segs = 16;
1332 mmc->max_phys_segs = 16;
1333
1334 /*
Pierre Ossmanbab76962006-07-02 16:51:35 +01001335 * Maximum number of sectors in one transfer. Limited by DMA boundary
Pierre Ossman55db8902006-11-21 17:55:45 +01001336 * size (512KiB).
Pierre Ossmand129bce2006-03-24 03:18:17 -08001337 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001338 mmc->max_req_size = 524288;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001339
1340 /*
1341 * Maximum segment size. Could be one segment with the maximum number
Pierre Ossman55db8902006-11-21 17:55:45 +01001342 * of bytes.
Pierre Ossmand129bce2006-03-24 03:18:17 -08001343 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001344 mmc->max_seg_size = mmc->max_req_size;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001345
1346 /*
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001347 * Maximum block size. This varies from controller to controller and
1348 * is specified in the capabilities register.
1349 */
1350 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1351 if (mmc->max_blk_size >= 3) {
1352 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1353 host->slot_descr);
1354 ret = -ENODEV;
1355 goto unmap;
1356 }
1357 mmc->max_blk_size = 512 << mmc->max_blk_size;
1358
1359 /*
Pierre Ossman55db8902006-11-21 17:55:45 +01001360 * Maximum block count.
1361 */
1362 mmc->max_blk_count = 65535;
1363
1364 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08001365 * Init tasklets.
1366 */
1367 tasklet_init(&host->card_tasklet,
1368 sdhci_tasklet_card, (unsigned long)host);
1369 tasklet_init(&host->finish_tasklet,
1370 sdhci_tasklet_finish, (unsigned long)host);
1371
Al Viroe4cad1b2006-10-10 22:47:07 +01001372 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001373
Thomas Gleixnerdace1452006-07-01 19:29:38 -07001374 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
Pierre Ossmand129bce2006-03-24 03:18:17 -08001375 host->slot_descr, host);
1376 if (ret)
Pierre Ossman8ef1a142006-06-30 02:22:21 -07001377 goto untasklet;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001378
1379 sdhci_init(host);
1380
1381#ifdef CONFIG_MMC_DEBUG
1382 sdhci_dumpregs(host);
1383#endif
1384
Pierre Ossman5f25a662006-10-04 02:15:39 -07001385 mmiowb();
1386
Pierre Ossmand129bce2006-03-24 03:18:17 -08001387 mmc_add_host(mmc);
1388
1389 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1390 host->addr, host->irq,
1391 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1392
1393 return 0;
1394
Pierre Ossman8ef1a142006-06-30 02:22:21 -07001395untasklet:
Pierre Ossmand129bce2006-03-24 03:18:17 -08001396 tasklet_kill(&host->card_tasklet);
1397 tasklet_kill(&host->finish_tasklet);
Pierre Ossman8ef1a142006-06-30 02:22:21 -07001398unmap:
Pierre Ossmand129bce2006-03-24 03:18:17 -08001399 iounmap(host->ioaddr);
1400release:
1401 pci_release_region(pdev, host->bar);
1402free:
1403 mmc_free_host(mmc);
1404
1405 return ret;
1406}
1407
1408static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1409{
1410 struct sdhci_chip *chip;
1411 struct mmc_host *mmc;
1412 struct sdhci_host *host;
1413
1414 chip = pci_get_drvdata(pdev);
1415 host = chip->hosts[slot];
1416 mmc = host->mmc;
1417
1418 chip->hosts[slot] = NULL;
1419
1420 mmc_remove_host(mmc);
1421
1422 sdhci_reset(host, SDHCI_RESET_ALL);
1423
1424 free_irq(host->irq, host);
1425
1426 del_timer_sync(&host->timer);
1427
1428 tasklet_kill(&host->card_tasklet);
1429 tasklet_kill(&host->finish_tasklet);
1430
1431 iounmap(host->ioaddr);
1432
1433 pci_release_region(pdev, host->bar);
1434
1435 mmc_free_host(mmc);
1436}
1437
1438static int __devinit sdhci_probe(struct pci_dev *pdev,
1439 const struct pci_device_id *ent)
1440{
1441 int ret, i;
Pierre Ossman51f82bc2006-06-30 02:22:22 -07001442 u8 slots, rev;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001443 struct sdhci_chip *chip;
1444
1445 BUG_ON(pdev == NULL);
1446 BUG_ON(ent == NULL);
1447
Pierre Ossman51f82bc2006-06-30 02:22:22 -07001448 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1449
1450 printk(KERN_INFO DRIVER_NAME
1451 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1452 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1453 (int)rev);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001454
1455 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1456 if (ret)
1457 return ret;
1458
1459 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1460 DBG("found %d slot(s)\n", slots);
1461 if (slots == 0)
1462 return -ENODEV;
1463
1464 ret = pci_enable_device(pdev);
1465 if (ret)
1466 return ret;
1467
1468 chip = kzalloc(sizeof(struct sdhci_chip) +
1469 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1470 if (!chip) {
1471 ret = -ENOMEM;
1472 goto err;
1473 }
1474
1475 chip->pdev = pdev;
Pierre Ossmandf673b22006-06-30 02:22:31 -07001476 chip->quirks = ent->driver_data;
1477
1478 if (debug_quirks)
1479 chip->quirks = debug_quirks;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001480
1481 chip->num_slots = slots;
1482 pci_set_drvdata(pdev, chip);
1483
1484 for (i = 0;i < slots;i++) {
1485 ret = sdhci_probe_slot(pdev, i);
1486 if (ret) {
1487 for (i--;i >= 0;i--)
1488 sdhci_remove_slot(pdev, i);
1489 goto free;
1490 }
1491 }
1492
1493 return 0;
1494
1495free:
1496 pci_set_drvdata(pdev, NULL);
1497 kfree(chip);
1498
1499err:
1500 pci_disable_device(pdev);
1501 return ret;
1502}
1503
1504static void __devexit sdhci_remove(struct pci_dev *pdev)
1505{
1506 int i;
1507 struct sdhci_chip *chip;
1508
1509 chip = pci_get_drvdata(pdev);
1510
1511 if (chip) {
1512 for (i = 0;i < chip->num_slots;i++)
1513 sdhci_remove_slot(pdev, i);
1514
1515 pci_set_drvdata(pdev, NULL);
1516
1517 kfree(chip);
1518 }
1519
1520 pci_disable_device(pdev);
1521}
1522
1523static struct pci_driver sdhci_driver = {
1524 .name = DRIVER_NAME,
1525 .id_table = pci_ids,
1526 .probe = sdhci_probe,
1527 .remove = __devexit_p(sdhci_remove),
1528 .suspend = sdhci_suspend,
1529 .resume = sdhci_resume,
1530};
1531
1532/*****************************************************************************\
1533 * *
1534 * Driver init/exit *
1535 * *
1536\*****************************************************************************/
1537
1538static int __init sdhci_drv_init(void)
1539{
1540 printk(KERN_INFO DRIVER_NAME
1541 ": Secure Digital Host Controller Interface driver, "
1542 DRIVER_VERSION "\n");
1543 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1544
1545 return pci_register_driver(&sdhci_driver);
1546}
1547
1548static void __exit sdhci_drv_exit(void)
1549{
1550 DBG("Exiting\n");
1551
1552 pci_unregister_driver(&sdhci_driver);
1553}
1554
1555module_init(sdhci_drv_init);
1556module_exit(sdhci_drv_exit);
1557
Pierre Ossman67435272006-06-30 02:22:31 -07001558module_param(debug_nodma, uint, 0444);
1559module_param(debug_forcedma, uint, 0444);
Pierre Ossmandf673b22006-06-30 02:22:31 -07001560module_param(debug_quirks, uint, 0444);
Pierre Ossman67435272006-06-30 02:22:31 -07001561
Pierre Ossmand129bce2006-03-24 03:18:17 -08001562MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1563MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1564MODULE_VERSION(DRIVER_VERSION);
1565MODULE_LICENSE("GPL");
Pierre Ossman67435272006-06-30 02:22:31 -07001566
1567MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1568MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
Pierre Ossmandf673b22006-06-30 02:22:31 -07001569MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");