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Kukjin Kim83014572011-11-06 13:54:56 +09001/* linux/arch/arm/mach-exynos/include/mach/map.h
Kukjin Kim7d30e8b2011-02-14 16:33:10 +09002 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
Kukjin Kim56b20922011-08-20 13:41:21 +090026#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090028
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +090029#define EXYNOS4_PA_FIMC0 0x11800000
30#define EXYNOS4_PA_FIMC1 0x11810000
31#define EXYNOS4_PA_FIMC2 0x11820000
32#define EXYNOS4_PA_FIMC3 0x11830000
33
Kamil Debski561ab532011-12-27 17:16:44 +090034#define EXYNOS4_PA_G2D 0x12800000
35
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090036#define EXYNOS4_PA_I2S0 0x03830000
37#define EXYNOS4_PA_I2S1 0xE3100000
38#define EXYNOS4_PA_I2S2 0xE2A00000
39
40#define EXYNOS4_PA_PCM0 0x03840000
41#define EXYNOS4_PA_PCM1 0x13980000
42#define EXYNOS4_PA_PCM2 0x13990000
43
44#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
45
46#define EXYNOS4_PA_ONENAND 0x0C000000
47#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
48
49#define EXYNOS4_PA_CHIPID 0x10000000
50
51#define EXYNOS4_PA_SYSCON 0x10010000
52#define EXYNOS4_PA_PMU 0x10020000
53#define EXYNOS4_PA_CMU 0x10030000
54
Changhwan Youn2b740152011-03-11 10:39:35 +090055#define EXYNOS4_PA_SYSTIMER 0x10050000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090056#define EXYNOS4_PA_WATCHDOG 0x10060000
57#define EXYNOS4_PA_RTC 0x10070000
58
Naveen Krishna Ch344021c2011-03-05 09:48:31 +090059#define EXYNOS4_PA_KEYPAD 0x100A0000
60
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090061#define EXYNOS4_PA_DMC0 0x10400000
62
Changhwan Youneb13f2b2011-07-16 10:48:47 +090063#define EXYNOS4_PA_COMBINER 0x10440000
64
65#define EXYNOS4_PA_GIC_CPU 0x10480000
66#define EXYNOS4_PA_GIC_DIST 0x10490000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090067
68#define EXYNOS4_PA_COREPERI 0x10500000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090069#define EXYNOS4_PA_TWD 0x10500600
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090070#define EXYNOS4_PA_L2CC 0x10502000
71
72#define EXYNOS4_PA_MDMA 0x10810000
73#define EXYNOS4_PA_PDMA0 0x12680000
74#define EXYNOS4_PA_PDMA1 0x12690000
75
76#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
77#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
78#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
79#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
80#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
81#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
82#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
83#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
84#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
85#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
86#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
87#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
88#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
89#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
90#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
91#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
Padmavathi Venna74ac23a2011-12-26 16:42:15 +090092#define EXYNOS4_PA_SPI0 0x13920000
93#define EXYNOS4_PA_SPI1 0x13930000
94#define EXYNOS4_PA_SPI2 0x13940000
95
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090096
97#define EXYNOS4_PA_GPIO1 0x11400000
98#define EXYNOS4_PA_GPIO2 0x11000000
99#define EXYNOS4_PA_GPIO3 0x03860000
100
101#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
102#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
103
Jonghun Han1aee2ad2011-07-21 15:46:19 +0900104#define EXYNOS4_PA_FIMD0 0x11C00000
105
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900106#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
Seungwon Jeond7919582011-07-21 00:34:58 +0900107#define EXYNOS4_PA_DWMCI 0x12550000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900108
Abhilash Kesavan40360212011-03-15 18:35:24 +0900109#define EXYNOS4_PA_SATA 0x12560000
110#define EXYNOS4_PA_SATAPHY 0x125D0000
111#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
112
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900113#define EXYNOS4_PA_SROMC 0x12570000
114
Joonyoung Shim3e112662011-04-08 13:22:09 +0900115#define EXYNOS4_PA_EHCI 0x12580000
Jingoo Han6e7eb1702011-12-23 11:19:36 +0900116#define EXYNOS4_PA_OHCI 0x12590000
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900117#define EXYNOS4_PA_HSPHY 0x125B0000
Kamil Debski0f75a962011-07-21 16:42:30 +0900118#define EXYNOS4_PA_MFC 0x13400000
Joonyoung Shim3e112662011-04-08 13:22:09 +0900119
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900120#define EXYNOS4_PA_UART 0x13800000
121
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +0900122#define EXYNOS4_PA_VP 0x12C00000
123#define EXYNOS4_PA_MIXER 0x12C10000
124#define EXYNOS4_PA_SDO 0x12C20000
125#define EXYNOS4_PA_HDMI 0x12D00000
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900126#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
127
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900128#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
129
MyungJoo Ham0e9e5262011-07-20 21:08:18 +0900130#define EXYNOS4_PA_ADC 0x13910000
131#define EXYNOS4_PA_ADC1 0x13911000
132
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900133#define EXYNOS4_PA_AC97 0x139A0000
134
Seungwhan Youn4dd508b2011-03-08 10:56:55 +0900135#define EXYNOS4_PA_SPDIF 0x139B0000
136
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900137#define EXYNOS4_PA_TIMER 0x139D0000
138
139#define EXYNOS4_PA_SDRAM 0x40000000
140
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900141/* Compatibiltiy Defines */
142
143#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
144#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
145#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
146#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
147#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
148#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
149#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
150#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
151#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
152#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
153#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
154#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
155#define S3C_PA_RTC EXYNOS4_PA_RTC
156#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
Kukjin Kim83014572011-11-06 13:54:56 +0900157#define S3C_PA_UART EXYNOS4_PA_UART
Padmavathi Venna74ac23a2011-12-26 16:42:15 +0900158#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
159#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
160#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900161
Kukjin Kim83014572011-11-06 13:54:56 +0900162#define S5P_PA_EHCI EXYNOS4_PA_EHCI
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900163#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
164#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
165#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
166#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
Kamil Debski561ab532011-12-27 17:16:44 +0900167#define S5P_PA_G2D EXYNOS4_PA_G2D
Jonghun Han1aee2ad2011-07-21 15:46:19 +0900168#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +0900169#define S5P_PA_HDMI EXYNOS4_PA_HDMI
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900170#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
Kukjin Kim83014572011-11-06 13:54:56 +0900171#define S5P_PA_MFC EXYNOS4_PA_MFC
172#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
173#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
174#define S5P_PA_MIXER EXYNOS4_PA_MIXER
175#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
176#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
177#define S5P_PA_SDO EXYNOS4_PA_SDO
178#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
Kukjin Kim83014572011-11-06 13:54:56 +0900179#define S5P_PA_VP EXYNOS4_PA_VP
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900180
Kukjin Kim83014572011-11-06 13:54:56 +0900181#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
182#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
Naveen Krishna Ch344021c2011-03-05 09:48:31 +0900183#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
184
Kukjin Kim83014572011-11-06 13:54:56 +0900185/* Compatibility UART */
186
187#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900188
Kukjin Kimcc511b82011-12-27 08:18:36 +0100189#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900190#define S5P_PA_UART0 S5P_PA_UART(0)
191#define S5P_PA_UART1 S5P_PA_UART(1)
192#define S5P_PA_UART2 S5P_PA_UART(2)
193#define S5P_PA_UART3 S5P_PA_UART(3)
194#define S5P_PA_UART4 S5P_PA_UART(4)
195
196#define S5P_SZ_UART SZ_256
197
198#endif /* __ASM_ARCH_MAP_H */