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Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001/*
Peter Ujfalusi71e822e2012-01-26 12:47:22 +02002 * sound/soc/omap/mcbsp.c
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01003 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
Peter Ujfalusi71e822e2012-01-26 12:47:22 +02007 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +030020#include <linux/platform_device.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010021#include <linux/interrupt.h>
22#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000023#include <linux/clk.h>
Tony Lindgren04fbf6a2007-02-12 10:50:53 -080024#include <linux/delay.h>
Eduardo Valentinfb78d802008-07-03 12:24:39 +030025#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090026#include <linux/slab.h>
Peter Ujfalusif1991312012-08-16 16:41:00 +030027#include <linux/pm_runtime.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010028
Arnd Bergmann22037472012-08-24 15:21:06 +020029#include <linux/platform_data/asoc-ti-mcbsp.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010030
Peter Ujfalusi219f4312012-02-03 13:11:47 +020031#include "mcbsp.h"
32
Manjunath Kondaiah Gb0a330d2010-10-08 10:00:19 -070033static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
Chandra Shekharb4b58f52008-10-08 10:01:39 +030034{
Jarkko Nikulacdc715142011-09-26 10:45:39 +030035 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
36
37 if (mcbsp->pdata->reg_size == 2) {
38 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
Victor Kamensky1b488a42013-11-16 02:01:19 +020039 writew_relaxed((u16)val, addr);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080040 } else {
Jarkko Nikulacdc715142011-09-26 10:45:39 +030041 ((u32 *)mcbsp->reg_cache)[reg] = val;
Victor Kamensky1b488a42013-11-16 02:01:19 +020042 writel_relaxed(val, addr);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080043 }
Chandra Shekharb4b58f52008-10-08 10:01:39 +030044}
45
Manjunath Kondaiah Gb0a330d2010-10-08 10:00:19 -070046static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
Chandra Shekharb4b58f52008-10-08 10:01:39 +030047{
Jarkko Nikulacdc715142011-09-26 10:45:39 +030048 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
49
50 if (mcbsp->pdata->reg_size == 2) {
Victor Kamensky1b488a42013-11-16 02:01:19 +020051 return !from_cache ? readw_relaxed(addr) :
Jarkko Nikulacdc715142011-09-26 10:45:39 +030052 ((u16 *)mcbsp->reg_cache)[reg];
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080053 } else {
Victor Kamensky1b488a42013-11-16 02:01:19 +020054 return !from_cache ? readl_relaxed(addr) :
Jarkko Nikulacdc715142011-09-26 10:45:39 +030055 ((u32 *)mcbsp->reg_cache)[reg];
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080056 }
Chandra Shekharb4b58f52008-10-08 10:01:39 +030057}
58
Manjunath Kondaiah Gb0a330d2010-10-08 10:00:19 -070059static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
Eero Nurkkalad912fa92010-02-22 12:21:11 +000060{
Victor Kamensky1b488a42013-11-16 02:01:19 +020061 writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
Eero Nurkkalad912fa92010-02-22 12:21:11 +000062}
63
Manjunath Kondaiah Gb0a330d2010-10-08 10:00:19 -070064static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
Eero Nurkkalad912fa92010-02-22 12:21:11 +000065{
Victor Kamensky1b488a42013-11-16 02:01:19 +020066 return readl_relaxed(mcbsp->st_data->io_base_st + reg);
Eero Nurkkalad912fa92010-02-22 12:21:11 +000067}
Eero Nurkkalad912fa92010-02-22 12:21:11 +000068
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080069#define MCBSP_READ(mcbsp, reg) \
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080070 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080071#define MCBSP_WRITE(mcbsp, reg, val) \
72 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -080073#define MCBSP_READ_CACHE(mcbsp, reg) \
74 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
Chandra Shekharb4b58f52008-10-08 10:01:39 +030075
Eero Nurkkalad912fa92010-02-22 12:21:11 +000076#define MCBSP_ST_READ(mcbsp, reg) \
77 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
78#define MCBSP_ST_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
80
Peter Ujfalusi45656b42012-02-14 18:20:58 +020081static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010082{
Chandra Shekharb4b58f52008-10-08 10:01:39 +030083 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
84 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080085 MCBSP_READ(mcbsp, DRR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030086 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080087 MCBSP_READ(mcbsp, DRR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030088 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080089 MCBSP_READ(mcbsp, DXR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030090 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080091 MCBSP_READ(mcbsp, DXR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030092 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080093 MCBSP_READ(mcbsp, SPCR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030094 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080095 MCBSP_READ(mcbsp, SPCR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030096 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080097 MCBSP_READ(mcbsp, RCR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +030098 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -080099 MCBSP_READ(mcbsp, RCR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300100 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800101 MCBSP_READ(mcbsp, XCR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300102 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800103 MCBSP_READ(mcbsp, XCR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300104 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800105 MCBSP_READ(mcbsp, SRGR2));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300106 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800107 MCBSP_READ(mcbsp, SRGR1));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300108 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800109 MCBSP_READ(mcbsp, PCR0));
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300110 dev_dbg(mcbsp->dev, "***********************\n");
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100111}
112
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200113static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
114{
115 struct omap_mcbsp *mcbsp = dev_id;
116 u16 irqst;
117
118 irqst = MCBSP_READ(mcbsp, IRQST);
119 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
120
121 if (irqst & RSYNCERREN)
122 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
123 if (irqst & RFSREN)
124 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
125 if (irqst & REOFEN)
126 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
127 if (irqst & RRDYEN)
128 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
129 if (irqst & RUNDFLEN)
130 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
131 if (irqst & ROVFLEN)
132 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
133
134 if (irqst & XSYNCERREN)
135 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
136 if (irqst & XFSXEN)
137 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
138 if (irqst & XEOFEN)
139 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
140 if (irqst & XRDYEN)
141 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
142 if (irqst & XUNDFLEN)
143 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
144 if (irqst & XOVFLEN)
145 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
146 if (irqst & XEMPTYEOFEN)
147 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
148
149 MCBSP_WRITE(mcbsp, IRQST, irqst);
150
151 return IRQ_HANDLED;
152}
153
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700154static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100155{
Jeff Garzike8f2af12007-10-26 05:40:25 -0400156 struct omap_mcbsp *mcbsp_tx = dev_id;
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700157 u16 irqst_spcr2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100158
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800159 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700160 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100161
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700162 if (irqst_spcr2 & XSYNC_ERR) {
163 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
164 irqst_spcr2);
165 /* Writing zero to XSYNC_ERR clears the IRQ */
Janusz Krzysztofik0841cb82010-02-23 15:50:38 +0000166 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700167 }
Eduardo Valentinfb78d802008-07-03 12:24:39 +0300168
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100169 return IRQ_HANDLED;
170}
171
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700172static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100173{
Jeff Garzike8f2af12007-10-26 05:40:25 -0400174 struct omap_mcbsp *mcbsp_rx = dev_id;
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700175 u16 irqst_spcr1;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100176
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800177 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700178 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100179
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700180 if (irqst_spcr1 & RSYNC_ERR) {
181 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
182 irqst_spcr1);
183 /* Writing zero to RSYNC_ERR clears the IRQ */
Janusz Krzysztofik0841cb82010-02-23 15:50:38 +0000184 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
Eero Nurkkalad6d834b2009-05-25 11:08:42 -0700185 }
Eduardo Valentinfb78d802008-07-03 12:24:39 +0300186
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100187 return IRQ_HANDLED;
188}
189
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100190/*
191 * omap_mcbsp_config simply write a config to the
192 * appropriate McBSP.
193 * You either call this function or set the McBSP registers
194 * by yourself before calling omap_mcbsp_start().
195 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200196void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
197 const struct omap_mcbsp_reg_cfg *config)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100198{
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300199 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
200 mcbsp->id, mcbsp->phys_base);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100201
202 /* We write the given config */
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800203 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
204 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
205 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
206 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
207 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
208 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
209 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
210 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
211 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
212 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
213 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
Jarkko Nikula88408232011-09-26 10:45:41 +0300214 if (mcbsp->pdata->has_ccr) {
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800215 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
216 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
Tony Lindgren3127f8f2009-01-15 13:09:54 +0200217 }
Peter Ujfalusi08905d82012-03-05 11:27:40 +0200218 /* Enable wakeup behavior */
219 if (mcbsp->pdata->has_wakeup)
220 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200221
222 /* Enable TX/RX sync error interrupts by default */
223 if (mcbsp->irq)
224 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100225}
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100226
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530227/**
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530228 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
229 * @id - mcbsp id
230 * @stream - indicates the direction of data flow (rx or tx)
231 *
232 * Returns the address of mcbsp data transmit register or data receive register
233 * to be used by DMA for transferring/receiving data based on the value of
234 * @stream for the requested mcbsp given by @id
235 */
Peter Ujfalusib8fb4902012-02-14 15:41:29 +0200236static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
237 unsigned int stream)
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530238{
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530239 int data_reg;
240
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300241 if (mcbsp->pdata->reg_size == 2) {
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530242 if (stream)
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300243 data_reg = OMAP_MCBSP_REG_DRR1;
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530244 else
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300245 data_reg = OMAP_MCBSP_REG_DXR1;
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530246 } else {
247 if (stream)
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300248 data_reg = OMAP_MCBSP_REG_DRR;
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530249 else
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300250 data_reg = OMAP_MCBSP_REG_DXR;
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530251 }
252
Jarkko Nikulacdc715142011-09-26 10:45:39 +0300253 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530254}
Kishon Vijay Abraham I9504ba62011-02-24 15:16:55 +0530255
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000256static void omap_st_on(struct omap_mcbsp *mcbsp)
257{
258 unsigned int w;
259
Jarkko Nikula1743d142011-09-26 10:45:44 +0300260 if (mcbsp->pdata->enable_st_clock)
261 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000262
263 /* Enable McBSP Sidetone */
264 w = MCBSP_READ(mcbsp, SSELCR);
265 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
266
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000267 /* Enable Sidetone from Sidetone Core */
268 w = MCBSP_ST_READ(mcbsp, SSELCR);
269 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
270}
271
272static void omap_st_off(struct omap_mcbsp *mcbsp)
273{
274 unsigned int w;
275
276 w = MCBSP_ST_READ(mcbsp, SSELCR);
277 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
278
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000279 w = MCBSP_READ(mcbsp, SSELCR);
280 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
281
Jarkko Nikula1743d142011-09-26 10:45:44 +0300282 if (mcbsp->pdata->enable_st_clock)
283 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000284}
285
286static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
287{
288 u16 val, i;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000289
290 val = MCBSP_ST_READ(mcbsp, SSELCR);
291
292 if (val & ST_COEFFWREN)
293 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
294
295 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
296
297 for (i = 0; i < 128; i++)
298 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
299
300 i = 0;
301
302 val = MCBSP_ST_READ(mcbsp, SSELCR);
303 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
304 val = MCBSP_ST_READ(mcbsp, SSELCR);
305
306 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
307
308 if (i == 1000)
309 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
310}
311
312static void omap_st_chgain(struct omap_mcbsp *mcbsp)
313{
314 u16 w;
315 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000316
317 w = MCBSP_ST_READ(mcbsp, SSELCR);
318
319 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
320 ST_CH1GAIN(st_data->ch1gain));
321}
322
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200323int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000324{
Peter Ujfalusie2002ab2012-02-23 15:38:37 +0200325 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000326 int ret = 0;
327
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000328 if (!st_data)
329 return -ENOENT;
330
331 spin_lock_irq(&mcbsp->lock);
332 if (channel == 0)
333 st_data->ch0gain = chgain;
334 else if (channel == 1)
335 st_data->ch1gain = chgain;
336 else
337 ret = -EINVAL;
338
339 if (st_data->enabled)
340 omap_st_chgain(mcbsp);
341 spin_unlock_irq(&mcbsp->lock);
342
343 return ret;
344}
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000345
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200346int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000347{
Peter Ujfalusie2002ab2012-02-23 15:38:37 +0200348 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000349 int ret = 0;
350
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000351 if (!st_data)
352 return -ENOENT;
353
354 spin_lock_irq(&mcbsp->lock);
355 if (channel == 0)
356 *chgain = st_data->ch0gain;
357 else if (channel == 1)
358 *chgain = st_data->ch1gain;
359 else
360 ret = -EINVAL;
361 spin_unlock_irq(&mcbsp->lock);
362
363 return ret;
364}
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000365
366static int omap_st_start(struct omap_mcbsp *mcbsp)
367{
368 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
369
Peter Ujfalusi58db1dc2012-02-23 15:40:55 +0200370 if (st_data->enabled && !st_data->running) {
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000371 omap_st_fir_write(mcbsp, st_data->taps);
372 omap_st_chgain(mcbsp);
373
374 if (!mcbsp->free) {
375 omap_st_on(mcbsp);
376 st_data->running = 1;
377 }
378 }
379
380 return 0;
381}
382
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200383int omap_st_enable(struct omap_mcbsp *mcbsp)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000384{
Peter Ujfalusie2002ab2012-02-23 15:38:37 +0200385 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000386
387 if (!st_data)
388 return -ENODEV;
389
390 spin_lock_irq(&mcbsp->lock);
391 st_data->enabled = 1;
392 omap_st_start(mcbsp);
393 spin_unlock_irq(&mcbsp->lock);
394
395 return 0;
396}
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000397
398static int omap_st_stop(struct omap_mcbsp *mcbsp)
399{
400 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
401
Peter Ujfalusi58db1dc2012-02-23 15:40:55 +0200402 if (st_data->running) {
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000403 if (!mcbsp->free) {
404 omap_st_off(mcbsp);
405 st_data->running = 0;
406 }
407 }
408
409 return 0;
410}
411
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200412int omap_st_disable(struct omap_mcbsp *mcbsp)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000413{
Peter Ujfalusie2002ab2012-02-23 15:38:37 +0200414 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000415 int ret = 0;
416
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000417 if (!st_data)
418 return -ENODEV;
419
420 spin_lock_irq(&mcbsp->lock);
421 omap_st_stop(mcbsp);
422 st_data->enabled = 0;
423 spin_unlock_irq(&mcbsp->lock);
424
425 return ret;
426}
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000427
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200428int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000429{
Peter Ujfalusie2002ab2012-02-23 15:38:37 +0200430 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000431
432 if (!st_data)
433 return -ENODEV;
434
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000435 return st_data->enabled;
436}
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000437
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300438/*
Peter Ujfalusi451fd822010-06-03 07:39:33 +0300439 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
440 * The threshold parameter is 1 based, and it is converted (threshold - 1)
441 * for the THRSH2 register.
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300442 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200443void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300444{
Jarkko Nikula7bba67a2011-09-26 10:45:42 +0300445 if (mcbsp->pdata->buffer_size == 0)
446 return;
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300447
Peter Ujfalusi451fd822010-06-03 07:39:33 +0300448 if (threshold && threshold <= mcbsp->max_tx_thres)
449 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300450}
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300451
452/*
Peter Ujfalusi451fd822010-06-03 07:39:33 +0300453 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
454 * The threshold parameter is 1 based, and it is converted (threshold - 1)
455 * for the THRSH1 register.
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300456 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200457void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300458{
Jarkko Nikula7bba67a2011-09-26 10:45:42 +0300459 if (mcbsp->pdata->buffer_size == 0)
460 return;
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300461
Peter Ujfalusi451fd822010-06-03 07:39:33 +0300462 if (threshold && threshold <= mcbsp->max_rx_thres)
463 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
Eduardo Valentin7aa9ff52009-08-20 16:18:10 +0300464}
Eduardo Valentina1a56f5f2009-08-20 16:18:11 +0300465
466/*
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200467 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
468 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200469u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200470{
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200471 u16 buffstat;
472
Jarkko Nikula7bba67a2011-09-26 10:45:42 +0300473 if (mcbsp->pdata->buffer_size == 0)
474 return 0;
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200475
476 /* Returns the number of free locations in the buffer */
477 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
478
479 /* Number of slots are different in McBSP ports */
Peter Ujfalusif10b8ad2010-06-03 07:39:34 +0300480 return mcbsp->pdata->buffer_size - buffstat;
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200481}
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200482
483/*
484 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
485 * to reach the threshold value (when the DMA will be triggered to read it)
486 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200487u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200488{
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200489 u16 buffstat, threshold;
490
Jarkko Nikula7bba67a2011-09-26 10:45:42 +0300491 if (mcbsp->pdata->buffer_size == 0)
492 return 0;
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200493
494 /* Returns the number of used locations in the buffer */
495 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
496 /* RX threshold */
497 threshold = MCBSP_READ(mcbsp, THRSH1);
498
499 /* Return the number of location till we reach the threshold limit */
500 if (threshold <= buffstat)
501 return 0;
502 else
503 return threshold - buffstat;
504}
Peter Ujfalusi7dc976e2010-03-03 15:08:08 +0200505
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200506int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100507{
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800508 void *reg_cache;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100509 int err;
510
Jarkko Nikulaac6747ca2011-09-26 10:45:43 +0300511 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800512 if (!reg_cache) {
513 return -ENOMEM;
514 }
515
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300516 spin_lock(&mcbsp->lock);
517 if (!mcbsp->free) {
518 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
519 mcbsp->id);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800520 err = -EBUSY;
521 goto err_kfree;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100522 }
523
Shubhrajyoti D6722a722010-12-07 16:25:41 -0800524 mcbsp->free = false;
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800525 mcbsp->reg_cache = reg_cache;
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300526 spin_unlock(&mcbsp->lock);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100527
Russell Kingb820ce42009-01-23 10:26:46 +0000528 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200529 mcbsp->pdata->ops->request(mcbsp->id - 1);
Russell Kingb820ce42009-01-23 10:26:46 +0000530
Jarkko Nikula5a070552008-10-08 10:01:41 +0300531 /*
532 * Make sure that transmitter, receiver and sample-rate generator are
533 * not running before activating IRQs.
534 */
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800535 MCBSP_WRITE(mcbsp, SPCR1, 0);
536 MCBSP_WRITE(mcbsp, SPCR2, 0);
Jarkko Nikula5a070552008-10-08 10:01:41 +0300537
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200538 if (mcbsp->irq) {
539 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
540 "McBSP", (void *)mcbsp);
Jarkko Nikulabafe2722011-06-14 11:23:52 +0000541 if (err != 0) {
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200542 dev_err(mcbsp->dev, "Unable to request IRQ\n");
543 goto err_clk_disable;
544 }
545 } else {
546 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
547 "McBSP TX", (void *)mcbsp);
548 if (err != 0) {
549 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
550 goto err_clk_disable;
551 }
552
553 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
554 "McBSP RX", (void *)mcbsp);
555 if (err != 0) {
556 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
Jarkko Nikulabafe2722011-06-14 11:23:52 +0000557 goto err_free_irq;
Tony Lindgren120db2c2006-04-02 17:46:27 +0100558 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100559 }
560
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100561 return 0;
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800562err_free_irq:
Janusz Krzysztofik1866b542010-01-08 10:29:04 -0800563 free_irq(mcbsp->tx_irq, (void *)mcbsp);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800564err_clk_disable:
Janusz Krzysztofik1866b542010-01-08 10:29:04 -0800565 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200566 mcbsp->pdata->ops->free(mcbsp->id - 1);
Janusz Krzysztofik1866b542010-01-08 10:29:04 -0800567
Jarkko Nikula1a645882011-09-26 10:45:40 +0300568 /* Disable wakeup behavior */
569 if (mcbsp->pdata->has_wakeup)
570 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
Janusz Krzysztofik1866b542010-01-08 10:29:04 -0800571
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800572 spin_lock(&mcbsp->lock);
Shubhrajyoti D6722a722010-12-07 16:25:41 -0800573 mcbsp->free = true;
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800574 mcbsp->reg_cache = NULL;
575err_kfree:
576 spin_unlock(&mcbsp->lock);
577 kfree(reg_cache);
Janusz Krzysztofik1866b542010-01-08 10:29:04 -0800578
579 return err;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100580}
581
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200582void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100583{
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800584 void *reg_cache;
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300585
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300586 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200587 mcbsp->pdata->ops->free(mcbsp->id - 1);
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +0300588
Jarkko Nikula1a645882011-09-26 10:45:40 +0300589 /* Disable wakeup behavior */
590 if (mcbsp->pdata->has_wakeup)
591 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
Eero Nurkkala2122fdc2009-08-20 16:18:15 +0300592
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200593 /* Disable interrupt requests */
594 if (mcbsp->irq)
595 MCBSP_WRITE(mcbsp, IRQEN, 0);
596
597 if (mcbsp->irq) {
598 free_irq(mcbsp->irq, (void *)mcbsp);
599 } else {
Jarkko Nikulabafe2722011-06-14 11:23:52 +0000600 free_irq(mcbsp->rx_irq, (void *)mcbsp);
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200601 free_irq(mcbsp->tx_irq, (void *)mcbsp);
602 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100603
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800604 reg_cache = mcbsp->reg_cache;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100605
Peter Ujfalusie3866152012-03-05 11:32:27 +0200606 /*
607 * Select CLKS source from internal source unconditionally before
608 * marking the McBSP port as free.
609 * If the external clock source via MCBSP_CLKS pin has been selected the
610 * system will refuse to enter idle if the CLKS pin source is not reset
611 * back to internal source.
612 */
Tony Lindgrene6507942012-11-21 09:42:25 -0800613 if (!mcbsp_omap1())
Peter Ujfalusie3866152012-03-05 11:32:27 +0200614 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
615
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800616 spin_lock(&mcbsp->lock);
617 if (mcbsp->free)
618 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
619 else
Shubhrajyoti D6722a722010-12-07 16:25:41 -0800620 mcbsp->free = true;
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800621 mcbsp->reg_cache = NULL;
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300622 spin_unlock(&mcbsp->lock);
Janusz Krzysztofikc8c99692010-02-15 10:03:33 -0800623
Markus Elfringbb66f2d2014-11-17 14:05:27 +0100624 kfree(reg_cache);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100625}
626
627/*
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300628 * Here we start the McBSP, by enabling transmitter, receiver or both.
629 * If no transmitter or receiver is active prior calling, then sample-rate
630 * generator and frame sync are started.
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100631 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200632void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100633{
Peter Ujfalusice3f0542010-08-31 08:11:44 +0000634 int enable_srg = 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100635 u16 w;
636
Jarkko Nikulaf821eec2011-09-26 10:45:45 +0300637 if (mcbsp->st_data)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000638 omap_st_start(mcbsp);
639
Peter Ujfalusice3f0542010-08-31 08:11:44 +0000640 /* Only enable SRG, if McBSP is master */
641 w = MCBSP_READ_CACHE(mcbsp, PCR0);
642 if (w & (FSXM | FSRM | CLKXM | CLKRM))
643 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
644 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300645
Peter Ujfalusice3f0542010-08-31 08:11:44 +0000646 if (enable_srg) {
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300647 /* Start the sample generator */
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800648 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800649 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300650 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100651
652 /* Enable transmitter and receiver */
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300653 tx &= 1;
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800654 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800655 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100656
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300657 rx &= 1;
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800658 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800659 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100660
Eduardo Valentin44a63112009-08-20 16:18:09 +0300661 /*
662 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
663 * REVISIT: 100us may give enough time for two CLKSRG, however
664 * due to some unknown PM related, clock gating etc. reason it
665 * is now at 500us.
666 */
667 udelay(500);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100668
Peter Ujfalusice3f0542010-08-31 08:11:44 +0000669 if (enable_srg) {
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300670 /* Start frame sync */
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800671 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800672 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300673 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100674
Jarkko Nikula88408232011-09-26 10:45:41 +0300675 if (mcbsp->pdata->has_ccr) {
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300676 /* Release the transmitter and receiver */
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800677 w = MCBSP_READ_CACHE(mcbsp, XCCR);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300678 w &= ~(tx ? XDISABLE : 0);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800679 MCBSP_WRITE(mcbsp, XCCR, w);
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800680 w = MCBSP_READ_CACHE(mcbsp, RCCR);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300681 w &= ~(rx ? RDISABLE : 0);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800682 MCBSP_WRITE(mcbsp, RCCR, w);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300683 }
684
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100685 /* Dump McBSP Regs */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200686 omap_mcbsp_dump_reg(mcbsp);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100687}
688
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200689void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100690{
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300691 int idle;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100692 u16 w;
693
Eduardo Valentinfb78d802008-07-03 12:24:39 +0300694 /* Reset transmitter */
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300695 tx &= 1;
Jarkko Nikula88408232011-09-26 10:45:41 +0300696 if (mcbsp->pdata->has_ccr) {
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800697 w = MCBSP_READ_CACHE(mcbsp, XCCR);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300698 w |= (tx ? XDISABLE : 0);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800699 MCBSP_WRITE(mcbsp, XCCR, w);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300700 }
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800701 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800702 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100703
704 /* Reset receiver */
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300705 rx &= 1;
Jarkko Nikula88408232011-09-26 10:45:41 +0300706 if (mcbsp->pdata->has_ccr) {
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800707 w = MCBSP_READ_CACHE(mcbsp, RCCR);
Jarkko Nikulaa93d4ed2009-10-14 09:56:35 -0700708 w |= (rx ? RDISABLE : 0);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800709 MCBSP_WRITE(mcbsp, RCCR, w);
Jarkko Nikulad09a2af2009-08-23 12:24:27 +0300710 }
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800711 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800712 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100713
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800714 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
715 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300716
717 if (idle) {
718 /* Reset the sample rate generator */
Janusz Krzysztofik96fbd742010-02-15 10:03:33 -0800719 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
Janusz Krzysztofik8ea32002010-02-15 10:03:32 -0800720 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300721 }
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000722
Jarkko Nikulaf821eec2011-09-26 10:45:45 +0300723 if (mcbsp->st_data)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000724 omap_st_stop(mcbsp);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100725}
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100726
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200727int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
Paul Walmsley69d042d2011-07-01 08:52:25 +0000728{
Peter Ujfalusif1991312012-08-16 16:41:00 +0300729 struct clk *fck_src;
Jarkko Nikula09d28d22011-09-26 10:45:48 +0300730 const char *src;
Peter Ujfalusif1991312012-08-16 16:41:00 +0300731 int r;
Paul Walmsley69d042d2011-07-01 08:52:25 +0000732
Jarkko Nikula09d28d22011-09-26 10:45:48 +0300733 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
Peter Ujfalusif1991312012-08-16 16:41:00 +0300734 src = "pad_fck";
Jarkko Nikula09d28d22011-09-26 10:45:48 +0300735 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
Peter Ujfalusif1991312012-08-16 16:41:00 +0300736 src = "prcm_fck";
Jarkko Nikula09d28d22011-09-26 10:45:48 +0300737 else
738 return -EINVAL;
739
Peter Ujfalusif1991312012-08-16 16:41:00 +0300740 fck_src = clk_get(mcbsp->dev, src);
741 if (IS_ERR(fck_src)) {
742 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
Peter Ujfalusicd1f08c2012-03-08 11:01:37 +0200743 return -EINVAL;
744 }
Jarkko Nikula7bc0c4b2011-09-26 10:45:49 +0300745
Peter Ujfalusif1991312012-08-16 16:41:00 +0300746 pm_runtime_put_sync(mcbsp->dev);
747
748 r = clk_set_parent(mcbsp->fclk, fck_src);
749 if (r) {
750 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
751 src);
752 clk_put(fck_src);
753 return r;
754 }
755
756 pm_runtime_get_sync(mcbsp->dev);
757
758 clk_put(fck_src);
759
760 return 0;
761
Paul Walmsley69d042d2011-07-01 08:52:25 +0000762}
Paul Walmsley69d042d2011-07-01 08:52:25 +0000763
Eduardo Valentina1a56f5f2009-08-20 16:18:11 +0300764#define max_thres(m) (mcbsp->pdata->buffer_size)
765#define valid_threshold(m, val) ((val) <= max_thres(m))
766#define THRESHOLD_PROP_BUILDER(prop) \
767static ssize_t prop##_show(struct device *dev, \
768 struct device_attribute *attr, char *buf) \
769{ \
770 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
771 \
772 return sprintf(buf, "%u\n", mcbsp->prop); \
773} \
774 \
775static ssize_t prop##_store(struct device *dev, \
776 struct device_attribute *attr, \
777 const char *buf, size_t size) \
778{ \
779 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
780 unsigned long val; \
781 int status; \
782 \
Jingoo Hanb785a492013-07-19 16:24:59 +0900783 status = kstrtoul(buf, 0, &val); \
Eduardo Valentina1a56f5f2009-08-20 16:18:11 +0300784 if (status) \
785 return status; \
786 \
787 if (!valid_threshold(mcbsp, val)) \
788 return -EDOM; \
789 \
790 mcbsp->prop = val; \
791 return size; \
792} \
793 \
794static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
795
796THRESHOLD_PROP_BUILDER(max_tx_thres);
797THRESHOLD_PROP_BUILDER(max_rx_thres);
798
Jarkko Nikula9b300502009-08-24 17:45:50 +0300799static const char *dma_op_modes[] = {
Peter Ujfalusi09fa37a2012-03-15 12:29:49 +0200800 "element", "threshold",
Jarkko Nikula9b300502009-08-24 17:45:50 +0300801};
802
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300803static ssize_t dma_op_mode_show(struct device *dev,
804 struct device_attribute *attr, char *buf)
805{
806 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
Jarkko Nikula9b300502009-08-24 17:45:50 +0300807 int dma_op_mode, i = 0;
808 ssize_t len = 0;
809 const char * const *s;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300810
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300811 dma_op_mode = mcbsp->dma_op_mode;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300812
Jarkko Nikula9b300502009-08-24 17:45:50 +0300813 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
814 if (dma_op_mode == i)
815 len += sprintf(buf + len, "[%s] ", *s);
816 else
817 len += sprintf(buf + len, "%s ", *s);
818 }
819 len += sprintf(buf + len, "\n");
820
821 return len;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300822}
823
824static ssize_t dma_op_mode_store(struct device *dev,
825 struct device_attribute *attr,
826 const char *buf, size_t size)
827{
828 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
Jarkko Nikula9b300502009-08-24 17:45:50 +0300829 const char * const *s;
830 int i = 0;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300831
Jarkko Nikula9b300502009-08-24 17:45:50 +0300832 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
833 if (sysfs_streq(buf, *s))
834 break;
835
836 if (i == ARRAY_SIZE(dma_op_modes))
837 return -EINVAL;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300838
839 spin_lock_irq(&mcbsp->lock);
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300840 if (!mcbsp->free) {
841 size = -EBUSY;
842 goto unlock;
843 }
Jarkko Nikula9b300502009-08-24 17:45:50 +0300844 mcbsp->dma_op_mode = i;
Peter Ujfalusi98cb20e2009-08-20 16:18:14 +0300845
846unlock:
847 spin_unlock_irq(&mcbsp->lock);
848
849 return size;
850}
851
852static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
853
Jarkko Nikula7bba67a2011-09-26 10:45:42 +0300854static const struct attribute *additional_attrs[] = {
855 &dev_attr_max_tx_thres.attr,
856 &dev_attr_max_rx_thres.attr,
857 &dev_attr_dma_op_mode.attr,
858 NULL,
859};
860
861static const struct attribute_group additional_attr_group = {
862 .attrs = (struct attribute **)additional_attrs,
863};
864
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000865static ssize_t st_taps_show(struct device *dev,
866 struct device_attribute *attr, char *buf)
867{
868 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
869 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
870 ssize_t status = 0;
871 int i;
872
873 spin_lock_irq(&mcbsp->lock);
874 for (i = 0; i < st_data->nr_taps; i++)
875 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
876 st_data->taps[i]);
877 if (i)
878 status += sprintf(&buf[status], "\n");
879 spin_unlock_irq(&mcbsp->lock);
880
881 return status;
882}
883
884static ssize_t st_taps_store(struct device *dev,
885 struct device_attribute *attr,
886 const char *buf, size_t size)
887{
888 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
889 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
890 int val, tmp, status, i = 0;
891
892 spin_lock_irq(&mcbsp->lock);
893 memset(st_data->taps, 0, sizeof(st_data->taps));
894 st_data->nr_taps = 0;
895
896 do {
897 status = sscanf(buf, "%d%n", &val, &tmp);
898 if (status < 0 || status == 0) {
899 size = -EINVAL;
900 goto out;
901 }
902 if (val < -32768 || val > 32767) {
903 size = -EINVAL;
904 goto out;
905 }
906 st_data->taps[i++] = val;
907 buf += tmp;
908 if (*buf != ',')
909 break;
910 buf++;
911 } while (1);
912
913 st_data->nr_taps = i;
914
915out:
916 spin_unlock_irq(&mcbsp->lock);
917
918 return size;
919}
920
921static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
922
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000923static const struct attribute *sidetone_attrs[] = {
924 &dev_attr_st_taps.attr,
925 NULL,
926};
927
928static const struct attribute_group sidetone_attr_group = {
929 .attrs = (struct attribute **)sidetone_attrs,
930};
931
Bill Pemberton7ff60002012-12-07 09:26:29 -0500932static int omap_st_add(struct omap_mcbsp *mcbsp, struct resource *res)
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000933{
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000934 struct omap_mcbsp_st_data *st_data;
935 int err;
936
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200937 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
938 if (!st_data)
939 return -ENOMEM;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000940
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200941 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
942 resource_size(res));
943 if (!st_data->io_base_st)
944 return -ENOMEM;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000945
946 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
947 if (err)
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200948 return err;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000949
950 mcbsp->st_data = st_data;
951 return 0;
Eero Nurkkalad912fa92010-02-22 12:21:11 +0000952}
953
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100954/*
955 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
956 * 730 has only 2 McBSP, and both of them are MPU peripherals.
957 */
Bill Pemberton7ff60002012-12-07 09:26:29 -0500958int omap_mcbsp_init(struct platform_device *pdev)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100959{
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200960 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800961 struct resource *res;
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +0300962 int ret = 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100963
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300964 spin_lock_init(&mcbsp->lock);
Shubhrajyoti D6722a722010-12-07 16:25:41 -0800965 mcbsp->free = true;
Chandra Shekharb4b58f52008-10-08 10:01:39 +0300966
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800967 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Axel Lin5aec8922015-08-24 16:49:05 +0800968 if (!res)
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Axel Lin5aec8922015-08-24 16:49:05 +0800970
971 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
972 if (IS_ERR(mcbsp->io_base))
973 return PTR_ERR(mcbsp->io_base);
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200974
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800975 mcbsp->phys_base = res->start;
Jarkko Nikulaac6747ca2011-09-26 10:45:43 +0300976 mcbsp->reg_cache_size = resource_size(res);
Russell Kingd592dd12008-09-04 14:25:42 +0100977
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800978 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
979 if (!res)
980 mcbsp->phys_dma_base = mcbsp->phys_base;
981 else
982 mcbsp->phys_dma_base = res->start;
983
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200984 /*
985 * OMAP1, 2 uses two interrupt lines: TX, RX
986 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
987 * OMAP4 and newer SoC only have the combined IRQ line.
988 * Use the combined IRQ if available since it gives better debugging
989 * possibilities.
990 */
991 mcbsp->irq = platform_get_irq_byname(pdev, "common");
992 if (mcbsp->irq == -ENXIO) {
993 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -0800994
Peter Ujfalusi35d210f2012-03-19 17:05:39 +0200995 if (mcbsp->tx_irq == -ENXIO) {
996 mcbsp->irq = platform_get_irq(pdev, 0);
997 mcbsp->tx_irq = 0;
998 } else {
999 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1000 mcbsp->irq = 0;
1001 }
Peter Ujfalusi73c95222012-03-07 11:15:37 +02001002 }
Kishon Vijay Abraham Icb7e9de2011-02-24 15:16:50 +05301003
Peter Ujfalusi9ab1fac2013-07-11 14:35:46 +02001004 if (!pdev->dev.of_node) {
1005 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1006 if (!res) {
1007 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1008 return -ENODEV;
1009 }
1010 mcbsp->dma_req[0] = res->start;
1011 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -08001012
Peter Ujfalusi9ab1fac2013-07-11 14:35:46 +02001013 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1014 if (!res) {
1015 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1016 return -ENODEV;
1017 }
1018 mcbsp->dma_req[1] = res->start;
1019 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
1020 } else {
1021 mcbsp->dma_data[0].filter_data = "tx";
1022 mcbsp->dma_data[1].filter_data = "rx";
Kishon Vijay Abraham I3cf32bb2011-02-24 12:51:45 -08001023 }
Peter Ujfalusi9ab1fac2013-07-11 14:35:46 +02001024
Lars-Peter Clausen09ae3aa2013-04-03 11:06:05 +02001025 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1026 mcbsp->dma_data[0].maxburst = 4;
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001027
Peter Ujfalusi9ab1fac2013-07-11 14:35:46 +02001028 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1029 mcbsp->dma_data[1].maxburst = 4;
1030
Russell Kingb820ce42009-01-23 10:26:46 +00001031 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1032 if (IS_ERR(mcbsp->fclk)) {
1033 ret = PTR_ERR(mcbsp->fclk);
Peter Ujfalusi2ee65952012-02-14 14:52:42 +02001034 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1035 return ret;
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001036 }
1037
Jarkko Nikula7bba67a2011-09-26 10:45:42 +03001038 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1039 if (mcbsp->pdata->buffer_size) {
1040 /*
1041 * Initially configure the maximum thresholds to a safe value.
1042 * The McBSP FIFO usage with these values should not go under
1043 * 16 locations.
1044 * If the whole FIFO without safety buffer is used, than there
1045 * is a possibility that the DMA will be not able to push the
1046 * new data on time, causing channel shifts in runtime.
1047 */
1048 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1049 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1050
1051 ret = sysfs_create_group(&mcbsp->dev->kobj,
1052 &additional_attr_group);
1053 if (ret) {
1054 dev_err(mcbsp->dev,
1055 "Unable to create additional controls\n");
1056 goto err_thres;
1057 }
1058 } else {
1059 mcbsp->max_tx_thres = -EINVAL;
1060 mcbsp->max_rx_thres = -EINVAL;
1061 }
1062
Jarkko Nikulaf821eec2011-09-26 10:45:45 +03001063 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1064 if (res) {
1065 ret = omap_st_add(mcbsp, res);
1066 if (ret) {
1067 dev_err(mcbsp->dev,
1068 "Unable to create sidetone controls\n");
1069 goto err_st;
1070 }
1071 }
Eduardo Valentina1a56f5f2009-08-20 16:18:11 +03001072
Russell Kingd592dd12008-09-04 14:25:42 +01001073 return 0;
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001074
Jarkko Nikulaf821eec2011-09-26 10:45:45 +03001075err_st:
1076 if (mcbsp->pdata->buffer_size)
Peter Ujfalusi2ee65952012-02-14 14:52:42 +02001077 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
Jarkko Nikula7bba67a2011-09-26 10:45:42 +03001078err_thres:
1079 clk_put(mcbsp->fclk);
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001080 return ret;
1081}
1082
Bill Pemberton7ff60002012-12-07 09:26:29 -05001083void omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001084{
Peter Ujfalusi2ee65952012-02-14 14:52:42 +02001085 if (mcbsp->pdata->buffer_size)
1086 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
Eduardo Valentinbc5d0c82008-07-03 12:24:39 +03001087
Peter Ujfalusi2ee65952012-02-14 14:52:42 +02001088 if (mcbsp->st_data)
1089 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001090}