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Paul Walmsleyecb24aa2008-08-19 11:08:43 +03001/*
Paul Walmsley98fa3d82010-01-26 20:13:13 -07002 * OMAP3 powerdomain definitions
Paul Walmsleyecb24aa2008-08-19 11:08:43 +03003 *
Paul Walmsley81794882011-09-14 11:34:21 -06004 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
Paul Walmsley4cb49fe2011-03-07 19:28:15 -07005 * Copyright (C) 2007-2011 Nokia Corporation
Paul Walmsleyecb24aa2008-08-19 11:08:43 +03006 *
Paul Walmsley6e014782010-12-21 20:01:20 -07007 * Paul Walmsley, Jouni Högander
Paul Walmsleyecb24aa2008-08-19 11:08:43 +03008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
Paul Walmsley6e014782010-12-21 20:01:20 -070014#include <linux/kernel.h>
15#include <linux/init.h>
Tony Lindgrend9a5f4d2012-03-07 17:28:01 -080016#include <linux/bug.h>
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030017
Tony Lindgrendbc04162012-08-31 10:59:07 -070018#include "soc.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070019#include "powerdomain.h"
Paul Walmsley6e014782010-12-21 20:01:20 -070020#include "powerdomains2xxx_3xxx_data.h"
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030021#include "prcm-common.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070022#include "prm2xxx_3xxx.h"
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030023#include "prm-regbits-34xx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070024#include "cm2xxx_3xxx.h"
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030025#include "cm-regbits-34xx.h"
26
27/*
28 * 34XX-specific powerdomains, dependencies
29 */
30
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030031/*
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030032 * Powerdomains
33 */
34
35static struct powerdomain iva2_pwrdm = {
36 .name = "iva2_pwrdm",
37 .prcm_offs = OMAP3430_IVA2_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030038 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF_RET,
40 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET,
43 [1] = PWRSTS_OFF_RET,
44 [2] = PWRSTS_OFF_RET,
45 [3] = PWRSTS_OFF_RET,
46 },
47 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -070048 [0] = PWRSTS_ON,
49 [1] = PWRSTS_ON,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030050 [2] = PWRSTS_OFF_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -070051 [3] = PWRSTS_ON,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030052 },
Paul Walmsley562e54d2013-01-26 00:58:17 -070053 .voltdm = { .name = "mpu_iva" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030054};
55
Paul Walmsley98fa3d82010-01-26 20:13:13 -070056static struct powerdomain mpu_3xxx_pwrdm = {
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030057 .name = "mpu_pwrdm",
58 .prcm_offs = MPU_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030059 .pwrsts = PWRSTS_OFF_RET_ON,
60 .pwrsts_logic_ret = PWRSTS_OFF_RET,
Thara Gopinath3863c742009-12-08 16:33:15 -070061 .flags = PWRDM_HAS_MPU_QUIRK,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030062 .banks = 1,
63 .pwrsts_mem_ret = {
64 [0] = PWRSTS_OFF_RET,
65 },
66 .pwrsts_mem_on = {
67 [0] = PWRSTS_OFF_ON,
68 },
Paul Walmsley562e54d2013-01-26 00:58:17 -070069 .voltdm = { .name = "mpu_iva" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030070};
71
Mark A. Greerff7ad7e2012-06-27 18:43:59 -060072static struct powerdomain mpu_am35x_pwrdm = {
73 .name = "mpu_pwrdm",
74 .prcm_offs = MPU_MOD,
75 .pwrsts = PWRSTS_ON,
76 .pwrsts_logic_ret = PWRSTS_ON,
77 .flags = PWRDM_HAS_MPU_QUIRK,
78 .banks = 1,
79 .pwrsts_mem_ret = {
80 [0] = PWRSTS_ON,
81 },
82 .pwrsts_mem_on = {
83 [0] = PWRSTS_ON,
84 },
Paul Walmsley562e54d2013-01-26 00:58:17 -070085 .voltdm = { .name = "mpu_iva" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -060086};
87
Anand Gadiyar58dcfb32010-07-14 13:38:49 +000088/*
89 * The USBTLL Save-and-Restore mechanism is broken on
Lucas De Marchi25985ed2011-03-30 22:57:33 -030090 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
Anand Gadiyar58dcfb32010-07-14 13:38:49 +000091 * needs to be disabled on these chips.
92 * Refer: 3430 errata ID i459 and 3630 errata ID i579
Jean Pihet447b8da2010-11-17 17:52:11 +000093 *
94 * Note: setting the SAR flag could help for errata ID i478
95 * which applies to 3430 <= ES3.1, but since the SAR feature
96 * is broken, do not use it.
Anand Gadiyar58dcfb32010-07-14 13:38:49 +000097 */
Paul Walmsley98fa3d82010-01-26 20:13:13 -070098static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
Paul Walmsleyecb24aa2008-08-19 11:08:43 +030099 .name = "core_pwrdm",
100 .prcm_offs = CORE_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300101 .pwrsts = PWRSTS_OFF_RET_ON,
Thara Gopinath4133a442010-02-24 12:05:50 -0700102 .pwrsts_logic_ret = PWRSTS_OFF_RET,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300103 .banks = 2,
104 .pwrsts_mem_ret = {
105 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
106 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
107 },
108 .pwrsts_mem_on = {
109 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
110 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
111 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700112 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300113};
114
Paul Walmsley98fa3d82010-01-26 20:13:13 -0700115static struct powerdomain core_3xxx_es3_1_pwrdm = {
Paul Walmsley7eb1afc2009-02-05 20:45:28 -0700116 .name = "core_pwrdm",
117 .prcm_offs = CORE_MOD,
Paul Walmsley7eb1afc2009-02-05 20:45:28 -0700118 .pwrsts = PWRSTS_OFF_RET_ON,
Thara Gopinath4133a442010-02-24 12:05:50 -0700119 .pwrsts_logic_ret = PWRSTS_OFF_RET,
Jean Pihet447b8da2010-11-17 17:52:11 +0000120 /*
121 * Setting the SAR flag for errata ID i478 which applies
122 * to 3430 <= ES3.1
123 */
Paul Walmsley7eb1afc2009-02-05 20:45:28 -0700124 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
125 .banks = 2,
126 .pwrsts_mem_ret = {
127 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
128 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
129 },
130 .pwrsts_mem_on = {
131 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
132 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
133 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700134 .voltdm = { .name = "core" },
Paul Walmsley7eb1afc2009-02-05 20:45:28 -0700135};
136
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600137static struct powerdomain core_am35x_pwrdm = {
138 .name = "core_pwrdm",
139 .prcm_offs = CORE_MOD,
140 .pwrsts = PWRSTS_ON,
141 .pwrsts_logic_ret = PWRSTS_ON,
142 .banks = 2,
143 .pwrsts_mem_ret = {
144 [0] = PWRSTS_ON, /* MEM1RETSTATE */
145 [1] = PWRSTS_ON, /* MEM2RETSTATE */
146 },
147 .pwrsts_mem_on = {
148 [0] = PWRSTS_ON, /* MEM1ONSTATE */
149 [1] = PWRSTS_ON, /* MEM2ONSTATE */
150 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700151 .voltdm = { .name = "core" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600152};
153
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300154static struct powerdomain dss_pwrdm = {
155 .name = "dss_pwrdm",
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300156 .prcm_offs = OMAP3430_DSS_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300157 .pwrsts = PWRSTS_OFF_RET_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700158 .pwrsts_logic_ret = PWRSTS_RET,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300159 .banks = 1,
160 .pwrsts_mem_ret = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700161 [0] = PWRSTS_RET, /* MEMRETSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300162 },
163 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700164 [0] = PWRSTS_ON, /* MEMONSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300165 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700166 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300167};
168
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600169static struct powerdomain dss_am35x_pwrdm = {
170 .name = "dss_pwrdm",
171 .prcm_offs = OMAP3430_DSS_MOD,
172 .pwrsts = PWRSTS_ON,
173 .pwrsts_logic_ret = PWRSTS_ON,
174 .banks = 1,
175 .pwrsts_mem_ret = {
176 [0] = PWRSTS_ON, /* MEMRETSTATE */
177 },
178 .pwrsts_mem_on = {
179 [0] = PWRSTS_ON, /* MEMONSTATE */
180 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700181 .voltdm = { .name = "core" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600182};
183
Paul Walmsleybe48ea72009-01-27 19:44:28 -0700184/*
185 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
186 * possible SGX powerstate, the SGX device itself does not support
187 * retention.
188 */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300189static struct powerdomain sgx_pwrdm = {
190 .name = "sgx_pwrdm",
191 .prcm_offs = OMAP3430ES2_SGX_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300192 /* XXX This is accurate for 3430 SGX, but what about GFX? */
Paul Walmsleybe48ea72009-01-27 19:44:28 -0700193 .pwrsts = PWRSTS_OFF_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700194 .pwrsts_logic_ret = PWRSTS_RET,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300195 .banks = 1,
196 .pwrsts_mem_ret = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700197 [0] = PWRSTS_RET, /* MEMRETSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300198 },
199 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700200 [0] = PWRSTS_ON, /* MEMONSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300201 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700202 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300203};
204
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600205static struct powerdomain sgx_am35x_pwrdm = {
206 .name = "sgx_pwrdm",
207 .prcm_offs = OMAP3430ES2_SGX_MOD,
208 .pwrsts = PWRSTS_ON,
209 .pwrsts_logic_ret = PWRSTS_ON,
210 .banks = 1,
211 .pwrsts_mem_ret = {
212 [0] = PWRSTS_ON, /* MEMRETSTATE */
213 },
214 .pwrsts_mem_on = {
215 [0] = PWRSTS_ON, /* MEMONSTATE */
216 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700217 .voltdm = { .name = "core" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600218};
219
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300220static struct powerdomain cam_pwrdm = {
221 .name = "cam_pwrdm",
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300222 .prcm_offs = OMAP3430_CAM_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300223 .pwrsts = PWRSTS_OFF_RET_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700224 .pwrsts_logic_ret = PWRSTS_RET,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300225 .banks = 1,
226 .pwrsts_mem_ret = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700227 [0] = PWRSTS_RET, /* MEMRETSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300228 },
229 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700230 [0] = PWRSTS_ON, /* MEMONSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300231 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700232 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300233};
234
235static struct powerdomain per_pwrdm = {
236 .name = "per_pwrdm",
237 .prcm_offs = OMAP3430_PER_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300238 .pwrsts = PWRSTS_OFF_RET_ON,
239 .pwrsts_logic_ret = PWRSTS_OFF_RET,
240 .banks = 1,
241 .pwrsts_mem_ret = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700242 [0] = PWRSTS_RET, /* MEMRETSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300243 },
244 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700245 [0] = PWRSTS_ON, /* MEMONSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300246 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700247 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300248};
249
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600250static struct powerdomain per_am35x_pwrdm = {
251 .name = "per_pwrdm",
252 .prcm_offs = OMAP3430_PER_MOD,
253 .pwrsts = PWRSTS_ON,
254 .pwrsts_logic_ret = PWRSTS_ON,
255 .banks = 1,
256 .pwrsts_mem_ret = {
257 [0] = PWRSTS_ON, /* MEMRETSTATE */
258 },
259 .pwrsts_mem_on = {
260 [0] = PWRSTS_ON, /* MEMONSTATE */
261 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700262 .voltdm = { .name = "core" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600263};
264
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300265static struct powerdomain emu_pwrdm = {
266 .name = "emu_pwrdm",
267 .prcm_offs = OMAP3430_EMU_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700268 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300269};
270
271static struct powerdomain neon_pwrdm = {
272 .name = "neon_pwrdm",
273 .prcm_offs = OMAP3430_NEON_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300274 .pwrsts = PWRSTS_OFF_RET_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700275 .pwrsts_logic_ret = PWRSTS_RET,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700276 .voltdm = { .name = "mpu_iva" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300277};
278
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600279static struct powerdomain neon_am35x_pwrdm = {
280 .name = "neon_pwrdm",
281 .prcm_offs = OMAP3430_NEON_MOD,
282 .pwrsts = PWRSTS_ON,
283 .pwrsts_logic_ret = PWRSTS_ON,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700284 .voltdm = { .name = "mpu_iva" },
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600285};
286
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300287static struct powerdomain usbhost_pwrdm = {
288 .name = "usbhost_pwrdm",
289 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300290 .pwrsts = PWRSTS_OFF_RET_ON,
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700291 .pwrsts_logic_ret = PWRSTS_RET,
Kalle Jokiniemi867d3202009-04-23 13:58:51 +0300292 /*
293 * REVISIT: Enabling usb host save and restore mechanism seems to
294 * leave the usb host domain permanently in ACTIVE mode after
295 * changing the usb host power domain state from OFF to active once.
296 * Disabling for now.
297 */
298 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300299 .banks = 1,
300 .pwrsts_mem_ret = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700301 [0] = PWRSTS_RET, /* MEMRETSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300302 },
303 .pwrsts_mem_on = {
Paul Walmsley4cb49fe2011-03-07 19:28:15 -0700304 [0] = PWRSTS_ON, /* MEMONSTATE */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300305 },
Paul Walmsley562e54d2013-01-26 00:58:17 -0700306 .voltdm = { .name = "core" },
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300307};
308
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700309static struct powerdomain dpll1_pwrdm = {
310 .name = "dpll1_pwrdm",
311 .prcm_offs = MPU_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700312 .voltdm = { .name = "mpu_iva" },
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700313};
314
315static struct powerdomain dpll2_pwrdm = {
316 .name = "dpll2_pwrdm",
317 .prcm_offs = OMAP3430_IVA2_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700318 .voltdm = { .name = "mpu_iva" },
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700319};
320
321static struct powerdomain dpll3_pwrdm = {
322 .name = "dpll3_pwrdm",
323 .prcm_offs = PLL_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700324 .voltdm = { .name = "core" },
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700325};
326
327static struct powerdomain dpll4_pwrdm = {
328 .name = "dpll4_pwrdm",
329 .prcm_offs = PLL_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700330 .voltdm = { .name = "core" },
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700331};
332
333static struct powerdomain dpll5_pwrdm = {
334 .name = "dpll5_pwrdm",
335 .prcm_offs = PLL_MOD,
Paul Walmsley562e54d2013-01-26 00:58:17 -0700336 .voltdm = { .name = "core" },
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700337};
338
Paul Walmsley6e014782010-12-21 20:01:20 -0700339/* As powerdomains are added or removed above, this list must also be changed */
Paul Walmsley81794882011-09-14 11:34:21 -0600340static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
Paul Walmsley6e014782010-12-21 20:01:20 -0700341 &wkup_omap2_pwrdm,
Paul Walmsley6e014782010-12-21 20:01:20 -0700342 &iva2_pwrdm,
343 &mpu_3xxx_pwrdm,
344 &neon_pwrdm,
Paul Walmsley6e014782010-12-21 20:01:20 -0700345 &cam_pwrdm,
346 &dss_pwrdm,
347 &per_pwrdm,
348 &emu_pwrdm,
Paul Walmsley6e014782010-12-21 20:01:20 -0700349 &dpll1_pwrdm,
350 &dpll2_pwrdm,
351 &dpll3_pwrdm,
352 &dpll4_pwrdm,
Paul Walmsley6e014782010-12-21 20:01:20 -0700353 NULL
354};
355
Paul Walmsley81794882011-09-14 11:34:21 -0600356static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
357 &gfx_omap2_pwrdm,
358 &core_3xxx_pre_es3_1_pwrdm,
359 NULL
360};
361
362/* also includes 3630ES1.0 */
363static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
364 &core_3xxx_pre_es3_1_pwrdm,
365 &sgx_pwrdm,
366 &usbhost_pwrdm,
367 &dpll5_pwrdm,
368 NULL
369};
370
371/* also includes 3630ES1.1+ */
372static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
373 &core_3xxx_es3_1_pwrdm,
374 &sgx_pwrdm,
375 &usbhost_pwrdm,
376 &dpll5_pwrdm,
377 NULL
378};
Paul Walmsley6e014782010-12-21 20:01:20 -0700379
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600380static struct powerdomain *powerdomains_am35x[] __initdata = {
381 &wkup_omap2_pwrdm,
382 &mpu_am35x_pwrdm,
383 &neon_am35x_pwrdm,
384 &core_am35x_pwrdm,
385 &sgx_am35x_pwrdm,
386 &dss_am35x_pwrdm,
387 &per_am35x_pwrdm,
388 &emu_pwrdm,
389 &dpll1_pwrdm,
390 &dpll3_pwrdm,
391 &dpll4_pwrdm,
392 &dpll5_pwrdm,
393 NULL
394};
395
Paul Walmsley6e014782010-12-21 20:01:20 -0700396void __init omap3xxx_powerdomains_init(void)
397{
Paul Walmsley81794882011-09-14 11:34:21 -0600398 unsigned int rev;
399
400 if (!cpu_is_omap34xx())
401 return;
402
Paul Walmsley129c65e2011-09-14 16:01:21 -0600403 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
Paul Walmsley81794882011-09-14 11:34:21 -0600404
405 rev = omap_rev();
406
Mark A. Greerff7ad7e2012-06-27 18:43:59 -0600407 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
408 pwrdm_register_pwrdms(powerdomains_am35x);
409 } else {
410 pwrdm_register_pwrdms(powerdomains_omap3430_common);
411
412 switch (rev) {
413 case OMAP3430_REV_ES1_0:
414 pwrdm_register_pwrdms(powerdomains_omap3430es1);
415 break;
416 case OMAP3430_REV_ES2_0:
417 case OMAP3430_REV_ES2_1:
418 case OMAP3430_REV_ES3_0:
419 case OMAP3630_REV_ES1_0:
420 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
421 break;
422 case OMAP3430_REV_ES3_1:
423 case OMAP3430_REV_ES3_1_2:
424 case OMAP3630_REV_ES1_1:
425 case OMAP3630_REV_ES1_2:
426 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
427 break;
428 default:
429 WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
430 }
431 }
Paul Walmsley81794882011-09-14 11:34:21 -0600432
Paul Walmsley129c65e2011-09-14 16:01:21 -0600433 pwrdm_complete_init();
Paul Walmsley6e014782010-12-21 20:01:20 -0700434}