blob: 6d6537d09d4f098e05d6f6231d50aeca8003e069 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
Arnd Bergmann78843722013-04-11 22:42:03 +020027#include <linux/dmaengine.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000028#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000029#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000030#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090031#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090032#include <linux/of.h>
33#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000034
Arnd Bergmann436d42c2012-08-24 15:22:12 +020035#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000036
Mark Brown563b4442013-04-18 18:06:05 +010037#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +020038#include <mach/dma.h>
39#endif
40
Thomas Abrahama5238e32012-07-13 07:15:14 +090041#define MAX_SPI_PORTS 3
42
Jassi Brar230d42d2009-11-30 07:39:42 +000043/* Registers and bit-fields */
44
45#define S3C64XX_SPI_CH_CFG 0x00
46#define S3C64XX_SPI_CLK_CFG 0x04
47#define S3C64XX_SPI_MODE_CFG 0x08
48#define S3C64XX_SPI_SLAVE_SEL 0x0C
49#define S3C64XX_SPI_INT_EN 0x10
50#define S3C64XX_SPI_STATUS 0x14
51#define S3C64XX_SPI_TX_DATA 0x18
52#define S3C64XX_SPI_RX_DATA 0x1C
53#define S3C64XX_SPI_PACKET_CNT 0x20
54#define S3C64XX_SPI_PENDING_CLR 0x24
55#define S3C64XX_SPI_SWAP_CFG 0x28
56#define S3C64XX_SPI_FB_CLK 0x2C
57
58#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
59#define S3C64XX_SPI_CH_SW_RST (1<<5)
60#define S3C64XX_SPI_CH_SLAVE (1<<4)
61#define S3C64XX_SPI_CPOL_L (1<<3)
62#define S3C64XX_SPI_CPHA_B (1<<2)
63#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
64#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
65
66#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
67#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
68#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090069#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000070
71#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
72#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
73#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
74#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
75#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
76#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
77#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
78#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
79#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
80#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
81#define S3C64XX_SPI_MODE_4BURST (1<<0)
82
83#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
84#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
85
Jassi Brar230d42d2009-11-30 07:39:42 +000086#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
87#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
88#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
89#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
90#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
91#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
92#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
93
94#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
95#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
96#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
97#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
98#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
99#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
100
101#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
102
103#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
104#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
105#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
106#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
107#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
108
109#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
110#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
111#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
112#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
113#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
114#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
115#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
116#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
117
118#define S3C64XX_SPI_FBCLK_MSK (3<<0)
119
Thomas Abrahama5238e32012-07-13 07:15:14 +0900120#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
121#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
122 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
123#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
124#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
125 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000126
127#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
128#define S3C64XX_SPI_TRAILCNT_OFF 19
129
130#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
131
132#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
133
Jassi Brar230d42d2009-11-30 07:39:42 +0000134#define RXBUSY (1<<2)
135#define TXBUSY (1<<3)
136
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900137struct s3c64xx_spi_dma_data {
Arnd Bergmann78843722013-04-11 22:42:03 +0200138 struct dma_chan *ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000139 enum dma_transfer_direction direction;
Arnd Bergmann78843722013-04-11 22:42:03 +0200140 unsigned int dmach;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900141};
142
Jassi Brar230d42d2009-11-30 07:39:42 +0000143/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900144 * struct s3c64xx_spi_info - SPI Controller hardware info
145 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
146 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
147 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
148 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
149 * @clk_from_cmu: True, if the controller does not include a clock mux and
150 * prescaler unit.
151 *
152 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
153 * differ in some aspects such as the size of the fifo and spi bus clock
154 * setup. Such differences are specified to the driver using this structure
155 * which is provided as driver data to the driver.
156 */
157struct s3c64xx_spi_port_config {
158 int fifo_lvl_mask[MAX_SPI_PORTS];
159 int rx_lvl_offset;
160 int tx_st_done;
161 bool high_speed;
162 bool clk_from_cmu;
163};
164
165/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000166 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
167 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700168 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000169 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000170 * @cntrlr_info: Platform specific data for the controller this driver manages.
171 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000172 * @queue: To log SPI xfer requests.
173 * @lock: Controller specific lock.
174 * @state: Set of FLAGS to indicate status.
175 * @rx_dmach: Controller's DMA channel for Rx.
176 * @tx_dmach: Controller's DMA channel for Tx.
177 * @sfr_start: BUS address of SPI controller regs.
178 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000179 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000180 * @xfer_completion: To indicate completion of xfer task.
181 * @cur_mode: Stores the active configuration of the controller.
182 * @cur_bpw: Stores the active bits per word settings.
183 * @cur_speed: Stores the active xfer clock speed.
184 */
185struct s3c64xx_spi_driver_data {
186 void __iomem *regs;
187 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700188 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000189 struct platform_device *pdev;
190 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700191 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000192 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000193 struct list_head queue;
194 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000195 unsigned long sfr_start;
196 struct completion xfer_completion;
197 unsigned state;
198 unsigned cur_mode, cur_bpw;
199 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900200 struct s3c64xx_spi_dma_data rx_dma;
201 struct s3c64xx_spi_dma_data tx_dma;
Mark Brown563b4442013-04-18 18:06:05 +0100202#ifdef CONFIG_S3C_DMA
Boojin Kim39d3e802011-09-02 09:44:41 +0900203 struct samsung_dma_ops *ops;
Arnd Bergmann78843722013-04-11 22:42:03 +0200204#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +0900205 struct s3c64xx_spi_port_config *port_conf;
206 unsigned int port_id;
Thomas Abraham2b908072012-07-13 07:15:15 +0900207 unsigned long gpios[4];
Jassi Brar230d42d2009-11-30 07:39:42 +0000208};
209
Jassi Brar230d42d2009-11-30 07:39:42 +0000210static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
211{
Jassi Brar230d42d2009-11-30 07:39:42 +0000212 void __iomem *regs = sdd->regs;
213 unsigned long loops;
214 u32 val;
215
216 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
217
218 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900219 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
220 writel(val, regs + S3C64XX_SPI_CH_CFG);
221
222 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000223 val |= S3C64XX_SPI_CH_SW_RST;
224 val &= ~S3C64XX_SPI_CH_HS_EN;
225 writel(val, regs + S3C64XX_SPI_CH_CFG);
226
227 /* Flush TxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900231 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000232
Mark Brownbe7852a2010-08-23 17:40:56 +0100233 if (loops == 0)
234 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
235
Jassi Brar230d42d2009-11-30 07:39:42 +0000236 /* Flush RxFIFO*/
237 loops = msecs_to_loops(1);
238 do {
239 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900240 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000241 readl(regs + S3C64XX_SPI_RX_DATA);
242 else
243 break;
244 } while (loops--);
245
Mark Brownbe7852a2010-08-23 17:40:56 +0100246 if (loops == 0)
247 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
248
Jassi Brar230d42d2009-11-30 07:39:42 +0000249 val = readl(regs + S3C64XX_SPI_CH_CFG);
250 val &= ~S3C64XX_SPI_CH_SW_RST;
251 writel(val, regs + S3C64XX_SPI_CH_CFG);
252
253 val = readl(regs + S3C64XX_SPI_MODE_CFG);
254 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
255 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000256}
257
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900258static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900259{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900260 struct s3c64xx_spi_driver_data *sdd;
261 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900262 unsigned long flags;
263
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900264 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900265 sdd = container_of(data,
266 struct s3c64xx_spi_driver_data, rx_dma);
267 else
268 sdd = container_of(data,
269 struct s3c64xx_spi_driver_data, tx_dma);
270
Boojin Kim39d3e802011-09-02 09:44:41 +0900271 spin_lock_irqsave(&sdd->lock, flags);
272
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900273 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900274 sdd->state &= ~RXBUSY;
275 if (!(sdd->state & TXBUSY))
276 complete(&sdd->xfer_completion);
277 } else {
278 sdd->state &= ~TXBUSY;
279 if (!(sdd->state & RXBUSY))
280 complete(&sdd->xfer_completion);
281 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900282
283 spin_unlock_irqrestore(&sdd->lock, flags);
284}
285
Mark Brown563b4442013-04-18 18:06:05 +0100286#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +0200287/* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
288
289static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
290 .name = "samsung-spi-dma",
291};
292
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900293static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
294 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900295{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900296 struct s3c64xx_spi_driver_data *sdd;
Boojin Kim4969c322012-06-19 13:27:03 +0900297 struct samsung_dma_prep info;
298 struct samsung_dma_config config;
Boojin Kim39d3e802011-09-02 09:44:41 +0900299
Boojin Kim4969c322012-06-19 13:27:03 +0900300 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900301 sdd = container_of((void *)dma,
302 struct s3c64xx_spi_driver_data, rx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900303 config.direction = sdd->rx_dma.direction;
304 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
305 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200306 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900307 } else {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900308 sdd = container_of((void *)dma,
309 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900310 config.direction = sdd->tx_dma.direction;
311 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
312 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200313 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900314 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900315
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900316 info.cap = DMA_SLAVE;
317 info.len = len;
318 info.fp = s3c64xx_spi_dmacb;
319 info.fp_param = dma;
320 info.direction = dma->direction;
321 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900322
Arnd Bergmann78843722013-04-11 22:42:03 +0200323 sdd->ops->prepare((enum dma_ch)dma->ch, &info);
324 sdd->ops->trigger((enum dma_ch)dma->ch);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900325}
326
327static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
328{
Boojin Kim4969c322012-06-19 13:27:03 +0900329 struct samsung_dma_req req;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530330 struct device *dev = &sdd->pdev->dev;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900331
332 sdd->ops = samsung_dma_get_ops();
333
Boojin Kim4969c322012-06-19 13:27:03 +0900334 req.cap = DMA_SLAVE;
335 req.client = &s3c64xx_spi_dma_client;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900336
Arnd Bergmann78843722013-04-11 22:42:03 +0200337 sdd->rx_dma.ch = (void *)sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
338 sdd->tx_dma.ch = (void *)sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900339
340 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900341}
342
Arnd Bergmann78843722013-04-11 22:42:03 +0200343static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
344{
345 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
346
347 /* Acquire DMA channels */
348 while (!acquire_dma(sdd))
349 usleep_range(10000, 11000);
350
351 pm_runtime_get_sync(&sdd->pdev->dev);
352
353 return 0;
354}
355
356static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
357{
358 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
359
360 /* Free DMA channels */
361 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
362 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
363
364 pm_runtime_put(&sdd->pdev->dev);
365
366 return 0;
367}
368
369static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
370 struct s3c64xx_spi_dma_data *dma)
371{
372 sdd->ops->stop((enum dma_ch)dma->ch);
373}
374#else
375
376static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
377 unsigned len, dma_addr_t buf)
378{
379 struct s3c64xx_spi_driver_data *sdd;
380 struct dma_slave_config config;
381 struct scatterlist sg;
382 struct dma_async_tx_descriptor *desc;
383
384 if (dma->direction == DMA_DEV_TO_MEM) {
385 sdd = container_of((void *)dma,
386 struct s3c64xx_spi_driver_data, rx_dma);
387 config.direction = dma->direction;
388 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
389 config.src_addr_width = sdd->cur_bpw / 8;
390 config.src_maxburst = 1;
391 dmaengine_slave_config(dma->ch, &config);
392 } else {
393 sdd = container_of((void *)dma,
394 struct s3c64xx_spi_driver_data, tx_dma);
395 config.direction = dma->direction;
396 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
397 config.dst_addr_width = sdd->cur_bpw / 8;
398 config.dst_maxburst = 1;
399 dmaengine_slave_config(dma->ch, &config);
400 }
401
402 sg_init_table(&sg, 1);
403 sg_dma_len(&sg) = len;
404 sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
405 len, offset_in_page(buf));
406 sg_dma_address(&sg) = buf;
407
408 desc = dmaengine_prep_slave_sg(dma->ch,
409 &sg, 1, dma->direction, DMA_PREP_INTERRUPT);
410
411 desc->callback = s3c64xx_spi_dmacb;
412 desc->callback_param = dma;
413
414 dmaengine_submit(desc);
415 dma_async_issue_pending(dma->ch);
416}
417
418static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
419{
420 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
421 dma_filter_fn filter = sdd->cntrlr_info->filter;
422 struct device *dev = &sdd->pdev->dev;
423 dma_cap_mask_t mask;
424
425 dma_cap_zero(mask);
426 dma_cap_set(DMA_SLAVE, mask);
427
428 /* Acquire DMA channels */
429 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
430 (void*)sdd->rx_dma.dmach, dev, "rx");
431 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
432 (void*)sdd->tx_dma.dmach, dev, "tx");
433 pm_runtime_get_sync(&sdd->pdev->dev);
434
435 return 0;
436}
437
438static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
439{
440 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
441
442 /* Free DMA channels */
443 dma_release_channel(sdd->rx_dma.ch);
444 dma_release_channel(sdd->tx_dma.ch);
445
446 pm_runtime_put(&sdd->pdev->dev);
447 return 0;
448}
449
450static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
451 struct s3c64xx_spi_dma_data *dma)
452{
453 dmaengine_terminate_all(dma->ch);
454}
455#endif
456
Jassi Brar230d42d2009-11-30 07:39:42 +0000457static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
458 struct spi_device *spi,
459 struct spi_transfer *xfer, int dma_mode)
460{
Jassi Brar230d42d2009-11-30 07:39:42 +0000461 void __iomem *regs = sdd->regs;
462 u32 modecfg, chcfg;
463
464 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
465 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
466
467 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
468 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
469
470 if (dma_mode) {
471 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
472 } else {
473 /* Always shift in data in FIFO, even if xfer is Tx only,
474 * this helps setting PCKT_CNT value for generating clocks
475 * as exactly needed.
476 */
477 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
478 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
479 | S3C64XX_SPI_PACKET_CNT_EN,
480 regs + S3C64XX_SPI_PACKET_CNT);
481 }
482
483 if (xfer->tx_buf != NULL) {
484 sdd->state |= TXBUSY;
485 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
486 if (dma_mode) {
487 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900488 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000489 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900490 switch (sdd->cur_bpw) {
491 case 32:
492 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
493 xfer->tx_buf, xfer->len / 4);
494 break;
495 case 16:
496 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
497 xfer->tx_buf, xfer->len / 2);
498 break;
499 default:
500 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
501 xfer->tx_buf, xfer->len);
502 break;
503 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000504 }
505 }
506
507 if (xfer->rx_buf != NULL) {
508 sdd->state |= RXBUSY;
509
Thomas Abrahama5238e32012-07-13 07:15:14 +0900510 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000511 && !(sdd->cur_mode & SPI_CPHA))
512 chcfg |= S3C64XX_SPI_CH_HS_EN;
513
514 if (dma_mode) {
515 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
516 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
517 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
518 | S3C64XX_SPI_PACKET_CNT_EN,
519 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900520 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000521 }
522 }
523
524 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
525 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
526}
527
528static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
529 struct spi_device *spi)
530{
531 struct s3c64xx_spi_csinfo *cs;
532
533 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
534 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
535 /* Deselect the last toggled device */
536 cs = sdd->tgl_spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900537 gpio_set_value(cs->line,
538 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000539 }
540 sdd->tgl_spi = NULL;
541 }
542
543 cs = spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900544 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Jassi Brar230d42d2009-11-30 07:39:42 +0000545}
546
547static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
548 struct spi_transfer *xfer, int dma_mode)
549{
Jassi Brar230d42d2009-11-30 07:39:42 +0000550 void __iomem *regs = sdd->regs;
551 unsigned long val;
552 int ms;
553
554 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
555 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100556 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000557
558 if (dma_mode) {
559 val = msecs_to_jiffies(ms) + 10;
560 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
561 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900562 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000563 val = msecs_to_loops(ms);
564 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900565 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900566 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000567 }
568
569 if (!val)
570 return -EIO;
571
572 if (dma_mode) {
573 u32 status;
574
575 /*
576 * DmaTx returns after simply writing data in the FIFO,
577 * w/o waiting for real transmission on the bus to finish.
578 * DmaRx returns only after Dma read data from FIFO which
579 * needs bus transmission to finish, so we don't worry if
580 * Xfer involved Rx(with or without Tx).
581 */
582 if (xfer->rx_buf == NULL) {
583 val = msecs_to_loops(10);
584 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900585 while ((TX_FIFO_LVL(status, sdd)
586 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000587 && --val) {
588 cpu_relax();
589 status = readl(regs + S3C64XX_SPI_STATUS);
590 }
591
592 if (!val)
593 return -EIO;
594 }
595 } else {
Jassi Brar230d42d2009-11-30 07:39:42 +0000596 /* If it was only Tx */
597 if (xfer->rx_buf == NULL) {
598 sdd->state &= ~TXBUSY;
599 return 0;
600 }
601
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900602 switch (sdd->cur_bpw) {
603 case 32:
604 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
605 xfer->rx_buf, xfer->len / 4);
606 break;
607 case 16:
608 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
609 xfer->rx_buf, xfer->len / 2);
610 break;
611 default:
612 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
613 xfer->rx_buf, xfer->len);
614 break;
615 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000616 sdd->state &= ~RXBUSY;
617 }
618
619 return 0;
620}
621
622static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
623 struct spi_device *spi)
624{
625 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
626
627 if (sdd->tgl_spi == spi)
628 sdd->tgl_spi = NULL;
629
Thomas Abraham1c20c202012-07-13 07:15:14 +0900630 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000631}
632
633static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
634{
Jassi Brar230d42d2009-11-30 07:39:42 +0000635 void __iomem *regs = sdd->regs;
636 u32 val;
637
638 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900639 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900640 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900641 } else {
642 val = readl(regs + S3C64XX_SPI_CLK_CFG);
643 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
644 writel(val, regs + S3C64XX_SPI_CLK_CFG);
645 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000646
647 /* Set Polarity and Phase */
648 val = readl(regs + S3C64XX_SPI_CH_CFG);
649 val &= ~(S3C64XX_SPI_CH_SLAVE |
650 S3C64XX_SPI_CPOL_L |
651 S3C64XX_SPI_CPHA_B);
652
653 if (sdd->cur_mode & SPI_CPOL)
654 val |= S3C64XX_SPI_CPOL_L;
655
656 if (sdd->cur_mode & SPI_CPHA)
657 val |= S3C64XX_SPI_CPHA_B;
658
659 writel(val, regs + S3C64XX_SPI_CH_CFG);
660
661 /* Set Channel & DMA Mode */
662 val = readl(regs + S3C64XX_SPI_MODE_CFG);
663 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
664 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
665
666 switch (sdd->cur_bpw) {
667 case 32:
668 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900669 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000670 break;
671 case 16:
672 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900673 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000674 break;
675 default:
676 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900677 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000678 break;
679 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000680
681 writel(val, regs + S3C64XX_SPI_MODE_CFG);
682
Thomas Abrahama5238e32012-07-13 07:15:14 +0900683 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900684 /* Configure Clock */
685 /* There is half-multiplier before the SPI */
686 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
687 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900688 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900689 } else {
690 /* Configure Clock */
691 val = readl(regs + S3C64XX_SPI_CLK_CFG);
692 val &= ~S3C64XX_SPI_PSR_MASK;
693 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
694 & S3C64XX_SPI_PSR_MASK);
695 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000696
Jassi Brarb42a81c2010-09-29 17:31:33 +0900697 /* Enable Clock */
698 val = readl(regs + S3C64XX_SPI_CLK_CFG);
699 val |= S3C64XX_SPI_ENCLK_ENABLE;
700 writel(val, regs + S3C64XX_SPI_CLK_CFG);
701 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000702}
703
Jassi Brar230d42d2009-11-30 07:39:42 +0000704#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
705
706static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
707 struct spi_message *msg)
708{
709 struct device *dev = &sdd->pdev->dev;
710 struct spi_transfer *xfer;
711
712 if (msg->is_dma_mapped)
713 return 0;
714
715 /* First mark all xfer unmapped */
716 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
717 xfer->rx_dma = XFER_DMAADDR_INVALID;
718 xfer->tx_dma = XFER_DMAADDR_INVALID;
719 }
720
721 /* Map until end or first fail */
722 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
723
Thomas Abrahama5238e32012-07-13 07:15:14 +0900724 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900725 continue;
726
Jassi Brar230d42d2009-11-30 07:39:42 +0000727 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900728 xfer->tx_dma = dma_map_single(dev,
729 (void *)xfer->tx_buf, xfer->len,
730 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000731 if (dma_mapping_error(dev, xfer->tx_dma)) {
732 dev_err(dev, "dma_map_single Tx failed\n");
733 xfer->tx_dma = XFER_DMAADDR_INVALID;
734 return -ENOMEM;
735 }
736 }
737
738 if (xfer->rx_buf != NULL) {
739 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
740 xfer->len, DMA_FROM_DEVICE);
741 if (dma_mapping_error(dev, xfer->rx_dma)) {
742 dev_err(dev, "dma_map_single Rx failed\n");
743 dma_unmap_single(dev, xfer->tx_dma,
744 xfer->len, DMA_TO_DEVICE);
745 xfer->tx_dma = XFER_DMAADDR_INVALID;
746 xfer->rx_dma = XFER_DMAADDR_INVALID;
747 return -ENOMEM;
748 }
749 }
750 }
751
752 return 0;
753}
754
755static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
756 struct spi_message *msg)
757{
758 struct device *dev = &sdd->pdev->dev;
759 struct spi_transfer *xfer;
760
761 if (msg->is_dma_mapped)
762 return;
763
764 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
765
Thomas Abrahama5238e32012-07-13 07:15:14 +0900766 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900767 continue;
768
Jassi Brar230d42d2009-11-30 07:39:42 +0000769 if (xfer->rx_buf != NULL
770 && xfer->rx_dma != XFER_DMAADDR_INVALID)
771 dma_unmap_single(dev, xfer->rx_dma,
772 xfer->len, DMA_FROM_DEVICE);
773
774 if (xfer->tx_buf != NULL
775 && xfer->tx_dma != XFER_DMAADDR_INVALID)
776 dma_unmap_single(dev, xfer->tx_dma,
777 xfer->len, DMA_TO_DEVICE);
778 }
779}
780
Mark Brownad2a99a2012-02-15 14:48:32 -0800781static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
782 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000783{
Mark Brownad2a99a2012-02-15 14:48:32 -0800784 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000785 struct spi_device *spi = msg->spi;
786 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
787 struct spi_transfer *xfer;
788 int status = 0, cs_toggle = 0;
789 u32 speed;
790 u8 bpw;
791
792 /* If Master's(controller) state differs from that needed by Slave */
793 if (sdd->cur_speed != spi->max_speed_hz
794 || sdd->cur_mode != spi->mode
795 || sdd->cur_bpw != spi->bits_per_word) {
796 sdd->cur_bpw = spi->bits_per_word;
797 sdd->cur_speed = spi->max_speed_hz;
798 sdd->cur_mode = spi->mode;
799 s3c64xx_spi_config(sdd);
800 }
801
802 /* Map all the transfers if needed */
803 if (s3c64xx_spi_map_mssg(sdd, msg)) {
804 dev_err(&spi->dev,
805 "Xfer: Unable to map message buffers!\n");
806 status = -ENOMEM;
807 goto out;
808 }
809
810 /* Configure feedback delay */
811 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
812
813 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
814
815 unsigned long flags;
816 int use_dma;
817
818 INIT_COMPLETION(sdd->xfer_completion);
819
820 /* Only BPW and Speed may change across transfers */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530821 bpw = xfer->bits_per_word;
Jassi Brar230d42d2009-11-30 07:39:42 +0000822 speed = xfer->speed_hz ? : spi->max_speed_hz;
823
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900824 if (xfer->len % (bpw / 8)) {
825 dev_err(&spi->dev,
826 "Xfer length(%u) not a multiple of word size(%u)\n",
827 xfer->len, bpw / 8);
828 status = -EIO;
829 goto out;
830 }
831
Jassi Brar230d42d2009-11-30 07:39:42 +0000832 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
833 sdd->cur_bpw = bpw;
834 sdd->cur_speed = speed;
835 s3c64xx_spi_config(sdd);
836 }
837
838 /* Polling method for xfers not bigger than FIFO capacity */
Arnd Bergmann78843722013-04-11 22:42:03 +0200839 use_dma = 0;
840 if (sdd->rx_dma.ch && sdd->tx_dma.ch &&
841 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))
Jassi Brar230d42d2009-11-30 07:39:42 +0000842 use_dma = 1;
843
844 spin_lock_irqsave(&sdd->lock, flags);
845
846 /* Pending only which is to be done */
847 sdd->state &= ~RXBUSY;
848 sdd->state &= ~TXBUSY;
849
850 enable_datapath(sdd, spi, xfer, use_dma);
851
852 /* Slave Select */
853 enable_cs(sdd, spi);
854
855 /* Start the signals */
Mark Brown5fc3e832012-07-19 14:36:23 +0900856 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000857
858 spin_unlock_irqrestore(&sdd->lock, flags);
859
860 status = wait_for_xfer(sdd, xfer, use_dma);
861
862 /* Quiese the signals */
Mark Brown5fc3e832012-07-19 14:36:23 +0900863 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
864 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000865
866 if (status) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900867 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000868 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
869 (sdd->state & RXBUSY) ? 'f' : 'p',
870 (sdd->state & TXBUSY) ? 'f' : 'p',
871 xfer->len);
872
873 if (use_dma) {
874 if (xfer->tx_buf != NULL
875 && (sdd->state & TXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200876 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000877 if (xfer->rx_buf != NULL
878 && (sdd->state & RXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200879 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000880 }
881
882 goto out;
883 }
884
885 if (xfer->delay_usecs)
886 udelay(xfer->delay_usecs);
887
888 if (xfer->cs_change) {
889 /* Hint that the next mssg is gonna be
890 for the same device */
891 if (list_is_last(&xfer->transfer_list,
892 &msg->transfers))
893 cs_toggle = 1;
Jassi Brar230d42d2009-11-30 07:39:42 +0000894 }
895
896 msg->actual_length += xfer->len;
897
898 flush_fifo(sdd);
899 }
900
901out:
902 if (!cs_toggle || status)
903 disable_cs(sdd, spi);
904 else
905 sdd->tgl_spi = spi;
906
907 s3c64xx_spi_unmap_mssg(sdd, msg);
908
909 msg->status = status;
910
Mark Brownad2a99a2012-02-15 14:48:32 -0800911 spi_finalize_current_message(master);
912
913 return 0;
Jassi Brar230d42d2009-11-30 07:39:42 +0000914}
915
Thomas Abraham2b908072012-07-13 07:15:15 +0900916static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +0900917 struct spi_device *spi)
918{
919 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +0000920 struct device_node *slave_np, *data_np = NULL;
Thomas Abraham2b908072012-07-13 07:15:15 +0900921 u32 fb_delay = 0;
922
923 slave_np = spi->dev.of_node;
924 if (!slave_np) {
925 dev_err(&spi->dev, "device node not found\n");
926 return ERR_PTR(-EINVAL);
927 }
928
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100929 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +0900930 if (!data_np) {
931 dev_err(&spi->dev, "child node 'controller-data' not found\n");
932 return ERR_PTR(-EINVAL);
933 }
934
935 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
936 if (!cs) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900937 dev_err(&spi->dev, "could not allocate memory for controller data\n");
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100938 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900939 return ERR_PTR(-ENOMEM);
940 }
941
942 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
943 if (!gpio_is_valid(cs->line)) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900944 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
Thomas Abraham2b908072012-07-13 07:15:15 +0900945 kfree(cs);
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100946 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900947 return ERR_PTR(-EINVAL);
948 }
949
950 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
951 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100952 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900953 return cs;
954}
955
Jassi Brar230d42d2009-11-30 07:39:42 +0000956/*
957 * Here we only check the validity of requested configuration
958 * and save the configuration in a local data-structure.
959 * The controller is actually configured only just before we
960 * get a message to transfer.
961 */
962static int s3c64xx_spi_setup(struct spi_device *spi)
963{
964 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
965 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -0700966 struct s3c64xx_spi_info *sci;
Jassi Brar230d42d2009-11-30 07:39:42 +0000967 struct spi_message *msg;
Jassi Brar230d42d2009-11-30 07:39:42 +0000968 unsigned long flags;
Thomas Abraham2b908072012-07-13 07:15:15 +0900969 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +0000970
Thomas Abraham2b908072012-07-13 07:15:15 +0900971 sdd = spi_master_get_devdata(spi->master);
972 if (!cs && spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +0100973 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +0900974 spi->controller_data = cs;
975 }
976
977 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000978 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
979 return -ENODEV;
980 }
981
Thomas Abraham1c20c202012-07-13 07:15:14 +0900982 if (!spi_get_ctldata(spi)) {
Mark Brown707214d2012-07-19 14:36:16 +0900983 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
984 dev_name(&spi->dev));
Thomas Abraham1c20c202012-07-13 07:15:14 +0900985 if (err) {
Mark Brown49f3eac2012-07-19 14:36:13 +0900986 dev_err(&spi->dev,
987 "Failed to get /CS gpio [%d]: %d\n",
988 cs->line, err);
Thomas Abraham2b908072012-07-13 07:15:15 +0900989 goto err_gpio_req;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900990 }
991 spi_set_ctldata(spi, cs);
992 }
993
Jassi Brar230d42d2009-11-30 07:39:42 +0000994 sci = sdd->cntrlr_info;
995
996 spin_lock_irqsave(&sdd->lock, flags);
997
998 list_for_each_entry(msg, &sdd->queue, queue) {
999 /* Is some mssg is already queued for this device */
1000 if (msg->spi == spi) {
1001 dev_err(&spi->dev,
1002 "setup: attempt while mssg in queue!\n");
1003 spin_unlock_irqrestore(&sdd->lock, flags);
Thomas Abraham2b908072012-07-13 07:15:15 +09001004 err = -EBUSY;
1005 goto err_msgq;
Jassi Brar230d42d2009-11-30 07:39:42 +00001006 }
1007 }
1008
Jassi Brar230d42d2009-11-30 07:39:42 +00001009 spin_unlock_irqrestore(&sdd->lock, flags);
1010
Mark Brownb97b6622011-12-04 00:58:06 +00001011 pm_runtime_get_sync(&sdd->pdev->dev);
1012
Jassi Brar230d42d2009-11-30 07:39:42 +00001013 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001014 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001015 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001016
Jassi Brarb42a81c2010-09-29 17:31:33 +09001017 /* Max possible */
1018 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001019
Jassi Brarb42a81c2010-09-29 17:31:33 +09001020 if (spi->max_speed_hz > speed)
1021 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001022
Jassi Brarb42a81c2010-09-29 17:31:33 +09001023 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1024 psr &= S3C64XX_SPI_PSR_MASK;
1025 if (psr == S3C64XX_SPI_PSR_MASK)
1026 psr--;
1027
1028 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1029 if (spi->max_speed_hz < speed) {
1030 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1031 psr++;
1032 } else {
1033 err = -EINVAL;
1034 goto setup_exit;
1035 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001036 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001037
Jassi Brarb42a81c2010-09-29 17:31:33 +09001038 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +09001039 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001040 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +09001041 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +00001042 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1043 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +09001044 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +09001045 goto setup_exit;
1046 }
Jassi Brarb42a81c2010-09-29 17:31:33 +09001047 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001048
Mark Brownb97b6622011-12-04 00:58:06 +00001049 pm_runtime_put(&sdd->pdev->dev);
Thomas Abraham2b908072012-07-13 07:15:15 +09001050 disable_cs(sdd, spi);
1051 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +00001052
Jassi Brar230d42d2009-11-30 07:39:42 +00001053setup_exit:
Jassi Brar230d42d2009-11-30 07:39:42 +00001054 /* setup() returns with device de-selected */
1055 disable_cs(sdd, spi);
1056
Thomas Abraham2b908072012-07-13 07:15:15 +09001057err_msgq:
1058 gpio_free(cs->line);
1059 spi_set_ctldata(spi, NULL);
1060
1061err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +02001062 if (spi->dev.of_node)
1063 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +09001064
Jassi Brar230d42d2009-11-30 07:39:42 +00001065 return err;
1066}
1067
Thomas Abraham1c20c202012-07-13 07:15:14 +09001068static void s3c64xx_spi_cleanup(struct spi_device *spi)
1069{
1070 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1071
Thomas Abraham2b908072012-07-13 07:15:15 +09001072 if (cs) {
Thomas Abraham1c20c202012-07-13 07:15:14 +09001073 gpio_free(cs->line);
Thomas Abraham2b908072012-07-13 07:15:15 +09001074 if (spi->dev.of_node)
1075 kfree(cs);
1076 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001077 spi_set_ctldata(spi, NULL);
1078}
1079
Mark Brownc2573122011-11-10 10:57:32 +00001080static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1081{
1082 struct s3c64xx_spi_driver_data *sdd = data;
1083 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +05301084 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +00001085
Girish K S375981f2013-03-13 12:13:30 +05301086 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +00001087
Girish K S375981f2013-03-13 12:13:30 +05301088 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1089 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001090 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301091 }
1092 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1093 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001094 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301095 }
1096 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1097 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001098 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301099 }
1100 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1101 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001102 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301103 }
1104
1105 /* Clear the pending irq by setting and then clearing it */
1106 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1107 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +00001108
1109 return IRQ_HANDLED;
1110}
1111
Jassi Brar230d42d2009-11-30 07:39:42 +00001112static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1113{
Jassi Brarad7de722010-01-20 13:49:44 -07001114 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001115 void __iomem *regs = sdd->regs;
1116 unsigned int val;
1117
1118 sdd->cur_speed = 0;
1119
Mark Brown5fc3e832012-07-19 14:36:23 +09001120 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +00001121
1122 /* Disable Interrupts - we use Polling if not DMA mode */
1123 writel(0, regs + S3C64XX_SPI_INT_EN);
1124
Thomas Abrahama5238e32012-07-13 07:15:14 +09001125 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +09001126 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +00001127 regs + S3C64XX_SPI_CLK_CFG);
1128 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1129 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1130
Girish K S375981f2013-03-13 12:13:30 +05301131 /* Clear any irq pending bits, should set and clear the bits */
1132 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1133 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1134 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1135 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1136 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1137 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +00001138
1139 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1140
1141 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1142 val &= ~S3C64XX_SPI_MODE_4BURST;
1143 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1144 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1145 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1146
1147 flush_fifo(sdd);
1148}
1149
Thomas Abraham2b908072012-07-13 07:15:15 +09001150#ifdef CONFIG_OF
Jingoo Han75bf3362013-01-31 15:25:01 +09001151static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +09001152{
1153 struct s3c64xx_spi_info *sci;
1154 u32 temp;
1155
1156 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1157 if (!sci) {
1158 dev_err(dev, "memory allocation for spi_info failed\n");
1159 return ERR_PTR(-ENOMEM);
1160 }
1161
1162 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001163 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001164 sci->src_clk_nr = 0;
1165 } else {
1166 sci->src_clk_nr = temp;
1167 }
1168
1169 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001170 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001171 sci->num_cs = 1;
1172 } else {
1173 sci->num_cs = temp;
1174 }
1175
1176 return sci;
1177}
1178#else
1179static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1180{
1181 return dev->platform_data;
1182}
Thomas Abraham2b908072012-07-13 07:15:15 +09001183#endif
1184
1185static const struct of_device_id s3c64xx_spi_dt_match[];
1186
Thomas Abrahama5238e32012-07-13 07:15:14 +09001187static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1188 struct platform_device *pdev)
1189{
Thomas Abraham2b908072012-07-13 07:15:15 +09001190#ifdef CONFIG_OF
1191 if (pdev->dev.of_node) {
1192 const struct of_device_id *match;
1193 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1194 return (struct s3c64xx_spi_port_config *)match->data;
1195 }
1196#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001197 return (struct s3c64xx_spi_port_config *)
1198 platform_get_device_id(pdev)->driver_data;
1199}
1200
Grant Likely2deff8d2013-02-05 13:27:35 +00001201static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001202{
Thomas Abraham2b908072012-07-13 07:15:15 +09001203 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301204 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001205 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001206 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
Jassi Brar230d42d2009-11-30 07:39:42 +00001207 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001208 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001209 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001210
Thomas Abraham2b908072012-07-13 07:15:15 +09001211 if (!sci && pdev->dev.of_node) {
1212 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1213 if (IS_ERR(sci))
1214 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001215 }
1216
Thomas Abraham2b908072012-07-13 07:15:15 +09001217 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001218 dev_err(&pdev->dev, "platform_data missing!\n");
1219 return -ENODEV;
1220 }
1221
Jassi Brar230d42d2009-11-30 07:39:42 +00001222 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223 if (mem_res == NULL) {
1224 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1225 return -ENXIO;
1226 }
1227
Mark Brownc2573122011-11-10 10:57:32 +00001228 irq = platform_get_irq(pdev, 0);
1229 if (irq < 0) {
1230 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1231 return irq;
1232 }
1233
Jassi Brar230d42d2009-11-30 07:39:42 +00001234 master = spi_alloc_master(&pdev->dev,
1235 sizeof(struct s3c64xx_spi_driver_data));
1236 if (master == NULL) {
1237 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1238 return -ENOMEM;
1239 }
1240
Jassi Brar230d42d2009-11-30 07:39:42 +00001241 platform_set_drvdata(pdev, master);
1242
1243 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001244 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001245 sdd->master = master;
1246 sdd->cntrlr_info = sci;
1247 sdd->pdev = pdev;
1248 sdd->sfr_start = mem_res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001249 if (pdev->dev.of_node) {
1250 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1251 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001252 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1253 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001254 goto err0;
1255 }
1256 sdd->port_id = ret;
1257 } else {
1258 sdd->port_id = pdev->id;
1259 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001260
1261 sdd->cur_bpw = 8;
1262
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301263 if (!sdd->pdev->dev.of_node) {
1264 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1265 if (!res) {
1266 dev_err(&pdev->dev, "Unable to get SPI tx dma "
1267 "resource\n");
1268 return -ENXIO;
1269 }
1270 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001271
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301272 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1273 if (!res) {
1274 dev_err(&pdev->dev, "Unable to get SPI rx dma "
1275 "resource\n");
1276 return -ENXIO;
1277 }
1278 sdd->rx_dma.dmach = res->start;
1279 }
1280
1281 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1282 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001283
1284 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001285 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001286 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001287 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001288 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1289 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1290 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001291 master->num_chipselect = sci->num_cs;
1292 master->dma_alignment = 8;
Mark Browne761f422013-04-01 14:17:37 +01001293 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001294 /* the spi->mode bits understood by this driver: */
1295 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1296
Thierry Redingb0ee5602013-01-21 11:09:18 +01001297 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1298 if (IS_ERR(sdd->regs)) {
1299 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001300 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001301 }
1302
Thomas Abraham00ab5392013-04-15 20:42:57 -07001303 if (sci->cfg_gpio && sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001304 dev_err(&pdev->dev, "Unable to config gpio\n");
1305 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001306 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001307 }
1308
1309 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001310 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001311 if (IS_ERR(sdd->clk)) {
1312 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1313 ret = PTR_ERR(sdd->clk);
Thomas Abraham00ab5392013-04-15 20:42:57 -07001314 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001315 }
1316
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001317 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001318 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1319 ret = -EBUSY;
Thomas Abraham00ab5392013-04-15 20:42:57 -07001320 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001321 }
1322
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001323 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001324 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001325 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001326 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001327 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001328 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001329 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001330 }
1331
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001332 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001333 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001334 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001335 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001336 }
1337
Jassi Brar230d42d2009-11-30 07:39:42 +00001338 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001339 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001340
1341 spin_lock_init(&sdd->lock);
1342 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001343 INIT_LIST_HEAD(&sdd->queue);
1344
Jingoo Han4eb77002013-01-10 11:04:21 +09001345 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1346 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001347 if (ret != 0) {
1348 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1349 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001350 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001351 }
1352
1353 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1354 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1355 sdd->regs + S3C64XX_SPI_INT_EN);
1356
Jassi Brar230d42d2009-11-30 07:39:42 +00001357 if (spi_register_master(master)) {
1358 dev_err(&pdev->dev, "cannot register SPI master\n");
1359 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001360 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001361 }
1362
Jingoo Han75bf3362013-01-31 15:25:01 +09001363 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001364 sdd->port_id, master->num_chipselect);
Joe Perches8a349d42010-02-02 07:22:13 +00001365 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
Jassi Brar230d42d2009-11-30 07:39:42 +00001366 mem_res->end, mem_res->start,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001367 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001368
Mark Brownb97b6622011-12-04 00:58:06 +00001369 pm_runtime_enable(&pdev->dev);
1370
Jassi Brar230d42d2009-11-30 07:39:42 +00001371 return 0;
1372
Jassi Brar230d42d2009-11-30 07:39:42 +00001373err3:
Jingoo Han4eb77002013-01-10 11:04:21 +09001374 clk_disable_unprepare(sdd->src_clk);
1375err2:
1376 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001377err0:
1378 platform_set_drvdata(pdev, NULL);
1379 spi_master_put(master);
1380
1381 return ret;
1382}
1383
1384static int s3c64xx_spi_remove(struct platform_device *pdev)
1385{
1386 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1387 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001388
Mark Brownb97b6622011-12-04 00:58:06 +00001389 pm_runtime_disable(&pdev->dev);
1390
Jassi Brar230d42d2009-11-30 07:39:42 +00001391 spi_unregister_master(master);
1392
Mark Brownc2573122011-11-10 10:57:32 +00001393 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1394
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001395 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001396
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001397 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001398
Jassi Brar230d42d2009-11-30 07:39:42 +00001399 platform_set_drvdata(pdev, NULL);
1400 spi_master_put(master);
1401
1402 return 0;
1403}
1404
Jingoo Han997230d2013-03-22 02:09:08 +00001405#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001406static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001407{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001408 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001409 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001410
Mark Brownad2a99a2012-02-15 14:48:32 -08001411 spi_master_suspend(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001412
1413 /* Disable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001414 clk_disable_unprepare(sdd->src_clk);
1415 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001416
1417 sdd->cur_speed = 0; /* Output Clock is stopped */
1418
1419 return 0;
1420}
1421
Mark Browne25d0bf2011-12-04 00:36:18 +00001422static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001423{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001424 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001425 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001426 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001427
Thomas Abraham00ab5392013-04-15 20:42:57 -07001428 if (sci->cfg_gpio)
Thomas Abraham2b908072012-07-13 07:15:15 +09001429 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001430
1431 /* Enable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001432 clk_prepare_enable(sdd->src_clk);
1433 clk_prepare_enable(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001434
Thomas Abrahama5238e32012-07-13 07:15:14 +09001435 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001436
Mark Brownad2a99a2012-02-15 14:48:32 -08001437 spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001438
1439 return 0;
1440}
Jingoo Han997230d2013-03-22 02:09:08 +00001441#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001442
Mark Brownb97b6622011-12-04 00:58:06 +00001443#ifdef CONFIG_PM_RUNTIME
1444static int s3c64xx_spi_runtime_suspend(struct device *dev)
1445{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001446 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001447 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1448
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001449 clk_disable_unprepare(sdd->clk);
1450 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001451
1452 return 0;
1453}
1454
1455static int s3c64xx_spi_runtime_resume(struct device *dev)
1456{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001457 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001458 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1459
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001460 clk_prepare_enable(sdd->src_clk);
1461 clk_prepare_enable(sdd->clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001462
1463 return 0;
1464}
1465#endif /* CONFIG_PM_RUNTIME */
1466
Mark Browne25d0bf2011-12-04 00:36:18 +00001467static const struct dev_pm_ops s3c64xx_spi_pm = {
1468 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001469 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1470 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001471};
1472
Sachin Kamat10ce0472012-08-03 10:08:12 +05301473static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001474 .fifo_lvl_mask = { 0x7f },
1475 .rx_lvl_offset = 13,
1476 .tx_st_done = 21,
1477 .high_speed = true,
1478};
1479
Sachin Kamat10ce0472012-08-03 10:08:12 +05301480static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001481 .fifo_lvl_mask = { 0x7f, 0x7F },
1482 .rx_lvl_offset = 13,
1483 .tx_st_done = 21,
1484};
1485
Sachin Kamat10ce0472012-08-03 10:08:12 +05301486static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001487 .fifo_lvl_mask = { 0x1ff, 0x7F },
1488 .rx_lvl_offset = 15,
1489 .tx_st_done = 25,
1490};
1491
Sachin Kamat10ce0472012-08-03 10:08:12 +05301492static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001493 .fifo_lvl_mask = { 0x7f, 0x7F },
1494 .rx_lvl_offset = 13,
1495 .tx_st_done = 21,
1496 .high_speed = true,
1497};
1498
Sachin Kamat10ce0472012-08-03 10:08:12 +05301499static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001500 .fifo_lvl_mask = { 0x1ff, 0x7F },
1501 .rx_lvl_offset = 15,
1502 .tx_st_done = 25,
1503 .high_speed = true,
1504};
1505
Sachin Kamat10ce0472012-08-03 10:08:12 +05301506static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001507 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1508 .rx_lvl_offset = 15,
1509 .tx_st_done = 25,
1510 .high_speed = true,
1511 .clk_from_cmu = true,
1512};
1513
1514static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1515 {
1516 .name = "s3c2443-spi",
1517 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1518 }, {
1519 .name = "s3c6410-spi",
1520 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1521 }, {
1522 .name = "s5p64x0-spi",
1523 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1524 }, {
1525 .name = "s5pc100-spi",
1526 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1527 }, {
1528 .name = "s5pv210-spi",
1529 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1530 }, {
1531 .name = "exynos4210-spi",
1532 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1533 },
1534 { },
1535};
1536
Thomas Abraham2b908072012-07-13 07:15:15 +09001537#ifdef CONFIG_OF
1538static const struct of_device_id s3c64xx_spi_dt_match[] = {
1539 { .compatible = "samsung,exynos4210-spi",
1540 .data = (void *)&exynos4_spi_port_config,
1541 },
1542 { },
1543};
1544MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1545#endif /* CONFIG_OF */
1546
Jassi Brar230d42d2009-11-30 07:39:42 +00001547static struct platform_driver s3c64xx_spi_driver = {
1548 .driver = {
1549 .name = "s3c64xx-spi",
1550 .owner = THIS_MODULE,
Mark Browne25d0bf2011-12-04 00:36:18 +00001551 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001552 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001553 },
1554 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001555 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001556};
1557MODULE_ALIAS("platform:s3c64xx-spi");
1558
1559static int __init s3c64xx_spi_init(void)
1560{
1561 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1562}
Mark Brownd2a787f2010-09-07 11:29:17 +01001563subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001564
1565static void __exit s3c64xx_spi_exit(void)
1566{
1567 platform_driver_unregister(&s3c64xx_spi_driver);
1568}
1569module_exit(s3c64xx_spi_exit);
1570
1571MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1572MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1573MODULE_LICENSE("GPL");