blob: 2ef876d8f2335febeab465a0ab7d30068988e204 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010016#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010018#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
22#include "gmii.h"
23#include "spi.h"
24#include "falcon.h"
25#include "falcon_hwdefs.h"
26#include "falcon_io.h"
27#include "mdio_10g.h"
28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h"
31
32/* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
Ben Hutchings37b5a602008-05-30 22:27:04 +010041 * @i2c_data: Operations and state for I2C bit-bashing algorithm
Ben Hutchings8ceee662008-04-27 12:55:59 +010042 */
43struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
Ben Hutchings37b5a602008-05-30 22:27:04 +010046 struct i2c_algo_bit_data i2c_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +010047};
48
49/**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56static int disable_dma_stats;
57
58/* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65#define TX_DC_ENTRIES 16
66#define TX_DC_ENTRIES_ORDER 0
67#define TX_DC_BASE 0x130000
68
69#define RX_DC_ENTRIES 64
70#define RX_DC_ENTRIES_ORDER 2
71#define RX_DC_BASE 0x100000
72
Ben Hutchings2f7f5732008-12-12 21:34:25 -080073static const unsigned int
74/* "Large" EEPROM device: Atmel AT25640 or similar
75 * 8 KB, 16-bit address, 32 B write block */
76large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
77 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
78 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
79/* Default flash device: Atmel AT25F1024
80 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
81default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
82 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
83 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
84 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
85 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
86
Ben Hutchings8ceee662008-04-27 12:55:59 +010087/* RX FIFO XOFF watermark
88 *
89 * When the amount of the RX FIFO increases used increases past this
90 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
91 * This also has an effect on RX/TX arbitration
92 */
93static int rx_xoff_thresh_bytes = -1;
94module_param(rx_xoff_thresh_bytes, int, 0644);
95MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
96
97/* RX FIFO XON watermark
98 *
99 * When the amount of the RX FIFO used decreases below this
100 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
101 * This also has an effect on RX/TX arbitration
102 */
103static int rx_xon_thresh_bytes = -1;
104module_param(rx_xon_thresh_bytes, int, 0644);
105MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
106
107/* TX descriptor ring size - min 512 max 4k */
108#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
109#define FALCON_TXD_RING_SIZE 1024
110#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
111
112/* RX descriptor ring size - min 512 max 4k */
113#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
114#define FALCON_RXD_RING_SIZE 1024
115#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
116
117/* Event queue size - max 32k */
118#define FALCON_EVQ_ORDER EVQ_SIZE_4K
119#define FALCON_EVQ_SIZE 4096
120#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
121
122/* Max number of internal errors. After this resets will not be performed */
123#define FALCON_MAX_INT_ERRORS 4
124
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100125/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
126 */
127#define FALCON_FLUSH_INTERVAL 10
128#define FALCON_FLUSH_POLL_COUNT 100
Ben Hutchings8ceee662008-04-27 12:55:59 +0100129
130/**************************************************************************
131 *
132 * Falcon constants
133 *
134 **************************************************************************
135 */
136
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100137/* DMA address mask */
138#define FALCON_DMA_MASK DMA_BIT_MASK(46)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100139
140/* TX DMA length mask (13-bit) */
141#define FALCON_TX_DMA_MASK (4096 - 1)
142
143/* Size and alignment of special buffers (4KB) */
144#define FALCON_BUF_SIZE 4096
145
146/* Dummy SRAM size code */
147#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
148
149/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
150#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
151#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
152#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
153#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
154#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
155
156#define FALCON_IS_DUAL_FUNC(efx) \
Ben Hutchings55668612008-05-16 21:16:10 +0100157 (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100158
159/**************************************************************************
160 *
161 * Falcon hardware access
162 *
163 **************************************************************************/
164
165/* Read the current event from the event queue */
166static inline efx_qword_t *falcon_event(struct efx_channel *channel,
167 unsigned int index)
168{
169 return (((efx_qword_t *) (channel->eventq.addr)) + index);
170}
171
172/* See if an event is present
173 *
174 * We check both the high and low dword of the event for all ones. We
175 * wrote all ones when we cleared the event, and no valid event can
176 * have all ones in either its high or low dwords. This approach is
177 * robust against reordering.
178 *
179 * Note that using a single 64-bit comparison is incorrect; even
180 * though the CPU read will be atomic, the DMA write may not be.
181 */
182static inline int falcon_event_present(efx_qword_t *event)
183{
184 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
185 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
186}
187
188/**************************************************************************
189 *
190 * I2C bus - this is a bit-bashing interface using GPIO pins
191 * Note that it uses the output enables to tristate the outputs
192 * SDA is the data pin and SCL is the clock
193 *
194 **************************************************************************
195 */
Ben Hutchings37b5a602008-05-30 22:27:04 +0100196static void falcon_setsda(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100197{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100198 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100199 efx_oword_t reg;
200
Ben Hutchings37b5a602008-05-30 22:27:04 +0100201 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
202 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
203 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100204}
205
Ben Hutchings37b5a602008-05-30 22:27:04 +0100206static void falcon_setscl(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100207{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100208 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100209 efx_oword_t reg;
210
Ben Hutchings37b5a602008-05-30 22:27:04 +0100211 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
212 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
213 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
214}
215
216static int falcon_getsda(void *data)
217{
218 struct efx_nic *efx = (struct efx_nic *)data;
219 efx_oword_t reg;
220
221 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100222 return EFX_OWORD_FIELD(reg, GPIO3_IN);
223}
224
Ben Hutchings37b5a602008-05-30 22:27:04 +0100225static int falcon_getscl(void *data)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100226{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100227 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100228 efx_oword_t reg;
229
Ben Hutchings37b5a602008-05-30 22:27:04 +0100230 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
231 return EFX_OWORD_FIELD(reg, GPIO0_IN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100232}
233
Ben Hutchings37b5a602008-05-30 22:27:04 +0100234static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
235 .setsda = falcon_setsda,
236 .setscl = falcon_setscl,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100237 .getsda = falcon_getsda,
238 .getscl = falcon_getscl,
Ben Hutchings62c78322008-05-30 22:27:46 +0100239 .udelay = 5,
Ben Hutchings9dadae62008-07-18 18:59:12 +0100240 /* Wait up to 50 ms for slave to let us pull SCL high */
241 .timeout = DIV_ROUND_UP(HZ, 20),
Ben Hutchings8ceee662008-04-27 12:55:59 +0100242};
243
244/**************************************************************************
245 *
246 * Falcon special buffer handling
247 * Special buffers are used for event queues and the TX and RX
248 * descriptor rings.
249 *
250 *************************************************************************/
251
252/*
253 * Initialise a Falcon special buffer
254 *
255 * This will define a buffer (previously allocated via
256 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
257 * it to be used for event queues, descriptor rings etc.
258 */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100259static void
Ben Hutchings8ceee662008-04-27 12:55:59 +0100260falcon_init_special_buffer(struct efx_nic *efx,
261 struct efx_special_buffer *buffer)
262{
263 efx_qword_t buf_desc;
264 int index;
265 dma_addr_t dma_addr;
266 int i;
267
268 EFX_BUG_ON_PARANOID(!buffer->addr);
269
270 /* Write buffer descriptors to NIC */
271 for (i = 0; i < buffer->entries; i++) {
272 index = buffer->index + i;
273 dma_addr = buffer->dma_addr + (i * 4096);
274 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
275 index, (unsigned long long)dma_addr);
276 EFX_POPULATE_QWORD_4(buf_desc,
277 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
278 BUF_ADR_REGION, 0,
279 BUF_ADR_FBUF, (dma_addr >> 12),
280 BUF_OWNER_ID_FBUF, 0);
281 falcon_write_sram(efx, &buf_desc, index);
282 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100283}
284
285/* Unmaps a buffer from Falcon and clears the buffer table entries */
286static void
287falcon_fini_special_buffer(struct efx_nic *efx,
288 struct efx_special_buffer *buffer)
289{
290 efx_oword_t buf_tbl_upd;
291 unsigned int start = buffer->index;
292 unsigned int end = (buffer->index + buffer->entries - 1);
293
294 if (!buffer->entries)
295 return;
296
297 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
298 buffer->index, buffer->index + buffer->entries - 1);
299
300 EFX_POPULATE_OWORD_4(buf_tbl_upd,
301 BUF_UPD_CMD, 0,
302 BUF_CLR_CMD, 1,
303 BUF_CLR_END_ID, end,
304 BUF_CLR_START_ID, start);
305 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
306}
307
308/*
309 * Allocate a new Falcon special buffer
310 *
311 * This allocates memory for a new buffer, clears it and allocates a
312 * new buffer ID range. It does not write into Falcon's buffer table.
313 *
314 * This call will allocate 4KB buffers, since Falcon can't use 8KB
315 * buffers for event queues and descriptor rings.
316 */
317static int falcon_alloc_special_buffer(struct efx_nic *efx,
318 struct efx_special_buffer *buffer,
319 unsigned int len)
320{
321 struct falcon_nic_data *nic_data = efx->nic_data;
322
323 len = ALIGN(len, FALCON_BUF_SIZE);
324
325 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
326 &buffer->dma_addr);
327 if (!buffer->addr)
328 return -ENOMEM;
329 buffer->len = len;
330 buffer->entries = len / FALCON_BUF_SIZE;
331 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
332
333 /* All zeros is a potentially valid event so memset to 0xff */
334 memset(buffer->addr, 0xff, len);
335
336 /* Select new buffer ID */
337 buffer->index = nic_data->next_buffer_table;
338 nic_data->next_buffer_table += buffer->entries;
339
340 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
341 "(virt %p phys %lx)\n", buffer->index,
342 buffer->index + buffer->entries - 1,
343 (unsigned long long)buffer->dma_addr, len,
344 buffer->addr, virt_to_phys(buffer->addr));
345
346 return 0;
347}
348
349static void falcon_free_special_buffer(struct efx_nic *efx,
350 struct efx_special_buffer *buffer)
351{
352 if (!buffer->addr)
353 return;
354
355 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
356 "(virt %p phys %lx)\n", buffer->index,
357 buffer->index + buffer->entries - 1,
358 (unsigned long long)buffer->dma_addr, buffer->len,
359 buffer->addr, virt_to_phys(buffer->addr));
360
361 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
362 buffer->dma_addr);
363 buffer->addr = NULL;
364 buffer->entries = 0;
365}
366
367/**************************************************************************
368 *
369 * Falcon generic buffer handling
370 * These buffers are used for interrupt status and MAC stats
371 *
372 **************************************************************************/
373
374static int falcon_alloc_buffer(struct efx_nic *efx,
375 struct efx_buffer *buffer, unsigned int len)
376{
377 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
378 &buffer->dma_addr);
379 if (!buffer->addr)
380 return -ENOMEM;
381 buffer->len = len;
382 memset(buffer->addr, 0, len);
383 return 0;
384}
385
386static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
387{
388 if (buffer->addr) {
389 pci_free_consistent(efx->pci_dev, buffer->len,
390 buffer->addr, buffer->dma_addr);
391 buffer->addr = NULL;
392 }
393}
394
395/**************************************************************************
396 *
397 * Falcon TX path
398 *
399 **************************************************************************/
400
401/* Returns a pointer to the specified transmit descriptor in the TX
402 * descriptor queue belonging to the specified channel.
403 */
404static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
405 unsigned int index)
406{
407 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
408}
409
410/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
411static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
412{
413 unsigned write_ptr;
414 efx_dword_t reg;
415
416 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
417 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
418 falcon_writel_page(tx_queue->efx, &reg,
419 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
420}
421
422
423/* For each entry inserted into the software descriptor ring, create a
424 * descriptor in the hardware TX descriptor ring (in host memory), and
425 * write a doorbell.
426 */
427void falcon_push_buffers(struct efx_tx_queue *tx_queue)
428{
429
430 struct efx_tx_buffer *buffer;
431 efx_qword_t *txd;
432 unsigned write_ptr;
433
434 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
435
436 do {
437 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
438 buffer = &tx_queue->buffer[write_ptr];
439 txd = falcon_tx_desc(tx_queue, write_ptr);
440 ++tx_queue->write_count;
441
442 /* Create TX descriptor ring entry */
443 EFX_POPULATE_QWORD_5(*txd,
444 TX_KER_PORT, 0,
445 TX_KER_CONT, buffer->continuation,
446 TX_KER_BYTE_CNT, buffer->len,
447 TX_KER_BUF_REGION, 0,
448 TX_KER_BUF_ADR, buffer->dma_addr);
449 } while (tx_queue->write_count != tx_queue->insert_count);
450
451 wmb(); /* Ensure descriptors are written before they are fetched */
452 falcon_notify_tx_desc(tx_queue);
453}
454
455/* Allocate hardware resources for a TX queue */
456int falcon_probe_tx(struct efx_tx_queue *tx_queue)
457{
458 struct efx_nic *efx = tx_queue->efx;
459 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
460 FALCON_TXD_RING_SIZE *
461 sizeof(efx_qword_t));
462}
463
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100464void falcon_init_tx(struct efx_tx_queue *tx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100465{
466 efx_oword_t tx_desc_ptr;
467 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100468
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100469 tx_queue->flushed = false;
470
Ben Hutchings8ceee662008-04-27 12:55:59 +0100471 /* Pin TX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100472 falcon_init_special_buffer(efx, &tx_queue->txd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100473
474 /* Push TX descriptor ring to card */
475 EFX_POPULATE_OWORD_10(tx_desc_ptr,
476 TX_DESCQ_EN, 1,
477 TX_ISCSI_DDIG_EN, 0,
478 TX_ISCSI_HDIG_EN, 0,
479 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100480 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100481 TX_DESCQ_OWNER_ID, 0,
482 TX_DESCQ_LABEL, tx_queue->queue,
483 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
484 TX_DESCQ_TYPE, 0,
485 TX_NON_IP_DROP_DIS_B0, 1);
486
Ben Hutchings55668612008-05-16 21:16:10 +0100487 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings60ac1062008-09-01 12:44:59 +0100488 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
489 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
490 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100491 }
492
493 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
494 tx_queue->queue);
495
Ben Hutchings55668612008-05-16 21:16:10 +0100496 if (falcon_rev(efx) < FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100497 efx_oword_t reg;
498
Ben Hutchings60ac1062008-09-01 12:44:59 +0100499 /* Only 128 bits in this register */
500 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100501
502 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
Ben Hutchings60ac1062008-09-01 12:44:59 +0100503 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100504 clear_bit_le(tx_queue->queue, (void *)&reg);
505 else
506 set_bit_le(tx_queue->queue, (void *)&reg);
507 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
508 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100509}
510
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100511static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100512{
513 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100514 efx_oword_t tx_flush_descq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100515
516 /* Post a flush command */
517 EFX_POPULATE_OWORD_2(tx_flush_descq,
518 TX_FLUSH_DESCQ_CMD, 1,
519 TX_FLUSH_DESCQ, tx_queue->queue);
520 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100521}
522
523void falcon_fini_tx(struct efx_tx_queue *tx_queue)
524{
525 struct efx_nic *efx = tx_queue->efx;
526 efx_oword_t tx_desc_ptr;
527
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100528 /* The queue should have been flushed */
529 WARN_ON(!tx_queue->flushed);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100530
531 /* Remove TX descriptor ring from card */
532 EFX_ZERO_OWORD(tx_desc_ptr);
533 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
534 tx_queue->queue);
535
536 /* Unpin TX descriptor ring */
537 falcon_fini_special_buffer(efx, &tx_queue->txd);
538}
539
540/* Free buffers backing TX queue */
541void falcon_remove_tx(struct efx_tx_queue *tx_queue)
542{
543 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
544}
545
546/**************************************************************************
547 *
548 * Falcon RX path
549 *
550 **************************************************************************/
551
552/* Returns a pointer to the specified descriptor in the RX descriptor queue */
553static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
554 unsigned int index)
555{
556 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
557}
558
559/* This creates an entry in the RX descriptor queue */
560static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
561 unsigned index)
562{
563 struct efx_rx_buffer *rx_buf;
564 efx_qword_t *rxd;
565
566 rxd = falcon_rx_desc(rx_queue, index);
567 rx_buf = efx_rx_buffer(rx_queue, index);
568 EFX_POPULATE_QWORD_3(*rxd,
569 RX_KER_BUF_SIZE,
570 rx_buf->len -
571 rx_queue->efx->type->rx_buffer_padding,
572 RX_KER_BUF_REGION, 0,
573 RX_KER_BUF_ADR, rx_buf->dma_addr);
574}
575
576/* This writes to the RX_DESC_WPTR register for the specified receive
577 * descriptor ring.
578 */
579void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
580{
581 efx_dword_t reg;
582 unsigned write_ptr;
583
584 while (rx_queue->notified_count != rx_queue->added_count) {
585 falcon_build_rx_desc(rx_queue,
586 rx_queue->notified_count &
587 FALCON_RXD_RING_MASK);
588 ++rx_queue->notified_count;
589 }
590
591 wmb();
592 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
593 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
594 falcon_writel_page(rx_queue->efx, &reg,
595 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
596}
597
598int falcon_probe_rx(struct efx_rx_queue *rx_queue)
599{
600 struct efx_nic *efx = rx_queue->efx;
601 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
602 FALCON_RXD_RING_SIZE *
603 sizeof(efx_qword_t));
604}
605
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100606void falcon_init_rx(struct efx_rx_queue *rx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100607{
608 efx_oword_t rx_desc_ptr;
609 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100610 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
611 bool iscsi_digest_en = is_b0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100612
613 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
614 rx_queue->queue, rx_queue->rxd.index,
615 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
616
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100617 rx_queue->flushed = false;
618
Ben Hutchings8ceee662008-04-27 12:55:59 +0100619 /* Pin RX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100620 falcon_init_special_buffer(efx, &rx_queue->rxd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100621
622 /* Push RX descriptor ring to card */
623 EFX_POPULATE_OWORD_10(rx_desc_ptr,
624 RX_ISCSI_DDIG_EN, iscsi_digest_en,
625 RX_ISCSI_HDIG_EN, iscsi_digest_en,
626 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100627 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100628 RX_DESCQ_OWNER_ID, 0,
629 RX_DESCQ_LABEL, rx_queue->queue,
630 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
631 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
632 /* For >=B0 this is scatter so disable */
633 RX_DESCQ_JUMBO, !is_b0,
634 RX_DESCQ_EN, 1);
635 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
636 rx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100637}
638
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100639static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100640{
641 struct efx_nic *efx = rx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100642 efx_oword_t rx_flush_descq;
643
644 /* Post a flush command */
645 EFX_POPULATE_OWORD_2(rx_flush_descq,
646 RX_FLUSH_DESCQ_CMD, 1,
647 RX_FLUSH_DESCQ, rx_queue->queue);
648 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100649}
650
651void falcon_fini_rx(struct efx_rx_queue *rx_queue)
652{
653 efx_oword_t rx_desc_ptr;
654 struct efx_nic *efx = rx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100655
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100656 /* The queue should already have been flushed */
657 WARN_ON(!rx_queue->flushed);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100658
659 /* Remove RX descriptor ring from card */
660 EFX_ZERO_OWORD(rx_desc_ptr);
661 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
662 rx_queue->queue);
663
664 /* Unpin RX descriptor ring */
665 falcon_fini_special_buffer(efx, &rx_queue->rxd);
666}
667
668/* Free buffers backing RX queue */
669void falcon_remove_rx(struct efx_rx_queue *rx_queue)
670{
671 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
672}
673
674/**************************************************************************
675 *
676 * Falcon event queue processing
677 * Event queues are processed by per-channel tasklets.
678 *
679 **************************************************************************/
680
681/* Update a channel's event queue's read pointer (RPTR) register
682 *
683 * This writes the EVQ_RPTR_REG register for the specified channel's
684 * event queue.
685 *
686 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
687 * whereas channel->eventq_read_ptr contains the index of the "next to
688 * read" event.
689 */
690void falcon_eventq_read_ack(struct efx_channel *channel)
691{
692 efx_dword_t reg;
693 struct efx_nic *efx = channel->efx;
694
695 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
696 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100697 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100698}
699
700/* Use HW to insert a SW defined event */
701void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
702{
703 efx_oword_t drv_ev_reg;
704
705 EFX_POPULATE_OWORD_2(drv_ev_reg,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100706 DRV_EV_QID, channel->channel,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100707 DRV_EV_DATA,
708 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
709 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
710}
711
712/* Handle a transmit completion event
713 *
714 * Falcon batches TX completion events; the message we receive is of
715 * the form "complete all TX events up to this index".
716 */
Ben Hutchings4d566062008-09-01 12:47:12 +0100717static void falcon_handle_tx_event(struct efx_channel *channel,
718 efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100719{
720 unsigned int tx_ev_desc_ptr;
721 unsigned int tx_ev_q_label;
722 struct efx_tx_queue *tx_queue;
723 struct efx_nic *efx = channel->efx;
724
725 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
726 /* Transmit completion */
727 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
728 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
729 tx_queue = &efx->tx_queue[tx_ev_q_label];
730 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
731 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
732 /* Rewrite the FIFO write pointer */
733 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
734 tx_queue = &efx->tx_queue[tx_ev_q_label];
735
Ben Hutchings55668612008-05-16 21:16:10 +0100736 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100737 netif_tx_lock(efx->net_dev);
738 falcon_notify_tx_desc(tx_queue);
Ben Hutchings55668612008-05-16 21:16:10 +0100739 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100740 netif_tx_unlock(efx->net_dev);
741 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
742 EFX_WORKAROUND_10727(efx)) {
743 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
744 } else {
745 EFX_ERR(efx, "channel %d unexpected TX event "
746 EFX_QWORD_FMT"\n", channel->channel,
747 EFX_QWORD_VAL(*event));
748 }
749}
750
Ben Hutchings8ceee662008-04-27 12:55:59 +0100751/* Detect errors included in the rx_evt_pkt_ok bit. */
752static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
753 const efx_qword_t *event,
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100754 bool *rx_ev_pkt_ok,
755 bool *discard)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100756{
757 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100758 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
759 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
760 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
761 bool rx_ev_other_err, rx_ev_pause_frm;
762 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
763 unsigned rx_ev_pkt_type;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100764
765 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
766 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
767 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
768 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
769 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
770 RX_EV_BUF_OWNER_ID_ERR);
771 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
772 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
773 RX_EV_IP_HDR_CHKSUM_ERR);
774 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
775 RX_EV_TCP_UDP_CHKSUM_ERR);
776 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
777 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
Ben Hutchings55668612008-05-16 21:16:10 +0100778 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
Ben Hutchings8ceee662008-04-27 12:55:59 +0100779 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
780 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
781
782 /* Every error apart from tobe_disc and pause_frm */
783 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
784 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
785 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
786
Ben Hutchings8ceee662008-04-27 12:55:59 +0100787 /* Count errors that are not in MAC stats. */
788 if (rx_ev_frm_trunc)
789 ++rx_queue->channel->n_rx_frm_trunc;
790 else if (rx_ev_tobe_disc)
791 ++rx_queue->channel->n_rx_tobe_disc;
792 else if (rx_ev_ip_hdr_chksum_err)
793 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
794 else if (rx_ev_tcp_udp_chksum_err)
795 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
796 if (rx_ev_ip_frag_err)
797 ++rx_queue->channel->n_rx_ip_frag_err;
798
799 /* The frame must be discarded if any of these are true. */
800 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
801 rx_ev_tobe_disc | rx_ev_pause_frm);
802
803 /* TOBE_DISC is expected on unicast mismatches; don't print out an
804 * error message. FRM_TRUNC indicates RXDP dropped the packet due
805 * to a FIFO overflow.
806 */
807#ifdef EFX_ENABLE_DEBUG
808 if (rx_ev_other_err) {
809 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100810 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
Ben Hutchings8ceee662008-04-27 12:55:59 +0100811 rx_queue->queue, EFX_QWORD_VAL(*event),
812 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
813 rx_ev_ip_hdr_chksum_err ?
814 " [IP_HDR_CHKSUM_ERR]" : "",
815 rx_ev_tcp_udp_chksum_err ?
816 " [TCP_UDP_CHKSUM_ERR]" : "",
817 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
818 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
819 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
820 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100821 rx_ev_pause_frm ? " [PAUSE]" : "");
Ben Hutchings8ceee662008-04-27 12:55:59 +0100822 }
823#endif
824
825 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
826 efx->phy_type == PHY_TYPE_10XPRESS))
827 tenxpress_crc_err(efx);
828}
829
830/* Handle receive events that are not in-order. */
831static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
832 unsigned index)
833{
834 struct efx_nic *efx = rx_queue->efx;
835 unsigned expected, dropped;
836
837 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
838 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
839 FALCON_RXD_RING_MASK);
840 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
841 dropped, index, expected);
842
843 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
844 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
845}
846
847/* Handle a packet received event
848 *
849 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
850 * wrong destination address
851 * Also "is multicast" and "matches multicast filter" flags can be used to
852 * discard non-matching multicast packets.
853 */
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100854static void falcon_handle_rx_event(struct efx_channel *channel,
855 const efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100856{
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100857 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100858 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100859 unsigned expected_ptr;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100860 bool rx_ev_pkt_ok, discard = false, checksummed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100861 struct efx_rx_queue *rx_queue;
862 struct efx_nic *efx = channel->efx;
863
864 /* Basic packet information */
865 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
866 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
867 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
868 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
869 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100870 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100871
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100872 rx_queue = &efx->rx_queue[channel->channel];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100873
874 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
875 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100876 if (unlikely(rx_ev_desc_ptr != expected_ptr))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100877 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100878
879 if (likely(rx_ev_pkt_ok)) {
880 /* If packet is marked as OK and packet type is TCP/IPv4 or
881 * UDP/IPv4, then we can rely on the hardware checksum.
882 */
883 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
884 } else {
885 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100886 &discard);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100887 checksummed = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100888 }
889
890 /* Detect multicast packets that didn't match the filter */
891 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
892 if (rx_ev_mcast_pkt) {
893 unsigned int rx_ev_mcast_hash_match =
894 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
895
896 if (unlikely(!rx_ev_mcast_hash_match))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100897 discard = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100898 }
899
900 /* Handle received packet */
901 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
902 checksummed, discard);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100903}
904
905/* Global events are basically PHY events */
906static void falcon_handle_global_event(struct efx_channel *channel,
907 efx_qword_t *event)
908{
909 struct efx_nic *efx = channel->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100910 bool is_phy_event = false, handled = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100911
912 /* Check for interrupt on either port. Some boards have a
913 * single PHY wired to the interrupt line for port 1. */
914 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
915 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
916 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100917 is_phy_event = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100918
Ben Hutchings55668612008-05-16 21:16:10 +0100919 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
Steve Hodgson92ade882008-09-01 12:49:29 +0100920 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100921 is_phy_event = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100922
923 if (is_phy_event) {
924 efx->phy_op->clear_interrupt(efx);
925 queue_work(efx->workqueue, &efx->reconfigure_work);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100926 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100927 }
928
929 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
930 EFX_ERR(efx, "channel %d seen global RX_RESET "
931 "event. Resetting.\n", channel->channel);
932
933 atomic_inc(&efx->rx_reset);
934 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
935 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100936 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100937 }
938
939 if (!handled)
940 EFX_ERR(efx, "channel %d unknown global event "
941 EFX_QWORD_FMT "\n", channel->channel,
942 EFX_QWORD_VAL(*event));
943}
944
945static void falcon_handle_driver_event(struct efx_channel *channel,
946 efx_qword_t *event)
947{
948 struct efx_nic *efx = channel->efx;
949 unsigned int ev_sub_code;
950 unsigned int ev_sub_data;
951
952 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
953 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
954
955 switch (ev_sub_code) {
956 case TX_DESCQ_FLS_DONE_EV_DECODE:
957 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
958 channel->channel, ev_sub_data);
959 break;
960 case RX_DESCQ_FLS_DONE_EV_DECODE:
961 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
962 channel->channel, ev_sub_data);
963 break;
964 case EVQ_INIT_DONE_EV_DECODE:
965 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
966 channel->channel, ev_sub_data);
967 break;
968 case SRM_UPD_DONE_EV_DECODE:
969 EFX_TRACE(efx, "channel %d SRAM update done\n",
970 channel->channel);
971 break;
972 case WAKE_UP_EV_DECODE:
973 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
974 channel->channel, ev_sub_data);
975 break;
976 case TIMER_EV_DECODE:
977 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
978 channel->channel, ev_sub_data);
979 break;
980 case RX_RECOVERY_EV_DECODE:
981 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
982 "Resetting.\n", channel->channel);
Ben Hutchings05e3ec02008-05-07 13:00:39 +0100983 atomic_inc(&efx->rx_reset);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100984 efx_schedule_reset(efx,
985 EFX_WORKAROUND_6555(efx) ?
986 RESET_TYPE_RX_RECOVERY :
987 RESET_TYPE_DISABLE);
988 break;
989 case RX_DSC_ERROR_EV_DECODE:
990 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
991 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
992 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
993 break;
994 case TX_DSC_ERROR_EV_DECODE:
995 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
996 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
997 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
998 break;
999 default:
1000 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1001 "data %04x\n", channel->channel, ev_sub_code,
1002 ev_sub_data);
1003 break;
1004 }
1005}
1006
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001007int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001008{
1009 unsigned int read_ptr;
1010 efx_qword_t event, *p_event;
1011 int ev_code;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001012 int rx_packets = 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001013
1014 read_ptr = channel->eventq_read_ptr;
1015
1016 do {
1017 p_event = falcon_event(channel, read_ptr);
1018 event = *p_event;
1019
1020 if (!falcon_event_present(&event))
1021 /* End of events */
1022 break;
1023
1024 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1025 channel->channel, EFX_QWORD_VAL(event));
1026
1027 /* Clear this event by marking it all ones */
1028 EFX_SET_QWORD(*p_event);
1029
1030 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1031
1032 switch (ev_code) {
1033 case RX_IP_EV_DECODE:
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001034 falcon_handle_rx_event(channel, &event);
1035 ++rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001036 break;
1037 case TX_IP_EV_DECODE:
1038 falcon_handle_tx_event(channel, &event);
1039 break;
1040 case DRV_GEN_EV_DECODE:
1041 channel->eventq_magic
1042 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1043 EFX_LOG(channel->efx, "channel %d received generated "
1044 "event "EFX_QWORD_FMT"\n", channel->channel,
1045 EFX_QWORD_VAL(event));
1046 break;
1047 case GLOBAL_EV_DECODE:
1048 falcon_handle_global_event(channel, &event);
1049 break;
1050 case DRIVER_EV_DECODE:
1051 falcon_handle_driver_event(channel, &event);
1052 break;
1053 default:
1054 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1055 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1056 ev_code, EFX_QWORD_VAL(event));
1057 }
1058
1059 /* Increment read pointer */
1060 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1061
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001062 } while (rx_packets < rx_quota);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001063
1064 channel->eventq_read_ptr = read_ptr;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001065 return rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001066}
1067
1068void falcon_set_int_moderation(struct efx_channel *channel)
1069{
1070 efx_dword_t timer_cmd;
1071 struct efx_nic *efx = channel->efx;
1072
1073 /* Set timer register */
1074 if (channel->irq_moderation) {
1075 /* Round to resolution supported by hardware. The value we
1076 * program is based at 0. So actual interrupt moderation
1077 * achieved is ((x + 1) * res).
1078 */
1079 unsigned int res = 5;
1080 channel->irq_moderation -= (channel->irq_moderation % res);
1081 if (channel->irq_moderation < res)
1082 channel->irq_moderation = res;
1083 EFX_POPULATE_DWORD_2(timer_cmd,
1084 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1085 TIMER_VAL,
1086 (channel->irq_moderation / res) - 1);
1087 } else {
1088 EFX_POPULATE_DWORD_2(timer_cmd,
1089 TIMER_MODE, TIMER_MODE_DIS,
1090 TIMER_VAL, 0);
1091 }
1092 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001093 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001094
1095}
1096
1097/* Allocate buffer table entries for event queue */
1098int falcon_probe_eventq(struct efx_channel *channel)
1099{
1100 struct efx_nic *efx = channel->efx;
1101 unsigned int evq_size;
1102
1103 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1104 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1105}
1106
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001107void falcon_init_eventq(struct efx_channel *channel)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001108{
1109 efx_oword_t evq_ptr;
1110 struct efx_nic *efx = channel->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001111
1112 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1113 channel->channel, channel->eventq.index,
1114 channel->eventq.index + channel->eventq.entries - 1);
1115
1116 /* Pin event queue buffer */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001117 falcon_init_special_buffer(efx, &channel->eventq);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001118
1119 /* Fill event queue with all ones (i.e. empty events) */
1120 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1121
1122 /* Push event queue to card */
1123 EFX_POPULATE_OWORD_3(evq_ptr,
1124 EVQ_EN, 1,
1125 EVQ_SIZE, FALCON_EVQ_ORDER,
1126 EVQ_BUF_BASE_ID, channel->eventq.index);
1127 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001128 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001129
1130 falcon_set_int_moderation(channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001131}
1132
1133void falcon_fini_eventq(struct efx_channel *channel)
1134{
1135 efx_oword_t eventq_ptr;
1136 struct efx_nic *efx = channel->efx;
1137
1138 /* Remove event queue from card */
1139 EFX_ZERO_OWORD(eventq_ptr);
1140 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +01001141 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001142
1143 /* Unpin event queue */
1144 falcon_fini_special_buffer(efx, &channel->eventq);
1145}
1146
1147/* Free buffers backing event queue */
1148void falcon_remove_eventq(struct efx_channel *channel)
1149{
1150 falcon_free_special_buffer(channel->efx, &channel->eventq);
1151}
1152
1153
1154/* Generates a test event on the event queue. A subsequent call to
1155 * process_eventq() should pick up the event and place the value of
1156 * "magic" into channel->eventq_magic;
1157 */
1158void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1159{
1160 efx_qword_t test_event;
1161
1162 EFX_POPULATE_QWORD_2(test_event,
1163 EV_CODE, DRV_GEN_EV_DECODE,
1164 EVQ_MAGIC, magic);
1165 falcon_generate_event(channel, &test_event);
1166}
1167
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001168/**************************************************************************
1169 *
1170 * Flush handling
1171 *
1172 **************************************************************************/
1173
1174
1175static void falcon_poll_flush_events(struct efx_nic *efx)
1176{
1177 struct efx_channel *channel = &efx->channel[0];
1178 struct efx_tx_queue *tx_queue;
1179 struct efx_rx_queue *rx_queue;
1180 unsigned int read_ptr, i;
1181
1182 read_ptr = channel->eventq_read_ptr;
1183 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1184 efx_qword_t *event = falcon_event(channel, read_ptr);
1185 int ev_code, ev_sub_code, ev_queue;
1186 bool ev_failed;
1187 if (!falcon_event_present(event))
1188 break;
1189
1190 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1191 if (ev_code != DRIVER_EV_DECODE)
1192 continue;
1193
1194 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1195 switch (ev_sub_code) {
1196 case TX_DESCQ_FLS_DONE_EV_DECODE:
1197 ev_queue = EFX_QWORD_FIELD(*event,
1198 DRIVER_EV_TX_DESCQ_ID);
1199 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1200 tx_queue = efx->tx_queue + ev_queue;
1201 tx_queue->flushed = true;
1202 }
1203 break;
1204 case RX_DESCQ_FLS_DONE_EV_DECODE:
1205 ev_queue = EFX_QWORD_FIELD(*event,
1206 DRIVER_EV_RX_DESCQ_ID);
1207 ev_failed = EFX_QWORD_FIELD(*event,
1208 DRIVER_EV_RX_FLUSH_FAIL);
1209 if (ev_queue < efx->n_rx_queues) {
1210 rx_queue = efx->rx_queue + ev_queue;
1211
1212 /* retry the rx flush */
1213 if (ev_failed)
1214 falcon_flush_rx_queue(rx_queue);
1215 else
1216 rx_queue->flushed = true;
1217 }
1218 break;
1219 }
1220
1221 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1222 }
1223}
1224
1225/* Handle tx and rx flushes at the same time, since they run in
1226 * parallel in the hardware and there's no reason for us to
1227 * serialise them */
1228int falcon_flush_queues(struct efx_nic *efx)
1229{
1230 struct efx_rx_queue *rx_queue;
1231 struct efx_tx_queue *tx_queue;
1232 int i;
1233 bool outstanding;
1234
1235 /* Issue flush requests */
1236 efx_for_each_tx_queue(tx_queue, efx) {
1237 tx_queue->flushed = false;
1238 falcon_flush_tx_queue(tx_queue);
1239 }
1240 efx_for_each_rx_queue(rx_queue, efx) {
1241 rx_queue->flushed = false;
1242 falcon_flush_rx_queue(rx_queue);
1243 }
1244
1245 /* Poll the evq looking for flush completions. Since we're not pushing
1246 * any more rx or tx descriptors at this point, we're in no danger of
1247 * overflowing the evq whilst we wait */
1248 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1249 msleep(FALCON_FLUSH_INTERVAL);
1250 falcon_poll_flush_events(efx);
1251
1252 /* Check if every queue has been succesfully flushed */
1253 outstanding = false;
1254 efx_for_each_tx_queue(tx_queue, efx)
1255 outstanding |= !tx_queue->flushed;
1256 efx_for_each_rx_queue(rx_queue, efx)
1257 outstanding |= !rx_queue->flushed;
1258 if (!outstanding)
1259 return 0;
1260 }
1261
1262 /* Mark the queues as all flushed. We're going to return failure
1263 * leading to a reset, or fake up success anyway. "flushed" now
1264 * indicates that we tried to flush. */
1265 efx_for_each_tx_queue(tx_queue, efx) {
1266 if (!tx_queue->flushed)
1267 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1268 tx_queue->queue);
1269 tx_queue->flushed = true;
1270 }
1271 efx_for_each_rx_queue(rx_queue, efx) {
1272 if (!rx_queue->flushed)
1273 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1274 rx_queue->queue);
1275 rx_queue->flushed = true;
1276 }
1277
1278 if (EFX_WORKAROUND_7803(efx))
1279 return 0;
1280
1281 return -ETIMEDOUT;
1282}
Ben Hutchings8ceee662008-04-27 12:55:59 +01001283
1284/**************************************************************************
1285 *
1286 * Falcon hardware interrupts
1287 * The hardware interrupt handler does very little work; all the event
1288 * queue processing is carried out by per-channel tasklets.
1289 *
1290 **************************************************************************/
1291
1292/* Enable/disable/generate Falcon interrupts */
1293static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1294 int force)
1295{
1296 efx_oword_t int_en_reg_ker;
1297
1298 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1299 KER_INT_KER, force,
1300 DRV_INT_EN_KER, enabled);
1301 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1302}
1303
1304void falcon_enable_interrupts(struct efx_nic *efx)
1305{
1306 efx_oword_t int_adr_reg_ker;
1307 struct efx_channel *channel;
1308
1309 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1310 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1311
1312 /* Program address */
1313 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1314 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1315 INT_ADR_KER, efx->irq_status.dma_addr);
1316 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1317
1318 /* Enable interrupts */
1319 falcon_interrupts(efx, 1, 0);
1320
1321 /* Force processing of all the channels to get the EVQ RPTRs up to
1322 date */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001323 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001324 efx_schedule_channel(channel);
1325}
1326
1327void falcon_disable_interrupts(struct efx_nic *efx)
1328{
1329 /* Disable interrupts */
1330 falcon_interrupts(efx, 0, 0);
1331}
1332
1333/* Generate a Falcon test interrupt
1334 * Interrupt must already have been enabled, otherwise nasty things
1335 * may happen.
1336 */
1337void falcon_generate_interrupt(struct efx_nic *efx)
1338{
1339 falcon_interrupts(efx, 1, 1);
1340}
1341
1342/* Acknowledge a legacy interrupt from Falcon
1343 *
1344 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1345 *
1346 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1347 * BIU. Interrupt acknowledge is read sensitive so must write instead
1348 * (then read to ensure the BIU collector is flushed)
1349 *
1350 * NB most hardware supports MSI interrupts
1351 */
1352static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1353{
1354 efx_dword_t reg;
1355
1356 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1357 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1358 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1359}
1360
1361/* Process a fatal interrupt
1362 * Disable bus mastering ASAP and schedule a reset
1363 */
1364static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1365{
1366 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001367 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001368 efx_oword_t fatal_intr;
1369 int error, mem_perr;
1370 static int n_int_errors;
1371
1372 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1373 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1374
1375 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1376 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1377 EFX_OWORD_VAL(fatal_intr),
1378 error ? "disabling bus mastering" : "no recognised error");
1379 if (error == 0)
1380 goto out;
1381
1382 /* If this is a memory parity error dump which blocks are offending */
1383 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1384 if (mem_perr) {
1385 efx_oword_t reg;
1386 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1387 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1388 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1389 }
1390
Ben Hutchings0a62f1a2008-09-01 12:50:14 +01001391 /* Disable both devices */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001392 pci_disable_device(efx->pci_dev);
1393 if (FALCON_IS_DUAL_FUNC(efx))
1394 pci_disable_device(nic_data->pci_dev2);
Ben Hutchings0a62f1a2008-09-01 12:50:14 +01001395 falcon_disable_interrupts(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001396
1397 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1398 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1399 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1400 } else {
1401 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1402 "NIC will be disabled\n");
1403 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1404 }
1405out:
1406 return IRQ_HANDLED;
1407}
1408
1409/* Handle a legacy interrupt from Falcon
1410 * Acknowledges the interrupt and schedule event queue processing.
1411 */
1412static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1413{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001414 struct efx_nic *efx = dev_id;
1415 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001416 struct efx_channel *channel;
1417 efx_dword_t reg;
1418 u32 queues;
1419 int syserr;
1420
1421 /* Read the ISR which also ACKs the interrupts */
1422 falcon_readl(efx, &reg, INT_ISR0_B0);
1423 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1424
1425 /* Check to see if we have a serious error condition */
1426 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1427 if (unlikely(syserr))
1428 return falcon_fatal_interrupt(efx);
1429
1430 if (queues == 0)
1431 return IRQ_NONE;
1432
1433 efx->last_irq_cpu = raw_smp_processor_id();
1434 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1435 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1436
1437 /* Schedule processing of any interrupting queues */
1438 channel = &efx->channel[0];
1439 while (queues) {
1440 if (queues & 0x01)
1441 efx_schedule_channel(channel);
1442 channel++;
1443 queues >>= 1;
1444 }
1445
1446 return IRQ_HANDLED;
1447}
1448
1449
1450static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1451{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001452 struct efx_nic *efx = dev_id;
1453 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001454 struct efx_channel *channel;
1455 int syserr;
1456 int queues;
1457
1458 /* Check to see if this is our interrupt. If it isn't, we
1459 * exit without having touched the hardware.
1460 */
1461 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1462 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1463 raw_smp_processor_id());
1464 return IRQ_NONE;
1465 }
1466 efx->last_irq_cpu = raw_smp_processor_id();
1467 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1468 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1469
1470 /* Check to see if we have a serious error condition */
1471 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1472 if (unlikely(syserr))
1473 return falcon_fatal_interrupt(efx);
1474
1475 /* Determine interrupting queues, clear interrupt status
1476 * register and acknowledge the device interrupt.
1477 */
1478 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1479 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1480 EFX_ZERO_OWORD(*int_ker);
1481 wmb(); /* Ensure the vector is cleared before interrupt ack */
1482 falcon_irq_ack_a1(efx);
1483
1484 /* Schedule processing of any interrupting queues */
1485 channel = &efx->channel[0];
1486 while (queues) {
1487 if (queues & 0x01)
1488 efx_schedule_channel(channel);
1489 channel++;
1490 queues >>= 1;
1491 }
1492
1493 return IRQ_HANDLED;
1494}
1495
1496/* Handle an MSI interrupt from Falcon
1497 *
1498 * Handle an MSI hardware interrupt. This routine schedules event
1499 * queue processing. No interrupt acknowledgement cycle is necessary.
1500 * Also, we never need to check that the interrupt is for us, since
1501 * MSI interrupts cannot be shared.
1502 */
1503static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1504{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001505 struct efx_channel *channel = dev_id;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001506 struct efx_nic *efx = channel->efx;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001507 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001508 int syserr;
1509
1510 efx->last_irq_cpu = raw_smp_processor_id();
1511 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1512 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1513
1514 /* Check to see if we have a serious error condition */
1515 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1516 if (unlikely(syserr))
1517 return falcon_fatal_interrupt(efx);
1518
1519 /* Schedule processing of the channel */
1520 efx_schedule_channel(channel);
1521
1522 return IRQ_HANDLED;
1523}
1524
1525
1526/* Setup RSS indirection table.
1527 * This maps from the hash value of the packet to RXQ
1528 */
1529static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1530{
1531 int i = 0;
1532 unsigned long offset;
1533 efx_dword_t dword;
1534
Ben Hutchings55668612008-05-16 21:16:10 +01001535 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001536 return;
1537
1538 for (offset = RX_RSS_INDIR_TBL_B0;
1539 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1540 offset += 0x10) {
1541 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
Ben Hutchings8831da72008-09-01 12:47:48 +01001542 i % efx->n_rx_queues);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001543 falcon_writel(efx, &dword, offset);
1544 i++;
1545 }
1546}
1547
1548/* Hook interrupt handler(s)
1549 * Try MSI and then legacy interrupts.
1550 */
1551int falcon_init_interrupt(struct efx_nic *efx)
1552{
1553 struct efx_channel *channel;
1554 int rc;
1555
1556 if (!EFX_INT_MODE_USE_MSI(efx)) {
1557 irq_handler_t handler;
Ben Hutchings55668612008-05-16 21:16:10 +01001558 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001559 handler = falcon_legacy_interrupt_b0;
1560 else
1561 handler = falcon_legacy_interrupt_a1;
1562
1563 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1564 efx->name, efx);
1565 if (rc) {
1566 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1567 efx->pci_dev->irq);
1568 goto fail1;
1569 }
1570 return 0;
1571 }
1572
1573 /* Hook MSI or MSI-X interrupt */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001574 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001575 rc = request_irq(channel->irq, falcon_msi_interrupt,
1576 IRQF_PROBE_SHARED, /* Not shared */
1577 efx->name, channel);
1578 if (rc) {
1579 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1580 goto fail2;
1581 }
1582 }
1583
1584 return 0;
1585
1586 fail2:
Ben Hutchings64ee3122008-09-01 12:47:38 +01001587 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001588 free_irq(channel->irq, channel);
1589 fail1:
1590 return rc;
1591}
1592
1593void falcon_fini_interrupt(struct efx_nic *efx)
1594{
1595 struct efx_channel *channel;
1596 efx_oword_t reg;
1597
1598 /* Disable MSI/MSI-X interrupts */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001599 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001600 if (channel->irq)
1601 free_irq(channel->irq, channel);
Ben Hutchingsb3475642008-05-16 21:15:49 +01001602 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001603
1604 /* ACK legacy interrupt */
Ben Hutchings55668612008-05-16 21:16:10 +01001605 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001606 falcon_read(efx, &reg, INT_ISR0_B0);
1607 else
1608 falcon_irq_ack_a1(efx);
1609
1610 /* Disable legacy interrupt */
1611 if (efx->legacy_irq)
1612 free_irq(efx->legacy_irq, efx);
1613}
1614
1615/**************************************************************************
1616 *
1617 * EEPROM/flash
1618 *
1619 **************************************************************************
1620 */
1621
Ben Hutchings23d30f02008-12-12 21:56:11 -08001622#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001623
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001624static int falcon_spi_poll(struct efx_nic *efx)
1625{
1626 efx_oword_t reg;
1627 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1628 return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1629}
1630
Ben Hutchings8ceee662008-04-27 12:55:59 +01001631/* Wait for SPI command completion */
1632static int falcon_spi_wait(struct efx_nic *efx)
1633{
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001634 /* Most commands will finish quickly, so we start polling at
1635 * very short intervals. Sometimes the command may have to
1636 * wait for VPD or expansion ROM access outside of our
1637 * control, so we allow up to 100 ms. */
1638 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1639 int i;
1640
1641 for (i = 0; i < 10; i++) {
1642 if (!falcon_spi_poll(efx))
1643 return 0;
1644 udelay(10);
1645 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001646
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001647 for (;;) {
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001648 if (!falcon_spi_poll(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001649 return 0;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001650 if (time_after_eq(jiffies, timeout)) {
1651 EFX_ERR(efx, "timed out waiting for SPI\n");
1652 return -ETIMEDOUT;
1653 }
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001654 schedule_timeout_uninterruptible(1);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001655 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001656}
1657
Ben Hutchingsf4150722008-11-04 20:34:28 +00001658int falcon_spi_cmd(const struct efx_spi_device *spi,
1659 unsigned int command, int address,
Ben Hutchings23d30f02008-12-12 21:56:11 -08001660 const void *in, void *out, size_t len)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001661{
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001662 struct efx_nic *efx = spi->efx;
1663 bool addressed = (address >= 0);
1664 bool reading = (out != NULL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001665 efx_oword_t reg;
1666 int rc;
1667
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001668 /* Input validation */
1669 if (len > FALCON_SPI_MAX_LEN)
1670 return -EINVAL;
Ben Hutchingsf4150722008-11-04 20:34:28 +00001671 BUG_ON(!mutex_is_locked(&efx->spi_lock));
Ben Hutchings8ceee662008-04-27 12:55:59 +01001672
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001673 /* Check that previous command is not still running */
1674 rc = falcon_spi_poll(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001675 if (rc)
1676 return rc;
1677
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001678 /* Program address register, if we have an address */
1679 if (addressed) {
1680 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1681 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1682 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001683
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001684 /* Program data register, if we have data */
1685 if (in != NULL) {
1686 memcpy(&reg, in, len);
1687 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1688 }
1689
1690 /* Issue read/write command */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001691 EFX_POPULATE_OWORD_7(reg,
1692 EE_SPI_HCMD_CMD_EN, 1,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001693 EE_SPI_HCMD_SF_SEL, spi->device_id,
Ben Hutchings8ceee662008-04-27 12:55:59 +01001694 EE_SPI_HCMD_DABCNT, len,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001695 EE_SPI_HCMD_READ, reading,
Ben Hutchings8ceee662008-04-27 12:55:59 +01001696 EE_SPI_HCMD_DUBCNT, 0,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001697 EE_SPI_HCMD_ADBCNT,
1698 (addressed ? spi->addr_len : 0),
Ben Hutchings8ceee662008-04-27 12:55:59 +01001699 EE_SPI_HCMD_ENC, command);
1700 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1701
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001702 /* Wait for read/write to complete */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001703 rc = falcon_spi_wait(efx);
1704 if (rc)
1705 return rc;
1706
1707 /* Read data */
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001708 if (out != NULL) {
1709 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1710 memcpy(out, &reg, len);
1711 }
1712
Ben Hutchings8ceee662008-04-27 12:55:59 +01001713 return 0;
1714}
1715
Ben Hutchings23d30f02008-12-12 21:56:11 -08001716static size_t
1717falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001718{
1719 return min(FALCON_SPI_MAX_LEN,
1720 (spi->block_size - (start & (spi->block_size - 1))));
1721}
1722
1723static inline u8
1724efx_spi_munge_command(const struct efx_spi_device *spi,
1725 const u8 command, const unsigned int address)
1726{
1727 return command | (((address >> 8) & spi->munge_address) << 3);
1728}
1729
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001730/* Wait up to 10 ms for buffered write completion */
1731int falcon_spi_wait_write(const struct efx_spi_device *spi)
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001732{
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001733 struct efx_nic *efx = spi->efx;
1734 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001735 u8 status;
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001736 int rc;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001737
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001738 for (;;) {
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001739 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1740 &status, sizeof(status));
1741 if (rc)
1742 return rc;
1743 if (!(status & SPI_STATUS_NRDY))
1744 return 0;
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001745 if (time_after_eq(jiffies, timeout)) {
1746 EFX_ERR(efx, "SPI write timeout on device %d"
1747 " last status=0x%02x\n",
1748 spi->device_id, status);
1749 return -ETIMEDOUT;
1750 }
1751 schedule_timeout_uninterruptible(1);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001752 }
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001753}
1754
1755int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1756 size_t len, size_t *retlen, u8 *buffer)
1757{
Ben Hutchings23d30f02008-12-12 21:56:11 -08001758 size_t block_len, pos = 0;
1759 unsigned int command;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001760 int rc = 0;
1761
1762 while (pos < len) {
Ben Hutchings23d30f02008-12-12 21:56:11 -08001763 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001764
1765 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1766 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1767 buffer + pos, block_len);
1768 if (rc)
1769 break;
1770 pos += block_len;
1771
1772 /* Avoid locking up the system */
1773 cond_resched();
1774 if (signal_pending(current)) {
1775 rc = -EINTR;
1776 break;
1777 }
1778 }
1779
1780 if (retlen)
1781 *retlen = pos;
1782 return rc;
1783}
1784
1785int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1786 size_t len, size_t *retlen, const u8 *buffer)
1787{
1788 u8 verify_buffer[FALCON_SPI_MAX_LEN];
Ben Hutchings23d30f02008-12-12 21:56:11 -08001789 size_t block_len, pos = 0;
1790 unsigned int command;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001791 int rc = 0;
1792
1793 while (pos < len) {
1794 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1795 if (rc)
1796 break;
1797
Ben Hutchings23d30f02008-12-12 21:56:11 -08001798 block_len = min(len - pos,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001799 falcon_spi_write_limit(spi, start + pos));
1800 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1801 rc = falcon_spi_cmd(spi, command, start + pos,
1802 buffer + pos, NULL, block_len);
1803 if (rc)
1804 break;
1805
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001806 rc = falcon_spi_wait_write(spi);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001807 if (rc)
1808 break;
1809
1810 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1811 rc = falcon_spi_cmd(spi, command, start + pos,
1812 NULL, verify_buffer, block_len);
1813 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1814 rc = -EIO;
1815 break;
1816 }
1817
1818 pos += block_len;
1819
1820 /* Avoid locking up the system */
1821 cond_resched();
1822 if (signal_pending(current)) {
1823 rc = -EINTR;
1824 break;
1825 }
1826 }
1827
1828 if (retlen)
1829 *retlen = pos;
1830 return rc;
1831}
1832
Ben Hutchings8ceee662008-04-27 12:55:59 +01001833/**************************************************************************
1834 *
1835 * MAC wrapper
1836 *
1837 **************************************************************************
1838 */
1839void falcon_drain_tx_fifo(struct efx_nic *efx)
1840{
1841 efx_oword_t temp;
1842 int count;
1843
Ben Hutchings55668612008-05-16 21:16:10 +01001844 if ((falcon_rev(efx) < FALCON_REV_B0) ||
Ben Hutchings3273c2e2008-05-07 13:36:19 +01001845 (efx->loopback_mode != LOOPBACK_NONE))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001846 return;
1847
1848 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1849 /* There is no point in draining more than once */
1850 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1851 return;
1852
1853 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1854 * the drain sequence with the statistics fetch */
1855 spin_lock(&efx->stats_lock);
1856
1857 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1858 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1859
1860 /* Reset the MAC and EM block. */
1861 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1862 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1863 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1864 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1865 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1866
1867 count = 0;
1868 while (1) {
1869 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1870 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1871 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1872 !EFX_OWORD_FIELD(temp, RST_EM)) {
1873 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1874 count);
1875 break;
1876 }
1877 if (count > 20) {
1878 EFX_ERR(efx, "MAC reset failed\n");
1879 break;
1880 }
1881 count++;
1882 udelay(10);
1883 }
1884
1885 spin_unlock(&efx->stats_lock);
1886
1887 /* If we've reset the EM block and the link is up, then
1888 * we'll have to kick the XAUI link so the PHY can recover */
1889 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1890 falcon_reset_xaui(efx);
1891}
1892
1893void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1894{
1895 efx_oword_t temp;
1896
Ben Hutchings55668612008-05-16 21:16:10 +01001897 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001898 return;
1899
1900 /* Isolate the MAC -> RX */
1901 falcon_read(efx, &temp, RX_CFG_REG_KER);
1902 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1903 falcon_write(efx, &temp, RX_CFG_REG_KER);
1904
1905 if (!efx->link_up)
1906 falcon_drain_tx_fifo(efx);
1907}
1908
1909void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1910{
1911 efx_oword_t reg;
1912 int link_speed;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001913 bool tx_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001914
1915 if (efx->link_options & GM_LPA_10000)
1916 link_speed = 0x3;
1917 else if (efx->link_options & GM_LPA_1000)
1918 link_speed = 0x2;
1919 else if (efx->link_options & GM_LPA_100)
1920 link_speed = 0x1;
1921 else
1922 link_speed = 0x0;
1923 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1924 * as advertised. Disable to ensure packets are not
1925 * indefinitely held and TX queue can be flushed at any point
1926 * while the link is down. */
1927 EFX_POPULATE_OWORD_5(reg,
1928 MAC_XOFF_VAL, 0xffff /* max pause time */,
1929 MAC_BCAD_ACPT, 1,
1930 MAC_UC_PROM, efx->promiscuous,
1931 MAC_LINK_STATUS, 1, /* always set */
1932 MAC_SPEED, link_speed);
1933 /* On B0, MAC backpressure can be disabled and packets get
1934 * discarded. */
Ben Hutchings55668612008-05-16 21:16:10 +01001935 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001936 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1937 !efx->link_up);
1938 }
1939
1940 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1941
1942 /* Restore the multicast hash registers. */
1943 falcon_set_multicast_hash(efx);
1944
1945 /* Transmission of pause frames when RX crosses the threshold is
1946 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1947 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001948 tx_fc = !!(efx->flow_control & EFX_FC_TX);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001949 falcon_read(efx, &reg, RX_CFG_REG_KER);
1950 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1951
1952 /* Unisolate the MAC -> RX */
Ben Hutchings55668612008-05-16 21:16:10 +01001953 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001954 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1955 falcon_write(efx, &reg, RX_CFG_REG_KER);
1956}
1957
1958int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1959{
1960 efx_oword_t reg;
1961 u32 *dma_done;
1962 int i;
1963
1964 if (disable_dma_stats)
1965 return 0;
1966
1967 /* Statistics fetch will fail if the MAC is in TX drain */
Ben Hutchings55668612008-05-16 21:16:10 +01001968 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001969 efx_oword_t temp;
1970 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1971 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1972 return 0;
1973 }
1974
1975 dma_done = (efx->stats_buffer.addr + done_offset);
1976 *dma_done = FALCON_STATS_NOT_DONE;
1977 wmb(); /* ensure done flag is clear */
1978
1979 /* Initiate DMA transfer of stats */
1980 EFX_POPULATE_OWORD_2(reg,
1981 MAC_STAT_DMA_CMD, 1,
1982 MAC_STAT_DMA_ADR,
1983 efx->stats_buffer.dma_addr);
1984 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1985
1986 /* Wait for transfer to complete */
1987 for (i = 0; i < 400; i++) {
Ben Hutchings1d0680f2008-09-01 12:50:08 +01001988 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
1989 rmb(); /* Ensure the stats are valid. */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001990 return 0;
Ben Hutchings1d0680f2008-09-01 12:50:08 +01001991 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001992 udelay(10);
1993 }
1994
1995 EFX_ERR(efx, "timed out waiting for statistics\n");
1996 return -ETIMEDOUT;
1997}
1998
1999/**************************************************************************
2000 *
2001 * PHY access via GMII
2002 *
2003 **************************************************************************
2004 */
2005
2006/* Use the top bit of the MII PHY id to indicate the PHY type
2007 * (1G/10G), with the remaining bits as the actual PHY id.
2008 *
2009 * This allows us to avoid leaking information from the mii_if_info
2010 * structure into other data structures.
2011 */
2012#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
2013#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2014#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
2015#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
2016#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
2017
2018
2019/* Packing the clause 45 port and device fields into a single value */
2020#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2021#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
2022#define MD_DEV_ADR_COMP_LBN 0
2023#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
2024
2025
2026/* Wait for GMII access to complete */
2027static int falcon_gmii_wait(struct efx_nic *efx)
2028{
2029 efx_dword_t md_stat;
2030 int count;
2031
2032 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
2033 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2034 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2035 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2036 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2037 EFX_ERR(efx, "error from GMII access "
2038 EFX_DWORD_FMT"\n",
2039 EFX_DWORD_VAL(md_stat));
2040 return -EIO;
2041 }
2042 return 0;
2043 }
2044 udelay(10);
2045 }
2046 EFX_ERR(efx, "timed out waiting for GMII\n");
2047 return -ETIMEDOUT;
2048}
2049
2050/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2051static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2052 int addr, int value)
2053{
Ben Hutchings767e4682008-09-01 12:43:14 +01002054 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002055 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2056 efx_oword_t reg;
2057
2058 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2059 * chosen so that the only current user, Falcon, can take the
2060 * packed value and use them directly.
2061 * Fail to build if this assumption is broken.
2062 */
2063 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2064 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2065 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2066 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2067
2068 if (phy_id2 == PHY_ADDR_INVALID)
2069 return;
2070
2071 /* See falcon_mdio_read for an explanation. */
2072 if (!(phy_id & FALCON_PHY_ID_10G)) {
2073 int mmd = ffs(efx->phy_op->mmds) - 1;
2074 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2075 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2076 & FALCON_PHY_ID_ID_MASK;
2077 }
2078
2079 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2080 addr, value);
2081
2082 spin_lock_bh(&efx->phy_lock);
2083
2084 /* Check MII not currently being accessed */
2085 if (falcon_gmii_wait(efx) != 0)
2086 goto out;
2087
2088 /* Write the address/ID register */
2089 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2090 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2091
2092 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2093 falcon_write(efx, &reg, MD_ID_REG_KER);
2094
2095 /* Write data */
2096 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2097 falcon_write(efx, &reg, MD_TXD_REG_KER);
2098
2099 EFX_POPULATE_OWORD_2(reg,
2100 MD_WRC, 1,
2101 MD_GC, 0);
2102 falcon_write(efx, &reg, MD_CS_REG_KER);
2103
2104 /* Wait for data to be written */
2105 if (falcon_gmii_wait(efx) != 0) {
2106 /* Abort the write operation */
2107 EFX_POPULATE_OWORD_2(reg,
2108 MD_WRC, 0,
2109 MD_GC, 1);
2110 falcon_write(efx, &reg, MD_CS_REG_KER);
2111 udelay(10);
2112 }
2113
2114 out:
2115 spin_unlock_bh(&efx->phy_lock);
2116}
2117
2118/* Reads a GMII register from a PHY connected to Falcon. If no value
2119 * could be read, -1 will be returned. */
2120static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2121{
Ben Hutchings767e4682008-09-01 12:43:14 +01002122 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002123 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2124 efx_oword_t reg;
2125 int value = -1;
2126
2127 if (phy_addr == PHY_ADDR_INVALID)
2128 return -1;
2129
2130 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2131 * but the generic Linux code does not make any distinction or have
2132 * any state for this.
2133 * We spot the case where someone tried to talk 22 to a 45 PHY and
2134 * redirect the request to the lowest numbered MMD as a clause45
2135 * request. This is enough to allow simple queries like id and link
2136 * state to succeed. TODO: We may need to do more in future.
2137 */
2138 if (!(phy_id & FALCON_PHY_ID_10G)) {
2139 int mmd = ffs(efx->phy_op->mmds) - 1;
2140 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2141 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2142 & FALCON_PHY_ID_ID_MASK;
2143 }
2144
2145 spin_lock_bh(&efx->phy_lock);
2146
2147 /* Check MII not currently being accessed */
2148 if (falcon_gmii_wait(efx) != 0)
2149 goto out;
2150
2151 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2152 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2153
2154 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2155 falcon_write(efx, &reg, MD_ID_REG_KER);
2156
2157 /* Request data to be read */
2158 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2159 falcon_write(efx, &reg, MD_CS_REG_KER);
2160
2161 /* Wait for data to become available */
2162 value = falcon_gmii_wait(efx);
2163 if (value == 0) {
2164 falcon_read(efx, &reg, MD_RXD_REG_KER);
2165 value = EFX_OWORD_FIELD(reg, MD_RXD);
2166 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2167 phy_id, addr, value);
2168 } else {
2169 /* Abort the read operation */
2170 EFX_POPULATE_OWORD_2(reg,
2171 MD_RIC, 0,
2172 MD_GC, 1);
2173 falcon_write(efx, &reg, MD_CS_REG_KER);
2174
2175 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2176 "error %d\n", phy_id, addr, value);
2177 }
2178
2179 out:
2180 spin_unlock_bh(&efx->phy_lock);
2181
2182 return value;
2183}
2184
2185static void falcon_init_mdio(struct mii_if_info *gmii)
2186{
2187 gmii->mdio_read = falcon_mdio_read;
2188 gmii->mdio_write = falcon_mdio_write;
2189 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2190 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2191}
2192
2193static int falcon_probe_phy(struct efx_nic *efx)
2194{
2195 switch (efx->phy_type) {
2196 case PHY_TYPE_10XPRESS:
2197 efx->phy_op = &falcon_tenxpress_phy_ops;
2198 break;
2199 case PHY_TYPE_XFP:
2200 efx->phy_op = &falcon_xfp_phy_ops;
2201 break;
2202 default:
2203 EFX_ERR(efx, "Unknown PHY type %d\n",
2204 efx->phy_type);
2205 return -1;
2206 }
Ben Hutchings3273c2e2008-05-07 13:36:19 +01002207
2208 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002209 return 0;
2210}
2211
2212/* This call is responsible for hooking in the MAC and PHY operations */
2213int falcon_probe_port(struct efx_nic *efx)
2214{
2215 int rc;
2216
2217 /* Hook in PHY operations table */
2218 rc = falcon_probe_phy(efx);
2219 if (rc)
2220 return rc;
2221
2222 /* Set up GMII structure for PHY */
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01002223 efx->mii.supports_gmii = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002224 falcon_init_mdio(&efx->mii);
2225
2226 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
Ben Hutchings55668612008-05-16 21:16:10 +01002227 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002228 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2229 else
2230 efx->flow_control = EFX_FC_RX;
2231
2232 /* Allocate buffer for stats */
2233 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2234 FALCON_MAC_STATS_SIZE);
2235 if (rc)
2236 return rc;
2237 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2238 (unsigned long long)efx->stats_buffer.dma_addr,
2239 efx->stats_buffer.addr,
2240 virt_to_phys(efx->stats_buffer.addr));
2241
2242 return 0;
2243}
2244
2245void falcon_remove_port(struct efx_nic *efx)
2246{
2247 falcon_free_buffer(efx, &efx->stats_buffer);
2248}
2249
2250/**************************************************************************
2251 *
2252 * Multicast filtering
2253 *
2254 **************************************************************************
2255 */
2256
2257void falcon_set_multicast_hash(struct efx_nic *efx)
2258{
2259 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2260
2261 /* Broadcast packets go through the multicast hash filter.
2262 * ether_crc_le() of the broadcast address is 0xbe2612ff
2263 * so we always add bit 0xff to the mask.
2264 */
2265 set_bit_le(0xff, mc_hash->byte);
2266
2267 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2268 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2269}
2270
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002271
2272/**************************************************************************
2273 *
2274 * Falcon test code
2275 *
2276 **************************************************************************/
2277
2278int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2279{
2280 struct falcon_nvconfig *nvconfig;
2281 struct efx_spi_device *spi;
2282 void *region;
2283 int rc, magic_num, struct_ver;
2284 __le16 *word, *limit;
2285 u32 csum;
2286
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002287 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2288 if (!spi)
2289 return -EINVAL;
2290
Ben Hutchings0a95f562008-11-04 20:33:11 +00002291 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002292 if (!region)
2293 return -ENOMEM;
2294 nvconfig = region + NVCONFIG_OFFSET;
2295
Ben Hutchingsf4150722008-11-04 20:34:28 +00002296 mutex_lock(&efx->spi_lock);
Ben Hutchings0a95f562008-11-04 20:33:11 +00002297 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
Ben Hutchingsf4150722008-11-04 20:34:28 +00002298 mutex_unlock(&efx->spi_lock);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002299 if (rc) {
2300 EFX_ERR(efx, "Failed to read %s\n",
2301 efx->spi_flash ? "flash" : "EEPROM");
2302 rc = -EIO;
2303 goto out;
2304 }
2305
2306 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2307 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2308
2309 rc = -EINVAL;
2310 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2311 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2312 goto out;
2313 }
2314 if (struct_ver < 2) {
2315 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2316 goto out;
2317 } else if (struct_ver < 4) {
2318 word = &nvconfig->board_magic_num;
2319 limit = (__le16 *) (nvconfig + 1);
2320 } else {
2321 word = region;
Ben Hutchings0a95f562008-11-04 20:33:11 +00002322 limit = region + FALCON_NVCONFIG_END;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002323 }
2324 for (csum = 0; word < limit; ++word)
2325 csum += le16_to_cpu(*word);
2326
2327 if (~csum & 0xffff) {
2328 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2329 goto out;
2330 }
2331
2332 rc = 0;
2333 if (nvconfig_out)
2334 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2335
2336 out:
2337 kfree(region);
2338 return rc;
2339}
2340
2341/* Registers tested in the falcon register test */
2342static struct {
2343 unsigned address;
2344 efx_oword_t mask;
2345} efx_test_registers[] = {
2346 { ADR_REGION_REG_KER,
2347 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2348 { RX_CFG_REG_KER,
2349 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2350 { TX_CFG_REG_KER,
2351 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2352 { TX_CFG2_REG_KER,
2353 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2354 { MAC0_CTRL_REG_KER,
2355 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2356 { SRM_TX_DC_CFG_REG_KER,
2357 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2358 { RX_DC_CFG_REG_KER,
2359 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2360 { RX_DC_PF_WM_REG_KER,
2361 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2362 { DP_CTRL_REG,
2363 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2364 { XM_GLB_CFG_REG,
2365 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2366 { XM_TX_CFG_REG,
2367 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2368 { XM_RX_CFG_REG,
2369 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2370 { XM_RX_PARAM_REG,
2371 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2372 { XM_FC_REG,
2373 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2374 { XM_ADR_LO_REG,
2375 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2376 { XX_SD_CTL_REG,
2377 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2378};
2379
2380static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2381 const efx_oword_t *mask)
2382{
2383 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2384 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2385}
2386
2387int falcon_test_registers(struct efx_nic *efx)
2388{
2389 unsigned address = 0, i, j;
2390 efx_oword_t mask, imask, original, reg, buf;
2391
2392 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2393 WARN_ON(!LOOPBACK_INTERNAL(efx));
2394
2395 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2396 address = efx_test_registers[i].address;
2397 mask = imask = efx_test_registers[i].mask;
2398 EFX_INVERT_OWORD(imask);
2399
2400 falcon_read(efx, &original, address);
2401
2402 /* bit sweep on and off */
2403 for (j = 0; j < 128; j++) {
2404 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2405 continue;
2406
2407 /* Test this testable bit can be set in isolation */
2408 EFX_AND_OWORD(reg, original, mask);
2409 EFX_SET_OWORD32(reg, j, j, 1);
2410
2411 falcon_write(efx, &reg, address);
2412 falcon_read(efx, &buf, address);
2413
2414 if (efx_masked_compare_oword(&reg, &buf, &mask))
2415 goto fail;
2416
2417 /* Test this testable bit can be cleared in isolation */
2418 EFX_OR_OWORD(reg, original, mask);
2419 EFX_SET_OWORD32(reg, j, j, 0);
2420
2421 falcon_write(efx, &reg, address);
2422 falcon_read(efx, &buf, address);
2423
2424 if (efx_masked_compare_oword(&reg, &buf, &mask))
2425 goto fail;
2426 }
2427
2428 falcon_write(efx, &original, address);
2429 }
2430
2431 return 0;
2432
2433fail:
2434 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2435 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2436 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2437 return -EIO;
2438}
2439
Ben Hutchings8ceee662008-04-27 12:55:59 +01002440/**************************************************************************
2441 *
2442 * Device reset
2443 *
2444 **************************************************************************
2445 */
2446
2447/* Resets NIC to known state. This routine must be called in process
2448 * context and is allowed to sleep. */
2449int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2450{
2451 struct falcon_nic_data *nic_data = efx->nic_data;
2452 efx_oword_t glb_ctl_reg_ker;
2453 int rc;
2454
2455 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2456
2457 /* Initiate device reset */
2458 if (method == RESET_TYPE_WORLD) {
2459 rc = pci_save_state(efx->pci_dev);
2460 if (rc) {
2461 EFX_ERR(efx, "failed to backup PCI state of primary "
2462 "function prior to hardware reset\n");
2463 goto fail1;
2464 }
2465 if (FALCON_IS_DUAL_FUNC(efx)) {
2466 rc = pci_save_state(nic_data->pci_dev2);
2467 if (rc) {
2468 EFX_ERR(efx, "failed to backup PCI state of "
2469 "secondary function prior to "
2470 "hardware reset\n");
2471 goto fail2;
2472 }
2473 }
2474
2475 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2476 EXT_PHY_RST_DUR, 0x7,
2477 SWRST, 1);
2478 } else {
2479 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2480 EXCLUDE_FROM_RESET : 0);
2481
2482 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2483 EXT_PHY_RST_CTL, reset_phy,
2484 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2485 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2486 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2487 EE_RST_CTL, EXCLUDE_FROM_RESET,
2488 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2489 SWRST, 1);
2490 }
2491 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2492
2493 EFX_LOG(efx, "waiting for hardware reset\n");
2494 schedule_timeout_uninterruptible(HZ / 20);
2495
2496 /* Restore PCI configuration if needed */
2497 if (method == RESET_TYPE_WORLD) {
2498 if (FALCON_IS_DUAL_FUNC(efx)) {
2499 rc = pci_restore_state(nic_data->pci_dev2);
2500 if (rc) {
2501 EFX_ERR(efx, "failed to restore PCI config for "
2502 "the secondary function\n");
2503 goto fail3;
2504 }
2505 }
2506 rc = pci_restore_state(efx->pci_dev);
2507 if (rc) {
2508 EFX_ERR(efx, "failed to restore PCI config for the "
2509 "primary function\n");
2510 goto fail4;
2511 }
2512 EFX_LOG(efx, "successfully restored PCI config\n");
2513 }
2514
2515 /* Assert that reset complete */
2516 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2517 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2518 rc = -ETIMEDOUT;
2519 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2520 goto fail5;
2521 }
2522 EFX_LOG(efx, "hardware reset complete\n");
2523
2524 return 0;
2525
2526 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2527fail2:
2528fail3:
2529 pci_restore_state(efx->pci_dev);
2530fail1:
2531fail4:
2532fail5:
2533 return rc;
2534}
2535
2536/* Zeroes out the SRAM contents. This routine must be called in
2537 * process context and is allowed to sleep.
2538 */
2539static int falcon_reset_sram(struct efx_nic *efx)
2540{
2541 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2542 int count;
2543
2544 /* Set the SRAM wake/sleep GPIO appropriately. */
2545 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2546 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2547 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2548 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2549
2550 /* Initiate SRAM reset */
2551 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2552 SRAM_OOB_BT_INIT_EN, 1,
2553 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2554 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2555
2556 /* Wait for SRAM reset to complete */
2557 count = 0;
2558 do {
2559 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2560
2561 /* SRAM reset is slow; expect around 16ms */
2562 schedule_timeout_uninterruptible(HZ / 50);
2563
2564 /* Check for reset complete */
2565 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2566 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2567 EFX_LOG(efx, "SRAM reset complete\n");
2568
2569 return 0;
2570 }
2571 } while (++count < 20); /* wait upto 0.4 sec */
2572
2573 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2574 return -ETIMEDOUT;
2575}
2576
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002577static int falcon_spi_device_init(struct efx_nic *efx,
2578 struct efx_spi_device **spi_device_ret,
2579 unsigned int device_id, u32 device_type)
2580{
2581 struct efx_spi_device *spi_device;
2582
2583 if (device_type != 0) {
2584 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2585 if (!spi_device)
2586 return -ENOMEM;
2587 spi_device->device_id = device_id;
2588 spi_device->size =
2589 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2590 spi_device->addr_len =
2591 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2592 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2593 spi_device->addr_len == 1);
Ben Hutchingsf4150722008-11-04 20:34:28 +00002594 spi_device->erase_command =
2595 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2596 spi_device->erase_size =
2597 1 << SPI_DEV_TYPE_FIELD(device_type,
2598 SPI_DEV_TYPE_ERASE_SIZE);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002599 spi_device->block_size =
2600 1 << SPI_DEV_TYPE_FIELD(device_type,
2601 SPI_DEV_TYPE_BLOCK_SIZE);
2602
2603 spi_device->efx = efx;
2604 } else {
2605 spi_device = NULL;
2606 }
2607
2608 kfree(*spi_device_ret);
2609 *spi_device_ret = spi_device;
2610 return 0;
2611}
2612
2613
2614static void falcon_remove_spi_devices(struct efx_nic *efx)
2615{
2616 kfree(efx->spi_eeprom);
2617 efx->spi_eeprom = NULL;
2618 kfree(efx->spi_flash);
2619 efx->spi_flash = NULL;
2620}
2621
Ben Hutchings8ceee662008-04-27 12:55:59 +01002622/* Extract non-volatile configuration */
2623static int falcon_probe_nvconfig(struct efx_nic *efx)
2624{
2625 struct falcon_nvconfig *nvconfig;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002626 int board_rev;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002627 int rc;
2628
Ben Hutchings8ceee662008-04-27 12:55:59 +01002629 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002630 if (!nvconfig)
2631 return -ENOMEM;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002632
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002633 rc = falcon_read_nvram(efx, nvconfig);
2634 if (rc == -EINVAL) {
2635 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
Ben Hutchings8ceee662008-04-27 12:55:59 +01002636 efx->phy_type = PHY_TYPE_NONE;
2637 efx->mii.phy_id = PHY_ADDR_INVALID;
2638 board_rev = 0;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002639 rc = 0;
2640 } else if (rc) {
2641 goto fail1;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002642 } else {
2643 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002644 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002645
2646 efx->phy_type = v2->port0_phy_type;
2647 efx->mii.phy_id = v2->port0_phy_addr;
2648 board_rev = le16_to_cpu(v2->board_revision);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002649
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002650 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002651 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2652 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2653 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2654 EE_SPI_FLASH,
2655 le32_to_cpu(fl));
2656 if (rc)
2657 goto fail2;
2658 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2659 EE_SPI_EEPROM,
2660 le32_to_cpu(ee));
2661 if (rc)
2662 goto fail2;
2663 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002664 }
2665
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002666 /* Read the MAC addresses */
2667 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2668
Ben Hutchings8ceee662008-04-27 12:55:59 +01002669 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2670
2671 efx_set_board_info(efx, board_rev);
2672
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002673 kfree(nvconfig);
2674 return 0;
2675
2676 fail2:
2677 falcon_remove_spi_devices(efx);
2678 fail1:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002679 kfree(nvconfig);
2680 return rc;
2681}
2682
2683/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2684 * count, port speed). Set workaround and feature flags accordingly.
2685 */
2686static int falcon_probe_nic_variant(struct efx_nic *efx)
2687{
2688 efx_oword_t altera_build;
2689
2690 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2691 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2692 EFX_ERR(efx, "Falcon FPGA not supported\n");
2693 return -ENODEV;
2694 }
2695
Ben Hutchings55668612008-05-16 21:16:10 +01002696 switch (falcon_rev(efx)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002697 case FALCON_REV_A0:
2698 case 0xff:
2699 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2700 return -ENODEV;
2701
2702 case FALCON_REV_A1:{
2703 efx_oword_t nic_stat;
2704
2705 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2706
2707 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2708 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2709 return -ENODEV;
2710 }
2711 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2712 EFX_ERR(efx, "1G mode not supported\n");
2713 return -ENODEV;
2714 }
2715 break;
2716 }
2717
2718 case FALCON_REV_B0:
2719 break;
2720
2721 default:
Ben Hutchings55668612008-05-16 21:16:10 +01002722 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002723 return -ENODEV;
2724 }
2725
2726 return 0;
2727}
2728
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002729/* Probe all SPI devices on the NIC */
2730static void falcon_probe_spi_devices(struct efx_nic *efx)
2731{
2732 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002733 int boot_dev;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002734
2735 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2736 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2737 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2738
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002739 if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2740 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2741 EE_SPI_FLASH : EE_SPI_EEPROM);
2742 EFX_LOG(efx, "Booted from %s\n",
2743 boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2744 } else {
2745 /* Disable VPD and set clock dividers to safe
2746 * values for initial programming. */
2747 boot_dev = -1;
2748 EFX_LOG(efx, "Booted from internal ASIC settings;"
2749 " setting SPI config\n");
2750 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2751 /* 125 MHz / 7 ~= 20 MHz */
2752 EE_SF_CLOCK_DIV, 7,
2753 /* 125 MHz / 63 ~= 2 MHz */
2754 EE_EE_CLOCK_DIV, 63);
2755 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002756 }
2757
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002758 if (boot_dev == EE_SPI_FLASH)
2759 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2760 default_flash_type);
2761 if (boot_dev == EE_SPI_EEPROM)
2762 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2763 large_eeprom_type);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002764}
2765
Ben Hutchings8ceee662008-04-27 12:55:59 +01002766int falcon_probe_nic(struct efx_nic *efx)
2767{
2768 struct falcon_nic_data *nic_data;
2769 int rc;
2770
Ben Hutchings8ceee662008-04-27 12:55:59 +01002771 /* Allocate storage for hardware specific data */
2772 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
Ben Hutchings88c59422008-09-03 15:07:50 +01002773 if (!nic_data)
2774 return -ENOMEM;
Ben Hutchings5daab962008-05-16 21:19:43 +01002775 efx->nic_data = nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002776
2777 /* Determine number of ports etc. */
2778 rc = falcon_probe_nic_variant(efx);
2779 if (rc)
2780 goto fail1;
2781
2782 /* Probe secondary function if expected */
2783 if (FALCON_IS_DUAL_FUNC(efx)) {
2784 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2785
2786 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2787 dev))) {
2788 if (dev->bus == efx->pci_dev->bus &&
2789 dev->devfn == efx->pci_dev->devfn + 1) {
2790 nic_data->pci_dev2 = dev;
2791 break;
2792 }
2793 }
2794 if (!nic_data->pci_dev2) {
2795 EFX_ERR(efx, "failed to find secondary function\n");
2796 rc = -ENODEV;
2797 goto fail2;
2798 }
2799 }
2800
2801 /* Now we can reset the NIC */
2802 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2803 if (rc) {
2804 EFX_ERR(efx, "failed to reset NIC\n");
2805 goto fail3;
2806 }
2807
2808 /* Allocate memory for INT_KER */
2809 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2810 if (rc)
2811 goto fail4;
2812 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2813
2814 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2815 (unsigned long long)efx->irq_status.dma_addr,
2816 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2817
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002818 falcon_probe_spi_devices(efx);
2819
Ben Hutchings8ceee662008-04-27 12:55:59 +01002820 /* Read in the non-volatile configuration */
2821 rc = falcon_probe_nvconfig(efx);
2822 if (rc)
2823 goto fail5;
2824
Ben Hutchings37b5a602008-05-30 22:27:04 +01002825 /* Initialise I2C adapter */
2826 efx->i2c_adap.owner = THIS_MODULE;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002827 nic_data->i2c_data = falcon_i2c_bit_operations;
2828 nic_data->i2c_data.data = efx;
2829 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2830 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
Ben Hutchings9dadae62008-07-18 18:59:12 +01002831 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
Ben Hutchings37b5a602008-05-30 22:27:04 +01002832 rc = i2c_bit_add_bus(&efx->i2c_adap);
2833 if (rc)
2834 goto fail5;
2835
Ben Hutchings8ceee662008-04-27 12:55:59 +01002836 return 0;
2837
2838 fail5:
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002839 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002840 falcon_free_buffer(efx, &efx->irq_status);
2841 fail4:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002842 fail3:
2843 if (nic_data->pci_dev2) {
2844 pci_dev_put(nic_data->pci_dev2);
2845 nic_data->pci_dev2 = NULL;
2846 }
2847 fail2:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002848 fail1:
2849 kfree(efx->nic_data);
2850 return rc;
2851}
2852
2853/* This call performs hardware-specific global initialisation, such as
2854 * defining the descriptor cache sizes and number of RSS channels.
2855 * It does not set up any buffers, descriptor rings or event queues.
2856 */
2857int falcon_init_nic(struct efx_nic *efx)
2858{
Ben Hutchings8ceee662008-04-27 12:55:59 +01002859 efx_oword_t temp;
2860 unsigned thresh;
2861 int rc;
2862
Ben Hutchings8ceee662008-04-27 12:55:59 +01002863 /* Use on-chip SRAM */
2864 falcon_read(efx, &temp, NIC_STAT_REG);
2865 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2866 falcon_write(efx, &temp, NIC_STAT_REG);
2867
2868 /* Set buffer table mode */
2869 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2870 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2871
2872 rc = falcon_reset_sram(efx);
2873 if (rc)
2874 return rc;
2875
2876 /* Set positions of descriptor caches in SRAM. */
2877 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2878 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2879 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2880 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2881
2882 /* Set TX descriptor cache size. */
2883 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2884 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2885 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2886
2887 /* Set RX descriptor cache size. Set low watermark to size-8, as
2888 * this allows most efficient prefetching.
2889 */
2890 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2891 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2892 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2893 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2894 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2895
2896 /* Clear the parity enables on the TX data fifos as
2897 * they produce false parity errors because of timing issues
2898 */
2899 if (EFX_WORKAROUND_5129(efx)) {
2900 falcon_read(efx, &temp, SPARE_REG_KER);
2901 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2902 falcon_write(efx, &temp, SPARE_REG_KER);
2903 }
2904
2905 /* Enable all the genuinely fatal interrupts. (They are still
2906 * masked by the overall interrupt mask, controlled by
2907 * falcon_interrupts()).
2908 *
2909 * Note: All other fatal interrupts are enabled
2910 */
2911 EFX_POPULATE_OWORD_3(temp,
2912 ILL_ADR_INT_KER_EN, 1,
2913 RBUF_OWN_INT_KER_EN, 1,
2914 TBUF_OWN_INT_KER_EN, 1);
2915 EFX_INVERT_OWORD(temp);
2916 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2917
Ben Hutchings8ceee662008-04-27 12:55:59 +01002918 if (EFX_WORKAROUND_7244(efx)) {
Ben Hutchings955f0a72008-09-01 12:47:52 +01002919 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002920 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2921 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2922 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2923 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
Ben Hutchings955f0a72008-09-01 12:47:52 +01002924 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002925 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002926
2927 falcon_setup_rss_indir_table(efx);
2928
2929 /* Setup RX. Wait for descriptor is broken and must
2930 * be disabled. RXDP recovery shouldn't be needed, but is.
2931 */
2932 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2933 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2934 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2935 if (EFX_WORKAROUND_5583(efx))
2936 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2937 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2938
2939 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2940 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2941 */
2942 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2943 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2944 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2945 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2946 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2947 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2948 /* Enable SW_EV to inherit in char driver - assume harmless here */
2949 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2950 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2951 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2952 /* Squash TX of packets of 16 bytes or less */
Ben Hutchings55668612008-05-16 21:16:10 +01002953 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01002954 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2955 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2956
2957 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2958 * descriptors (which is bad).
2959 */
2960 falcon_read(efx, &temp, TX_CFG_REG_KER);
2961 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2962 falcon_write(efx, &temp, TX_CFG_REG_KER);
2963
2964 /* RX config */
2965 falcon_read(efx, &temp, RX_CFG_REG_KER);
2966 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2967 if (EFX_WORKAROUND_7575(efx))
2968 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2969 (3 * 4096) / 32);
Ben Hutchings55668612008-05-16 21:16:10 +01002970 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002971 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2972
2973 /* RX FIFO flow control thresholds */
2974 thresh = ((rx_xon_thresh_bytes >= 0) ?
2975 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2976 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2977 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2978 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2979 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2980 /* RX control FIFO thresholds [32 entries] */
Ben Hutchingsc84a6f12008-09-01 12:46:21 +01002981 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2982 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002983 falcon_write(efx, &temp, RX_CFG_REG_KER);
2984
2985 /* Set destination of both TX and RX Flush events */
Ben Hutchings55668612008-05-16 21:16:10 +01002986 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002987 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2988 falcon_write(efx, &temp, DP_CTRL_REG);
2989 }
2990
2991 return 0;
2992}
2993
2994void falcon_remove_nic(struct efx_nic *efx)
2995{
2996 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002997 int rc;
2998
2999 rc = i2c_del_adapter(&efx->i2c_adap);
3000 BUG_ON(rc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003001
Ben Hutchings4a5b5042008-09-01 12:47:16 +01003002 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003003 falcon_free_buffer(efx, &efx->irq_status);
3004
Ben Hutchings91ad7572008-05-16 21:14:27 +01003005 falcon_reset_hw(efx, RESET_TYPE_ALL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003006
3007 /* Release the second function after the reset */
3008 if (nic_data->pci_dev2) {
3009 pci_dev_put(nic_data->pci_dev2);
3010 nic_data->pci_dev2 = NULL;
3011 }
3012
3013 /* Tear down the private nic state */
3014 kfree(efx->nic_data);
3015 efx->nic_data = NULL;
3016}
3017
3018void falcon_update_nic_stats(struct efx_nic *efx)
3019{
3020 efx_oword_t cnt;
3021
3022 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3023 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3024}
3025
3026/**************************************************************************
3027 *
3028 * Revision-dependent attributes used by efx.c
3029 *
3030 **************************************************************************
3031 */
3032
3033struct efx_nic_type falcon_a_nic_type = {
3034 .mem_bar = 2,
3035 .mem_map_size = 0x20000,
3036 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3037 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3038 .buf_tbl_base = BUF_TBL_KER_A1,
3039 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3040 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3041 .txd_ring_mask = FALCON_TXD_RING_MASK,
3042 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3043 .evq_size = FALCON_EVQ_SIZE,
3044 .max_dma_mask = FALCON_DMA_MASK,
3045 .tx_dma_mask = FALCON_TX_DMA_MASK,
3046 .bug5391_mask = 0xf,
3047 .rx_xoff_thresh = 2048,
3048 .rx_xon_thresh = 512,
3049 .rx_buffer_padding = 0x24,
3050 .max_interrupt_mode = EFX_INT_MODE_MSI,
3051 .phys_addr_channels = 4,
3052};
3053
3054struct efx_nic_type falcon_b_nic_type = {
3055 .mem_bar = 2,
3056 /* Map everything up to and including the RSS indirection
3057 * table. Don't map MSI-X table, MSI-X PBA since Linux
3058 * requires that they not be mapped. */
3059 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3060 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3061 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3062 .buf_tbl_base = BUF_TBL_KER_B0,
3063 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3064 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3065 .txd_ring_mask = FALCON_TXD_RING_MASK,
3066 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3067 .evq_size = FALCON_EVQ_SIZE,
3068 .max_dma_mask = FALCON_DMA_MASK,
3069 .tx_dma_mask = FALCON_TX_DMA_MASK,
3070 .bug5391_mask = 0,
3071 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3072 .rx_xon_thresh = 27648, /* ~3*max MTU */
3073 .rx_buffer_padding = 0,
3074 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3075 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3076 * interrupt handler only supports 32
3077 * channels */
3078};
3079