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Pierre Ossmand129bce2006-03-24 03:18:17 -08001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
Pierre Ossmand129bce2006-03-24 03:18:17 -08003 *
Giuseppe Cavallaro1978fda2010-09-28 10:41:29 +02004 * Header file for Host Controller registers and I/O accessors.
5 *
Pierre Ossmanb69c9052008-03-08 23:44:25 +01006 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
Pierre Ossmand129bce2006-03-24 03:18:17 -08007 *
8 * This program is free software; you can redistribute it and/or modify
Pierre Ossman643f7202006-09-30 23:27:52 -07009 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
Pierre Ossmand129bce2006-03-24 03:18:17 -080012 */
Giuseppe Cavallaro1978fda2010-09-28 10:41:29 +020013#ifndef __SDHCI_HW_H
14#define __SDHCI_HW_H
Pierre Ossmand129bce2006-03-24 03:18:17 -080015
Andrew Morton0c7ad102008-07-25 19:44:35 -070016#include <linux/scatterlist.h>
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030017#include <linux/compiler.h>
18#include <linux/types.h>
19#include <linux/io.h>
Andrew Morton0c7ad102008-07-25 19:44:35 -070020
Giuseppe Cavallaro1978fda2010-09-28 10:41:29 +020021#include <linux/mmc/sdhci.h>
22
Pierre Ossmand129bce2006-03-24 03:18:17 -080023/*
Pierre Ossmand129bce2006-03-24 03:18:17 -080024 * Controller registers
25 */
26
27#define SDHCI_DMA_ADDRESS 0x00
28
29#define SDHCI_BLOCK_SIZE 0x04
Pierre Ossmanbab76962006-07-02 16:51:35 +010030#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
Pierre Ossmand129bce2006-03-24 03:18:17 -080031
32#define SDHCI_BLOCK_COUNT 0x06
33
34#define SDHCI_ARGUMENT 0x08
35
36#define SDHCI_TRANSFER_MODE 0x0C
37#define SDHCI_TRNS_DMA 0x01
38#define SDHCI_TRNS_BLK_CNT_EN 0x02
39#define SDHCI_TRNS_ACMD12 0x04
40#define SDHCI_TRNS_READ 0x10
41#define SDHCI_TRNS_MULTI 0x20
42
43#define SDHCI_COMMAND 0x0E
44#define SDHCI_CMD_RESP_MASK 0x03
45#define SDHCI_CMD_CRC 0x08
46#define SDHCI_CMD_INDEX 0x10
47#define SDHCI_CMD_DATA 0x20
Richard Zhu574e3f52011-03-21 13:22:14 +080048#define SDHCI_CMD_ABORTCMD 0xC0
Pierre Ossmand129bce2006-03-24 03:18:17 -080049
50#define SDHCI_CMD_RESP_NONE 0x00
51#define SDHCI_CMD_RESP_LONG 0x01
52#define SDHCI_CMD_RESP_SHORT 0x02
53#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
54
55#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
Aries Lee22113ef2010-12-15 08:14:24 +010056#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
Pierre Ossmand129bce2006-03-24 03:18:17 -080057
58#define SDHCI_RESPONSE 0x10
59
60#define SDHCI_BUFFER 0x20
61
62#define SDHCI_PRESENT_STATE 0x24
63#define SDHCI_CMD_INHIBIT 0x00000001
64#define SDHCI_DATA_INHIBIT 0x00000002
65#define SDHCI_DOING_WRITE 0x00000100
66#define SDHCI_DOING_READ 0x00000200
67#define SDHCI_SPACE_AVAILABLE 0x00000400
68#define SDHCI_DATA_AVAILABLE 0x00000800
69#define SDHCI_CARD_PRESENT 0x00010000
70#define SDHCI_WRITE_PROTECT 0x00080000
71
72#define SDHCI_HOST_CONTROL 0x28
73#define SDHCI_CTRL_LED 0x01
74#define SDHCI_CTRL_4BITBUS 0x02
Pierre Ossman077df882006-11-08 23:06:35 +010075#define SDHCI_CTRL_HISPD 0x04
Pierre Ossman2134a922008-06-28 18:28:51 +020076#define SDHCI_CTRL_DMA_MASK 0x18
77#define SDHCI_CTRL_SDMA 0x00
78#define SDHCI_CTRL_ADMA1 0x08
79#define SDHCI_CTRL_ADMA32 0x10
80#define SDHCI_CTRL_ADMA64 0x18
Philip Rakity15ec4462010-11-19 16:48:39 -050081#define SDHCI_CTRL_8BITBUS 0x20
Pierre Ossmand129bce2006-03-24 03:18:17 -080082
83#define SDHCI_POWER_CONTROL 0x29
Pierre Ossman146ad662006-06-30 02:22:23 -070084#define SDHCI_POWER_ON 0x01
85#define SDHCI_POWER_180 0x0A
86#define SDHCI_POWER_300 0x0C
87#define SDHCI_POWER_330 0x0E
Pierre Ossmand129bce2006-03-24 03:18:17 -080088
89#define SDHCI_BLOCK_GAP_CONTROL 0x2A
90
Nicolas Pitre2df3b712007-09-29 10:46:20 -040091#define SDHCI_WAKE_UP_CONTROL 0x2B
Daniel Drake5f619702010-11-04 22:20:39 +000092#define SDHCI_WAKE_ON_INT 0x01
93#define SDHCI_WAKE_ON_INSERT 0x02
94#define SDHCI_WAKE_ON_REMOVE 0x04
Pierre Ossmand129bce2006-03-24 03:18:17 -080095
96#define SDHCI_CLOCK_CONTROL 0x2C
97#define SDHCI_DIVIDER_SHIFT 8
Zhangfei Gao85105c52010-08-06 07:10:01 +080098#define SDHCI_DIVIDER_HI_SHIFT 6
99#define SDHCI_DIV_MASK 0xFF
100#define SDHCI_DIV_MASK_LEN 8
101#define SDHCI_DIV_HI_MASK 0x300
Pierre Ossmand129bce2006-03-24 03:18:17 -0800102#define SDHCI_CLOCK_CARD_EN 0x0004
103#define SDHCI_CLOCK_INT_STABLE 0x0002
104#define SDHCI_CLOCK_INT_EN 0x0001
105
106#define SDHCI_TIMEOUT_CONTROL 0x2E
107
108#define SDHCI_SOFTWARE_RESET 0x2F
109#define SDHCI_RESET_ALL 0x01
110#define SDHCI_RESET_CMD 0x02
111#define SDHCI_RESET_DATA 0x04
112
113#define SDHCI_INT_STATUS 0x30
114#define SDHCI_INT_ENABLE 0x34
115#define SDHCI_SIGNAL_ENABLE 0x38
116#define SDHCI_INT_RESPONSE 0x00000001
117#define SDHCI_INT_DATA_END 0x00000002
118#define SDHCI_INT_DMA_END 0x00000008
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100119#define SDHCI_INT_SPACE_AVAIL 0x00000010
120#define SDHCI_INT_DATA_AVAIL 0x00000020
Pierre Ossmand129bce2006-03-24 03:18:17 -0800121#define SDHCI_INT_CARD_INSERT 0x00000040
122#define SDHCI_INT_CARD_REMOVE 0x00000080
123#define SDHCI_INT_CARD_INT 0x00000100
Pierre Ossman964f9ce2007-07-20 18:20:36 +0200124#define SDHCI_INT_ERROR 0x00008000
Pierre Ossmand129bce2006-03-24 03:18:17 -0800125#define SDHCI_INT_TIMEOUT 0x00010000
126#define SDHCI_INT_CRC 0x00020000
127#define SDHCI_INT_END_BIT 0x00040000
128#define SDHCI_INT_INDEX 0x00080000
129#define SDHCI_INT_DATA_TIMEOUT 0x00100000
130#define SDHCI_INT_DATA_CRC 0x00200000
131#define SDHCI_INT_DATA_END_BIT 0x00400000
132#define SDHCI_INT_BUS_POWER 0x00800000
133#define SDHCI_INT_ACMD12ERR 0x01000000
Pierre Ossman2134a922008-06-28 18:28:51 +0200134#define SDHCI_INT_ADMA_ERROR 0x02000000
Pierre Ossmand129bce2006-03-24 03:18:17 -0800135
136#define SDHCI_INT_NORMAL_MASK 0x00007FFF
137#define SDHCI_INT_ERROR_MASK 0xFFFF8000
138
139#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
140 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
141#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100142 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
Pierre Ossmand129bce2006-03-24 03:18:17 -0800143 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
Zhangfei Gaoa751a7d692010-05-26 14:42:02 -0700144 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300145#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800146
147#define SDHCI_ACMD12_ERR 0x3C
148
149/* 3E-3F reserved */
150
151#define SDHCI_CAPABILITIES 0x40
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700152#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
153#define SDHCI_TIMEOUT_CLK_SHIFT 0
154#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
Pierre Ossmand129bce2006-03-24 03:18:17 -0800155#define SDHCI_CLOCK_BASE_MASK 0x00003F00
Zhangfei Gaoc4687d52010-08-20 14:02:36 -0400156#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
Pierre Ossmand129bce2006-03-24 03:18:17 -0800157#define SDHCI_CLOCK_BASE_SHIFT 8
Pierre Ossman1d676e02006-07-02 16:52:10 +0100158#define SDHCI_MAX_BLOCK_MASK 0x00030000
159#define SDHCI_MAX_BLOCK_SHIFT 16
Philip Rakity15ec4462010-11-19 16:48:39 -0500160#define SDHCI_CAN_DO_8BIT 0x00040000
Pierre Ossman2134a922008-06-28 18:28:51 +0200161#define SDHCI_CAN_DO_ADMA2 0x00080000
162#define SDHCI_CAN_DO_ADMA1 0x00100000
Pierre Ossman077df882006-11-08 23:06:35 +0100163#define SDHCI_CAN_DO_HISPD 0x00200000
Richard Röjforsa13abc72009-09-22 16:45:30 -0700164#define SDHCI_CAN_DO_SDMA 0x00400000
Pierre Ossman146ad662006-06-30 02:22:23 -0700165#define SDHCI_CAN_VDD_330 0x01000000
166#define SDHCI_CAN_VDD_300 0x02000000
167#define SDHCI_CAN_VDD_180 0x04000000
Pierre Ossman2134a922008-06-28 18:28:51 +0200168#define SDHCI_CAN_64BIT 0x10000000
Pierre Ossmand129bce2006-03-24 03:18:17 -0800169
Philip Rakitye8120ad2010-11-30 00:55:23 -0500170#define SDHCI_CAPABILITIES_1 0x44
Pierre Ossmand129bce2006-03-24 03:18:17 -0800171
172#define SDHCI_MAX_CURRENT 0x48
173
174/* 4C-4F reserved for more max current */
175
Pierre Ossman2134a922008-06-28 18:28:51 +0200176#define SDHCI_SET_ACMD12_ERROR 0x50
177#define SDHCI_SET_INT_ERROR 0x52
178
179#define SDHCI_ADMA_ERROR 0x54
180
181/* 55-57 reserved */
182
183#define SDHCI_ADMA_ADDRESS 0x58
184
185/* 60-FB reserved */
Pierre Ossmand129bce2006-03-24 03:18:17 -0800186
187#define SDHCI_SLOT_INT_STATUS 0xFC
188
189#define SDHCI_HOST_VERSION 0xFE
Pierre Ossman4a965502006-06-30 02:22:29 -0700190#define SDHCI_VENDOR_VER_MASK 0xFF00
191#define SDHCI_VENDOR_VER_SHIFT 8
192#define SDHCI_SPEC_VER_MASK 0x00FF
193#define SDHCI_SPEC_VER_SHIFT 0
Pierre Ossman2134a922008-06-28 18:28:51 +0200194#define SDHCI_SPEC_100 0
195#define SDHCI_SPEC_200 1
Zhangfei Gao85105c52010-08-06 07:10:01 +0800196#define SDHCI_SPEC_300 2
Pierre Ossmand129bce2006-03-24 03:18:17 -0800197
Zhangfei Gao03975262010-09-20 15:15:18 -0400198/*
199 * End of controller registers.
200 */
201
202#define SDHCI_MAX_DIV_SPEC_200 256
203#define SDHCI_MAX_DIV_SPEC_300 2046
204
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100205struct sdhci_ops {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300206#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
Matt Flemingdc297c92010-05-26 14:42:03 -0700207 u32 (*read_l)(struct sdhci_host *host, int reg);
208 u16 (*read_w)(struct sdhci_host *host, int reg);
209 u8 (*read_b)(struct sdhci_host *host, int reg);
210 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
211 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
212 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300213#endif
214
Anton Vorontsov81146342009-03-17 00:13:59 +0300215 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
216
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100217 int (*enable_dma)(struct sdhci_host *host);
Ben Dooks4240ff02009-03-17 00:13:57 +0300218 unsigned int (*get_max_clock)(struct sdhci_host *host);
Anton Vorontsova9e58f22009-07-29 15:04:16 -0700219 unsigned int (*get_min_clock)(struct sdhci_host *host);
Ben Dooks4240ff02009-03-17 00:13:57 +0300220 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
Philip Rakity15ec4462010-11-19 16:48:39 -0500221 int (*platform_8bit_width)(struct sdhci_host *host,
222 int width);
Philip Rakity643a81f2010-09-23 08:24:32 -0700223 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
224 u8 power_mode);
Wolfram Sang2dfb5792010-10-15 12:21:01 +0200225 unsigned int (*get_ro)(struct sdhci_host *host);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800226};
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100227
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300228#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
229
230static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
231{
Matt Flemingdc297c92010-05-26 14:42:03 -0700232 if (unlikely(host->ops->write_l))
233 host->ops->write_l(host, val, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300234 else
235 writel(val, host->ioaddr + reg);
236}
237
238static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
239{
Matt Flemingdc297c92010-05-26 14:42:03 -0700240 if (unlikely(host->ops->write_w))
241 host->ops->write_w(host, val, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300242 else
243 writew(val, host->ioaddr + reg);
244}
245
246static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
247{
Matt Flemingdc297c92010-05-26 14:42:03 -0700248 if (unlikely(host->ops->write_b))
249 host->ops->write_b(host, val, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300250 else
251 writeb(val, host->ioaddr + reg);
252}
253
254static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
255{
Matt Flemingdc297c92010-05-26 14:42:03 -0700256 if (unlikely(host->ops->read_l))
257 return host->ops->read_l(host, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300258 else
259 return readl(host->ioaddr + reg);
260}
261
262static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
263{
Matt Flemingdc297c92010-05-26 14:42:03 -0700264 if (unlikely(host->ops->read_w))
265 return host->ops->read_w(host, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300266 else
267 return readw(host->ioaddr + reg);
268}
269
270static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
271{
Matt Flemingdc297c92010-05-26 14:42:03 -0700272 if (unlikely(host->ops->read_b))
273 return host->ops->read_b(host, reg);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300274 else
275 return readb(host->ioaddr + reg);
276}
277
278#else
279
280static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
281{
282 writel(val, host->ioaddr + reg);
283}
284
285static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
286{
287 writew(val, host->ioaddr + reg);
288}
289
290static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
291{
292 writeb(val, host->ioaddr + reg);
293}
294
295static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
296{
297 return readl(host->ioaddr + reg);
298}
299
300static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
301{
302 return readw(host->ioaddr + reg);
303}
304
305static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
306{
307 return readb(host->ioaddr + reg);
308}
309
310#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100311
312extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
313 size_t priv_size);
314extern void sdhci_free_host(struct sdhci_host *host);
315
316static inline void *sdhci_priv(struct sdhci_host *host)
317{
318 return (void *)host->private;
319}
320
Marek Szyprowski17866e12010-08-10 18:01:58 -0700321extern void sdhci_card_detect(struct sdhci_host *host);
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100322extern int sdhci_add_host(struct sdhci_host *host);
Pierre Ossman1e728592008-04-16 19:13:13 +0200323extern void sdhci_remove_host(struct sdhci_host *host, int dead);
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100324
325#ifdef CONFIG_PM
326extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
327extern int sdhci_resume_host(struct sdhci_host *host);
Daniel Drake5f619702010-11-04 22:20:39 +0000328extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100329#endif
Albert Herranzc0bba0d2009-12-17 15:27:19 -0800330
Giuseppe Cavallaro1978fda2010-09-28 10:41:29 +0200331#endif /* __SDHCI_HW_H */