blob: 2dfe7fdb77e7fe95d6b22d1cc925fe24a06c685b [file] [log] [blame]
Shaohua Li7d715a62008-02-25 09:46:41 +08001/*
2 * File: drivers/pci/pcie/aspm.c
Stefan Assmann45e829e2009-12-03 06:49:24 -05003 * Enabling PCIe link L0s/L1 state and Clock Power Management
Shaohua Li7d715a62008-02-25 09:46:41 +08004 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
Thomas Renninger2a42d9d2008-12-09 13:05:09 +010019#include <linux/jiffies.h>
Andrew Patterson987a4c72009-01-05 16:21:04 -070020#include <linux/delay.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080021#include <linux/pci-aspm.h>
22#include "../pci.h"
23
24#ifdef MODULE_PARAM_PREFIX
25#undef MODULE_PARAM_PREFIX
26#endif
27#define MODULE_PARAM_PREFIX "pcie_aspm."
28
Kenji Kaneshigeac180182009-08-19 11:02:13 +090029/* Note: those are not register definitions */
30#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32#define ASPM_STATE_L1 (4) /* L1 state */
33#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
35
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090036struct aspm_latency {
37 u32 l0s; /* L0s latency (nsec) */
38 u32 l1; /* L1 latency (nsec) */
Shaohua Li7d715a62008-02-25 09:46:41 +080039};
40
41struct pcie_link_state {
Kenji Kaneshige5cde89d2009-05-13 12:17:04 +090042 struct pci_dev *pdev; /* Upstream component of the Link */
Kenji Kaneshige5c92ffb2009-05-13 12:23:57 +090043 struct pcie_link_state *root; /* pointer to the root port link */
Kenji Kaneshige5cde89d2009-05-13 12:17:04 +090044 struct pcie_link_state *parent; /* pointer to the parent Link state */
45 struct list_head sibling; /* node in link_list */
46 struct list_head children; /* list of child link states */
47 struct list_head link; /* node in parent's children list */
Shaohua Li7d715a62008-02-25 09:46:41 +080048
49 /* ASPM state */
Kenji Kaneshigeac180182009-08-19 11:02:13 +090050 u32 aspm_support:3; /* Supported ASPM state */
51 u32 aspm_enabled:3; /* Enabled ASPM state */
52 u32 aspm_capable:3; /* Capable ASPM state with latency */
53 u32 aspm_default:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable:3; /* Disabled ASPM state */
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +090055
Kenji Kaneshige4d246e42009-05-13 12:15:38 +090056 /* Clock PM state */
57 u32 clkpm_capable:1; /* Clock PM capable? */
58 u32 clkpm_enabled:1; /* Current Clock PM state */
59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
60
Kenji Kaneshigeac180182009-08-19 11:02:13 +090061 /* Exit latencies */
62 struct aspm_latency latency_up; /* Upstream direction exit latency */
63 struct aspm_latency latency_dw; /* Downstream direction exit latency */
Shaohua Li7d715a62008-02-25 09:46:41 +080064 /*
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090065 * Endpoint acceptable latencies. A pcie downstream port only
66 * has one slot under it, so at most there are 8 functions.
Shaohua Li7d715a62008-02-25 09:46:41 +080067 */
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090068 struct aspm_latency acceptable[8];
Shaohua Li7d715a62008-02-25 09:46:41 +080069};
70
Matthew Garrett3c076352011-11-10 16:38:33 -050071static int aspm_disabled, aspm_force;
Rafael J. Wysocki8b8bae92011-03-05 13:21:51 +010072static bool aspm_support_enabled = true;
Shaohua Li7d715a62008-02-25 09:46:41 +080073static DEFINE_MUTEX(aspm_lock);
74static LIST_HEAD(link_list);
75
76#define POLICY_DEFAULT 0 /* BIOS default setting */
77#define POLICY_PERFORMANCE 1 /* high performance */
78#define POLICY_POWERSAVE 2 /* high power saving */
Matthew Garrettad71c962012-02-03 10:18:13 -050079
80#ifdef CONFIG_PCIEASPM_PERFORMANCE
81static int aspm_policy = POLICY_PERFORMANCE;
82#elif defined CONFIG_PCIEASPM_POWERSAVE
83static int aspm_policy = POLICY_POWERSAVE;
84#else
Shaohua Li7d715a62008-02-25 09:46:41 +080085static int aspm_policy;
Matthew Garrettad71c962012-02-03 10:18:13 -050086#endif
87
Shaohua Li7d715a62008-02-25 09:46:41 +080088static const char *policy_str[] = {
89 [POLICY_DEFAULT] = "default",
90 [POLICY_PERFORMANCE] = "performance",
91 [POLICY_POWERSAVE] = "powersave"
92};
93
Andrew Patterson987a4c72009-01-05 16:21:04 -070094#define LINK_RETRAIN_TIMEOUT HZ
95
Kenji Kaneshige5aa63582009-05-13 12:17:44 +090096static int policy_to_aspm_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +080097{
Shaohua Li7d715a62008-02-25 09:46:41 +080098 switch (aspm_policy) {
99 case POLICY_PERFORMANCE:
100 /* Disable ASPM and Clock PM */
101 return 0;
102 case POLICY_POWERSAVE:
103 /* Enable ASPM L0s/L1 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900104 return ASPM_STATE_ALL;
Shaohua Li7d715a62008-02-25 09:46:41 +0800105 case POLICY_DEFAULT:
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900106 return link->aspm_default;
Shaohua Li7d715a62008-02-25 09:46:41 +0800107 }
108 return 0;
109}
110
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900111static int policy_to_clkpm_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800112{
Shaohua Li7d715a62008-02-25 09:46:41 +0800113 switch (aspm_policy) {
114 case POLICY_PERFORMANCE:
115 /* Disable ASPM and Clock PM */
116 return 0;
117 case POLICY_POWERSAVE:
118 /* Disable Clock PM */
119 return 1;
120 case POLICY_DEFAULT:
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900121 return link->clkpm_default;
Shaohua Li7d715a62008-02-25 09:46:41 +0800122 }
123 return 0;
124}
125
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900126static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800127{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900128 struct pci_dev *child;
129 struct pci_bus *linkbus = link->pdev->subordinate;
Bjorn Helgaas0c0cbb62015-06-10 14:00:21 -0500130 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
Shaohua Li7d715a62008-02-25 09:46:41 +0800131
Bjorn Helgaas0c0cbb62015-06-10 14:00:21 -0500132 list_for_each_entry(child, &linkbus->devices, bus_list)
133 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
134 PCI_EXP_LNKCTL_CLKREQ_EN,
135 val);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900136 link->clkpm_enabled = !!enable;
Shaohua Li7d715a62008-02-25 09:46:41 +0800137}
138
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900139static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
140{
141 /* Don't enable Clock PM if the link is not Clock PM capable */
142 if (!link->clkpm_capable && enable)
Matthew Garrett2f671e22010-12-06 14:00:56 -0500143 enable = 0;
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900144 /* Need nothing if the specified equals to current state */
145 if (link->clkpm_enabled == enable)
146 return;
147 pcie_set_clkpm_nocheck(link, enable);
148}
149
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900150static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
Shaohua Li7d715a62008-02-25 09:46:41 +0800151{
Jiang Liuf12eb722012-07-24 17:20:12 +0800152 int capable = 1, enabled = 1;
Shaohua Li7d715a62008-02-25 09:46:41 +0800153 u32 reg32;
154 u16 reg16;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900155 struct pci_dev *child;
156 struct pci_bus *linkbus = link->pdev->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800157
158 /* All functions should have the same cap and state, take the worst */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900159 list_for_each_entry(child, &linkbus->devices, bus_list) {
Jiang Liuf12eb722012-07-24 17:20:12 +0800160 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
Shaohua Li7d715a62008-02-25 09:46:41 +0800161 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
162 capable = 0;
163 enabled = 0;
164 break;
165 }
Jiang Liuf12eb722012-07-24 17:20:12 +0800166 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800167 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
168 enabled = 0;
169 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900170 link->clkpm_enabled = enabled;
171 link->clkpm_default = enabled;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900172 link->clkpm_capable = (blacklist) ? 0 : capable;
Shaohua Li46bbdfa2008-12-19 09:27:42 +0800173}
174
Shaohua Li7d715a62008-02-25 09:46:41 +0800175/*
176 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
177 * could use common clock. If they are, configure them to use the
178 * common clock. That will reduce the ASPM state exit latency.
179 */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900180static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800181{
Jiang Liuf12eb722012-07-24 17:20:12 +0800182 int same_clock = 1;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900183 u16 reg16, parent_reg, child_reg[8];
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100184 unsigned long start_jiffies;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900185 struct pci_dev *child, *parent = link->pdev;
186 struct pci_bus *linkbus = parent->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800187 /*
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900188 * All functions of a slot should have the same Slot Clock
Shaohua Li7d715a62008-02-25 09:46:41 +0800189 * Configuration, so just check one function
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900190 */
191 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900192 BUG_ON(!pci_is_pcie(child));
Shaohua Li7d715a62008-02-25 09:46:41 +0800193
194 /* Check downstream component if bit Slot Clock Configuration is 1 */
Jiang Liuf12eb722012-07-24 17:20:12 +0800195 pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800196 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
197 same_clock = 0;
198
199 /* Check upstream component if bit Slot Clock Configuration is 1 */
Jiang Liuf12eb722012-07-24 17:20:12 +0800200 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800201 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
202 same_clock = 0;
203
204 /* Configure downstream component, all functions */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900205 list_for_each_entry(child, &linkbus->devices, bus_list) {
Jiang Liuf12eb722012-07-24 17:20:12 +0800206 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900207 child_reg[PCI_FUNC(child->devfn)] = reg16;
Shaohua Li7d715a62008-02-25 09:46:41 +0800208 if (same_clock)
209 reg16 |= PCI_EXP_LNKCTL_CCC;
210 else
211 reg16 &= ~PCI_EXP_LNKCTL_CCC;
Jiang Liuf12eb722012-07-24 17:20:12 +0800212 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800213 }
214
215 /* Configure upstream component */
Jiang Liuf12eb722012-07-24 17:20:12 +0800216 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100217 parent_reg = reg16;
Shaohua Li7d715a62008-02-25 09:46:41 +0800218 if (same_clock)
219 reg16 |= PCI_EXP_LNKCTL_CCC;
220 else
221 reg16 &= ~PCI_EXP_LNKCTL_CCC;
Jiang Liuf12eb722012-07-24 17:20:12 +0800222 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800223
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900224 /* Retrain link */
Shaohua Li7d715a62008-02-25 09:46:41 +0800225 reg16 |= PCI_EXP_LNKCTL_RL;
Jiang Liuf12eb722012-07-24 17:20:12 +0800226 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800227
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900228 /* Wait for link training end. Break out after waiting for timeout */
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100229 start_jiffies = jiffies;
Andrew Patterson987a4c72009-01-05 16:21:04 -0700230 for (;;) {
Jiang Liuf12eb722012-07-24 17:20:12 +0800231 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800232 if (!(reg16 & PCI_EXP_LNKSTA_LT))
233 break;
Andrew Patterson987a4c72009-01-05 16:21:04 -0700234 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
235 break;
236 msleep(1);
Shaohua Li7d715a62008-02-25 09:46:41 +0800237 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900238 if (!(reg16 & PCI_EXP_LNKSTA_LT))
239 return;
240
241 /* Training failed. Restore common clock configurations */
Joe Perches438be3c2012-10-28 01:05:49 -0700242 dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
Jiang Liuf12eb722012-07-24 17:20:12 +0800243 list_for_each_entry(child, &linkbus->devices, bus_list)
244 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
245 child_reg[PCI_FUNC(child->devfn)]);
246 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
Shaohua Li7d715a62008-02-25 09:46:41 +0800247}
248
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900249/* Convert L0s latency encoding to ns */
250static u32 calc_l0s_latency(u32 encoding)
Shaohua Li7d715a62008-02-25 09:46:41 +0800251{
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900252 if (encoding == 0x7)
253 return (5 * 1000); /* > 4us */
254 return (64 << encoding);
Shaohua Li7d715a62008-02-25 09:46:41 +0800255}
256
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900257/* Convert L0s acceptable latency encoding to ns */
258static u32 calc_l0s_acceptable(u32 encoding)
Shaohua Li7d715a62008-02-25 09:46:41 +0800259{
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900260 if (encoding == 0x7)
261 return -1U;
262 return (64 << encoding);
263}
Shaohua Li7d715a62008-02-25 09:46:41 +0800264
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900265/* Convert L1 latency encoding to ns */
266static u32 calc_l1_latency(u32 encoding)
267{
268 if (encoding == 0x7)
269 return (65 * 1000); /* > 64us */
270 return (1000 << encoding);
271}
272
273/* Convert L1 acceptable latency encoding to ns */
274static u32 calc_l1_acceptable(u32 encoding)
275{
276 if (encoding == 0x7)
277 return -1U;
278 return (1000 << encoding);
Shaohua Li7d715a62008-02-25 09:46:41 +0800279}
280
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900281struct aspm_register_info {
282 u32 support:2;
283 u32 enabled:2;
284 u32 latency_encoding_l0s;
285 u32 latency_encoding_l1;
286};
287
288static void pcie_get_aspm_reg(struct pci_dev *pdev,
289 struct aspm_register_info *info)
Shaohua Li7d715a62008-02-25 09:46:41 +0800290{
Shaohua Li7d715a62008-02-25 09:46:41 +0800291 u16 reg16;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900292 u32 reg32;
Shaohua Li7d715a62008-02-25 09:46:41 +0800293
Jiang Liuf12eb722012-07-24 17:20:12 +0800294 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900295 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900296 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
297 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
Jiang Liuf12eb722012-07-24 17:20:12 +0800298 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900299 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
Shaohua Li7d715a62008-02-25 09:46:41 +0800300}
301
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900302static void pcie_aspm_check_latency(struct pci_dev *endpoint)
303{
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900304 u32 latency, l1_switch_latency = 0;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900305 struct aspm_latency *acceptable;
306 struct pcie_link_state *link;
307
308 /* Device not in D0 doesn't need latency check */
309 if ((endpoint->current_state != PCI_D0) &&
310 (endpoint->current_state != PCI_UNKNOWN))
311 return;
312
313 link = endpoint->bus->self->link_state;
314 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
315
316 while (link) {
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900317 /* Check upstream direction L0s latency */
318 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
319 (link->latency_up.l0s > acceptable->l0s))
320 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
321
322 /* Check downstream direction L0s latency */
323 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
324 (link->latency_dw.l0s > acceptable->l0s))
325 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900326 /*
327 * Check L1 latency.
328 * Every switch on the path to root complex need 1
329 * more microsecond for L1. Spec doesn't mention L0s.
330 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900331 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
332 if ((link->aspm_capable & ASPM_STATE_L1) &&
333 (latency + l1_switch_latency > acceptable->l1))
334 link->aspm_capable &= ~ASPM_STATE_L1;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900335 l1_switch_latency += 1000;
336
337 link = link->parent;
338 }
339}
340
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900341static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
Shaohua Li7d715a62008-02-25 09:46:41 +0800342{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900343 struct pci_dev *child, *parent = link->pdev;
344 struct pci_bus *linkbus = parent->subordinate;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900345 struct aspm_register_info upreg, dwreg;
Shaohua Li7d715a62008-02-25 09:46:41 +0800346
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900347 if (blacklist) {
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900348 /* Set enabled/disable so that we will disable ASPM later */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900349 link->aspm_enabled = ASPM_STATE_ALL;
350 link->aspm_disable = ASPM_STATE_ALL;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900351 return;
352 }
353
354 /* Configure common clock before checking latencies */
355 pcie_aspm_configure_common_clock(link);
356
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900357 /* Get upstream/downstream components' register state */
358 pcie_get_aspm_reg(parent, &upreg);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900359 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900360 pcie_get_aspm_reg(child, &dwreg);
361
362 /*
363 * Setup L0s state
364 *
365 * Note that we must not enable L0s in either direction on a
366 * given link unless components on both sides of the link each
367 * support L0s.
368 */
369 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
370 link->aspm_support |= ASPM_STATE_L0S;
371 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
372 link->aspm_enabled |= ASPM_STATE_L0S_UP;
373 if (upreg.enabled & PCIE_LINK_STATE_L0S)
374 link->aspm_enabled |= ASPM_STATE_L0S_DW;
375 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
376 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
377
378 /* Setup L1 state */
379 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
380 link->aspm_support |= ASPM_STATE_L1;
381 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
382 link->aspm_enabled |= ASPM_STATE_L1;
383 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
384 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900385
Kenji Kaneshigeb127bd52009-08-19 10:57:31 +0900386 /* Save default state */
387 link->aspm_default = link->aspm_enabled;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900388
389 /* Setup initial capable state. Will be updated later */
390 link->aspm_capable = link->aspm_support;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900391 /*
392 * If the downstream component has pci bridge function, don't
393 * do ASPM for now.
394 */
395 list_for_each_entry(child, &linkbus->devices, bus_list) {
Yijing Wang62f87c02012-07-24 17:20:03 +0800396 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900397 link->aspm_disable = ASPM_STATE_ALL;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900398 break;
399 }
400 }
Kenji Kaneshigeb127bd52009-08-19 10:57:31 +0900401
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900402 /* Get and check endpoint acceptable latencies */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900403 list_for_each_entry(child, &linkbus->devices, bus_list) {
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900404 u32 reg32, encoding;
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +0900405 struct aspm_latency *acceptable =
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900406 &link->acceptable[PCI_FUNC(child->devfn)];
Shaohua Li7d715a62008-02-25 09:46:41 +0800407
Yijing Wang62f87c02012-07-24 17:20:03 +0800408 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
409 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
Shaohua Li7d715a62008-02-25 09:46:41 +0800410 continue;
411
Jiang Liuf12eb722012-07-24 17:20:12 +0800412 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900413 /* Calculate endpoint L0s acceptable latency */
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900414 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
415 acceptable->l0s = calc_l0s_acceptable(encoding);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900416 /* Calculate endpoint L1 acceptable latency */
417 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
418 acceptable->l1 = calc_l1_acceptable(encoding);
419
420 pcie_aspm_check_latency(child);
Shaohua Li7d715a62008-02-25 09:46:41 +0800421 }
422}
423
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900424static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
Shaohua Li7d715a62008-02-25 09:46:41 +0800425{
Bjorn Helgaas75083202012-12-05 13:51:19 -0700426 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
427 PCI_EXP_LNKCTL_ASPMC, val);
Shaohua Li7d715a62008-02-25 09:46:41 +0800428}
429
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900430static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800431{
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900432 u32 upstream = 0, dwstream = 0;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900433 struct pci_dev *child, *parent = link->pdev;
434 struct pci_bus *linkbus = parent->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800435
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900436 /* Nothing to do if the link is already in the requested state */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900437 state &= (link->aspm_capable & ~link->aspm_disable);
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900438 if (link->aspm_enabled == state)
439 return;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900440 /* Convert ASPM state to upstream/downstream ASPM register state */
441 if (state & ASPM_STATE_L0S_UP)
Bjorn Helgaas75083202012-12-05 13:51:19 -0700442 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900443 if (state & ASPM_STATE_L0S_DW)
Bjorn Helgaas75083202012-12-05 13:51:19 -0700444 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900445 if (state & ASPM_STATE_L1) {
Bjorn Helgaas75083202012-12-05 13:51:19 -0700446 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
447 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900448 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800449 /*
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900450 * Spec 2.0 suggests all functions should be configured the
451 * same setting for ASPM. Enabling ASPM L1 should be done in
452 * upstream component first and then downstream, and vice
453 * versa for disabling ASPM L1. Spec doesn't mention L0S.
Shaohua Li7d715a62008-02-25 09:46:41 +0800454 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900455 if (state & ASPM_STATE_L1)
456 pcie_config_aspm_dev(parent, upstream);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900457 list_for_each_entry(child, &linkbus->devices, bus_list)
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900458 pcie_config_aspm_dev(child, dwstream);
459 if (!(state & ASPM_STATE_L1))
460 pcie_config_aspm_dev(parent, upstream);
Shaohua Li7d715a62008-02-25 09:46:41 +0800461
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900462 link->aspm_enabled = state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800463}
464
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900465static void pcie_config_aspm_path(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800466{
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900467 while (link) {
468 pcie_config_aspm_link(link, policy_to_aspm_state(link));
469 link = link->parent;
Shaohua Li46bbdfa2008-12-19 09:27:42 +0800470 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800471}
472
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900473static void free_link_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800474{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900475 link->pdev->link_state = NULL;
476 kfree(link);
Shaohua Li7d715a62008-02-25 09:46:41 +0800477}
478
Shaohua Liddc97532008-05-21 16:58:40 +0800479static int pcie_aspm_sanity_check(struct pci_dev *pdev)
480{
Kenji Kaneshige36475842009-05-13 12:23:09 +0900481 struct pci_dev *child;
Shaohua Li149e1632008-07-23 10:32:31 +0800482 u32 reg32;
Matthew Garrett2f671e22010-12-06 14:00:56 -0500483
Shaohua Liddc97532008-05-21 16:58:40 +0800484 /*
Stefan Assmann45e829e2009-12-03 06:49:24 -0500485 * Some functions in a slot might not all be PCIe functions,
Kenji Kaneshige36475842009-05-13 12:23:09 +0900486 * very strange. Disable ASPM for the whole slot
Shaohua Liddc97532008-05-21 16:58:40 +0800487 */
Kenji Kaneshige36475842009-05-13 12:23:09 +0900488 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
Jiang Liuf12eb722012-07-24 17:20:12 +0800489 if (!pci_is_pcie(child))
Shaohua Liddc97532008-05-21 16:58:40 +0800490 return -EINVAL;
Matthew Garrettc9651e72012-03-27 10:17:41 -0400491
492 /*
493 * If ASPM is disabled then we're not going to change
494 * the BIOS state. It's safe to continue even if it's a
495 * pre-1.1 device
496 */
497
498 if (aspm_disabled)
499 continue;
500
Shaohua Li149e1632008-07-23 10:32:31 +0800501 /*
502 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
503 * RBER bit to determine if a function is 1.1 version device
504 */
Jiang Liuf12eb722012-07-24 17:20:12 +0800505 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
Sitsofe Wheelere1f4f592008-09-16 14:27:13 +0100506 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
Joe Perches438be3c2012-10-28 01:05:49 -0700507 dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
Shaohua Li149e1632008-07-23 10:32:31 +0800508 return -EINVAL;
509 }
Shaohua Liddc97532008-05-21 16:58:40 +0800510 }
511 return 0;
512}
513
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900514static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900515{
516 struct pcie_link_state *link;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900517
518 link = kzalloc(sizeof(*link), GFP_KERNEL);
519 if (!link)
520 return NULL;
521 INIT_LIST_HEAD(&link->sibling);
522 INIT_LIST_HEAD(&link->children);
523 INIT_LIST_HEAD(&link->link);
524 link->pdev = pdev;
Yijing Wangc8fc9332015-05-21 15:05:03 +0800525 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) {
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900526 struct pcie_link_state *parent;
527 parent = pdev->bus->parent->self->link_state;
528 if (!parent) {
529 kfree(link);
530 return NULL;
531 }
532 link->parent = parent;
533 list_add(&link->link, &parent->children);
534 }
Kenji Kaneshige5c92ffb2009-05-13 12:23:57 +0900535 /* Setup a pointer to the root port link */
536 if (!link->parent)
537 link->root = link;
538 else
539 link->root = link->parent->root;
540
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900541 list_add(&link->sibling, &link_list);
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900542 pdev->link_state = link;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900543 return link;
544}
545
Shaohua Li7d715a62008-02-25 09:46:41 +0800546/*
547 * pcie_aspm_init_link_state: Initiate PCI express link state.
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700548 * It is called after the pcie and its children devices are scanned.
Shaohua Li7d715a62008-02-25 09:46:41 +0800549 * @pdev: the root port or switch downstream port
550 */
551void pcie_aspm_init_link_state(struct pci_dev *pdev)
552{
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900553 struct pcie_link_state *link;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900554 int blacklist = !!pcie_aspm_sanity_check(pdev);
Shaohua Li7d715a62008-02-25 09:46:41 +0800555
Joe Lawrencea26d5ec2013-01-15 15:31:28 -0500556 if (!aspm_support_enabled)
557 return;
558
Yijing Wangc8fc9332015-05-21 15:05:03 +0800559 if (pdev->link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800560 return;
Yijing Wangc8fc9332015-05-21 15:05:03 +0800561
562 /*
563 * We allocate pcie_link_state for the component on the upstream
564 * end of a Link, so there's nothing to do unless this device has a
565 * Link on its secondary side.
566 */
567 if (!pdev->has_secondary_link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800568 return;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900569
Shaohua Li8e822df2009-06-08 09:27:25 +0800570 /* VIA has a strange chipset, root port is under a bridge */
Yijing Wang62f87c02012-07-24 17:20:03 +0800571 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900572 pdev->bus->self)
Shaohua Li8e822df2009-06-08 09:27:25 +0800573 return;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900574
Shaohua Li7d715a62008-02-25 09:46:41 +0800575 down_read(&pci_bus_sem);
576 if (list_empty(&pdev->subordinate->devices))
577 goto out;
578
Shaohua Li7d715a62008-02-25 09:46:41 +0800579 mutex_lock(&aspm_lock);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900580 link = alloc_pcie_link_state(pdev);
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900581 if (!link)
582 goto unlock;
583 /*
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900584 * Setup initial ASPM state. Note that we need to configure
585 * upstream links also because capable state of them can be
586 * update through pcie_aspm_cap_init().
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900587 */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900588 pcie_aspm_cap_init(link, blacklist);
Shaohua Li7d715a62008-02-25 09:46:41 +0800589
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900590 /* Setup initial Clock PM state */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900591 pcie_clkpm_cap_init(link, blacklist);
Matthew Garrett41cd7662010-06-09 16:05:07 -0400592
593 /*
594 * At this stage drivers haven't had an opportunity to change the
595 * link policy setting. Enabling ASPM on broken hardware can cripple
596 * it even before the driver has had a chance to disable ASPM, so
597 * default to a safe level right now. If we're enabling ASPM beyond
598 * the BIOS's expectation, we'll do so once pci_enable_device() is
599 * called.
600 */
Matthew Garrett3c076352011-11-10 16:38:33 -0500601 if (aspm_policy != POLICY_POWERSAVE) {
Matthew Garrett41cd7662010-06-09 16:05:07 -0400602 pcie_config_aspm_path(link);
603 pcie_set_clkpm(link, policy_to_clkpm_state(link));
604 }
605
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900606unlock:
Shaohua Li7d715a62008-02-25 09:46:41 +0800607 mutex_unlock(&aspm_lock);
608out:
609 up_read(&pci_bus_sem);
610}
611
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900612/* Recheck latencies and update aspm_capable for links under the root */
613static void pcie_update_aspm_capable(struct pcie_link_state *root)
614{
615 struct pcie_link_state *link;
616 BUG_ON(root->parent);
617 list_for_each_entry(link, &link_list, sibling) {
618 if (link->root != root)
619 continue;
620 link->aspm_capable = link->aspm_support;
621 }
622 list_for_each_entry(link, &link_list, sibling) {
623 struct pci_dev *child;
624 struct pci_bus *linkbus = link->pdev->subordinate;
625 if (link->root != root)
626 continue;
627 list_for_each_entry(child, &linkbus->devices, bus_list) {
Yijing Wang62f87c02012-07-24 17:20:03 +0800628 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
629 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900630 continue;
631 pcie_aspm_check_latency(child);
632 }
633 }
634}
635
Shaohua Li7d715a62008-02-25 09:46:41 +0800636/* @pdev: the endpoint device */
637void pcie_aspm_exit_link_state(struct pci_dev *pdev)
638{
639 struct pci_dev *parent = pdev->bus->self;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900640 struct pcie_link_state *link, *root, *parent_link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800641
Myron Stowe84fb9132013-01-31 16:29:25 -0700642 if (!parent || !parent->link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800643 return;
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900644
Shaohua Li7d715a62008-02-25 09:46:41 +0800645 down_read(&pci_bus_sem);
646 mutex_lock(&aspm_lock);
Shaohua Li7d715a62008-02-25 09:46:41 +0800647 /*
648 * All PCIe functions are in one slot, remove one function will remove
Alex Chiang3419c752009-01-28 14:59:18 -0700649 * the whole slot, so just wait until we are the last function left.
Shaohua Li7d715a62008-02-25 09:46:41 +0800650 */
Alex Chiang3419c752009-01-28 14:59:18 -0700651 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
Shaohua Li7d715a62008-02-25 09:46:41 +0800652 goto out;
653
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900654 link = parent->link_state;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900655 root = link->root;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900656 parent_link = link->parent;
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900657
Shaohua Li7d715a62008-02-25 09:46:41 +0800658 /* All functions are removed, so just disable ASPM for the link */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900659 pcie_config_aspm_link(link, 0);
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900660 list_del(&link->sibling);
661 list_del(&link->link);
Shaohua Li7d715a62008-02-25 09:46:41 +0800662 /* Clock PM is for endpoint device */
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900663 free_link_state(link);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900664
665 /* Recheck latencies and configure upstream links */
Kenji Kaneshigeb26a34a2009-11-06 11:25:13 +0900666 if (parent_link) {
667 pcie_update_aspm_capable(root);
668 pcie_config_aspm_path(parent_link);
669 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800670out:
671 mutex_unlock(&aspm_lock);
672 up_read(&pci_bus_sem);
673}
674
675/* @pdev: the root port or switch downstream port */
676void pcie_aspm_pm_state_change(struct pci_dev *pdev)
677{
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900678 struct pcie_link_state *link = pdev->link_state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800679
Yijing Wangf9b8cd72015-05-19 11:41:34 +0800680 if (aspm_disabled || !link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800681 return;
682 /*
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900683 * Devices changed PM state, we should recheck if latency
684 * meets all functions' requirement
Shaohua Li7d715a62008-02-25 09:46:41 +0800685 */
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900686 down_read(&pci_bus_sem);
687 mutex_lock(&aspm_lock);
688 pcie_update_aspm_capable(link->root);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900689 pcie_config_aspm_path(link);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900690 mutex_unlock(&aspm_lock);
691 up_read(&pci_bus_sem);
Shaohua Li7d715a62008-02-25 09:46:41 +0800692}
693
Naga Chumbalkar1a680b72011-03-21 03:29:08 +0000694void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
695{
696 struct pcie_link_state *link = pdev->link_state;
697
Yijing Wangf9b8cd72015-05-19 11:41:34 +0800698 if (aspm_disabled || !link)
Naga Chumbalkar1a680b72011-03-21 03:29:08 +0000699 return;
700
701 if (aspm_policy != POLICY_POWERSAVE)
702 return;
703
Naga Chumbalkar1a680b72011-03-21 03:29:08 +0000704 down_read(&pci_bus_sem);
705 mutex_lock(&aspm_lock);
706 pcie_config_aspm_path(link);
707 pcie_set_clkpm(link, policy_to_clkpm_state(link));
708 mutex_unlock(&aspm_lock);
709 up_read(&pci_bus_sem);
710}
711
Bjorn Helgaase127a042015-05-20 12:13:05 -0500712static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
Shaohua Li7d715a62008-02-25 09:46:41 +0800713{
714 struct pci_dev *parent = pdev->bus->self;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900715 struct pcie_link_state *link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800716
Matthew Garrett3c076352011-11-10 16:38:33 -0500717 if (!pci_is_pcie(pdev))
718 return;
719
Yijing Wangc8fc9332015-05-21 15:05:03 +0800720 if (pdev->has_secondary_link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800721 parent = pdev;
722 if (!parent || !parent->link_state)
723 return;
724
Bjorn Helgaas2add0ec2013-05-21 10:56:51 -0600725 /*
726 * A driver requested that ASPM be disabled on this device, but
727 * if we don't have permission to manage ASPM (e.g., on ACPI
728 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
729 * the _OSC method), we can't honor that request. Windows has
730 * a similar mechanism using "PciASPMOptOut", which is also
731 * ignored in this situation.
732 */
Bjorn Helgaase127a042015-05-20 12:13:05 -0500733 if (aspm_disabled) {
Bjorn Helgaas2add0ec2013-05-21 10:56:51 -0600734 dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
735 return;
736 }
737
Yinghai Lu9f728f52011-05-12 17:11:47 -0700738 if (sem)
739 down_read(&pci_bus_sem);
Shaohua Li7d715a62008-02-25 09:46:41 +0800740 mutex_lock(&aspm_lock);
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900741 link = parent->link_state;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900742 if (state & PCIE_LINK_STATE_L0S)
743 link->aspm_disable |= ASPM_STATE_L0S;
744 if (state & PCIE_LINK_STATE_L1)
745 link->aspm_disable |= ASPM_STATE_L1;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900746 pcie_config_aspm_link(link, policy_to_aspm_state(link));
747
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900748 if (state & PCIE_LINK_STATE_CLKPM) {
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900749 link->clkpm_capable = 0;
750 pcie_set_clkpm(link, 0);
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900751 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800752 mutex_unlock(&aspm_lock);
Yinghai Lu9f728f52011-05-12 17:11:47 -0700753 if (sem)
754 up_read(&pci_bus_sem);
755}
756
757void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
758{
Bjorn Helgaase127a042015-05-20 12:13:05 -0500759 __pci_disable_link_state(pdev, state, false);
Yinghai Lu9f728f52011-05-12 17:11:47 -0700760}
761EXPORT_SYMBOL(pci_disable_link_state_locked);
762
Yijing Wang2dfca872013-05-28 16:03:22 +0800763/**
764 * pci_disable_link_state - Disable device's link state, so the link will
765 * never enter specific states. Note that if the BIOS didn't grant ASPM
766 * control to the OS, this does nothing because we can't touch the LNKCTL
767 * register.
768 *
769 * @pdev: PCI device
770 * @state: ASPM link state to disable
771 */
Yinghai Lu9f728f52011-05-12 17:11:47 -0700772void pci_disable_link_state(struct pci_dev *pdev, int state)
773{
Bjorn Helgaase127a042015-05-20 12:13:05 -0500774 __pci_disable_link_state(pdev, state, true);
Shaohua Li7d715a62008-02-25 09:46:41 +0800775}
776EXPORT_SYMBOL(pci_disable_link_state);
777
778static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
779{
780 int i;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900781 struct pcie_link_state *link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800782
Naga Chumbalkarbbfa3062011-03-21 03:29:14 +0000783 if (aspm_disabled)
784 return -EPERM;
Shaohua Li7d715a62008-02-25 09:46:41 +0800785 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
786 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
787 break;
788 if (i >= ARRAY_SIZE(policy_str))
789 return -EINVAL;
790 if (i == aspm_policy)
791 return 0;
792
793 down_read(&pci_bus_sem);
794 mutex_lock(&aspm_lock);
795 aspm_policy = i;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900796 list_for_each_entry(link, &link_list, sibling) {
797 pcie_config_aspm_link(link, policy_to_aspm_state(link));
798 pcie_set_clkpm(link, policy_to_clkpm_state(link));
Shaohua Li7d715a62008-02-25 09:46:41 +0800799 }
800 mutex_unlock(&aspm_lock);
801 up_read(&pci_bus_sem);
802 return 0;
803}
804
805static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
806{
807 int i, cnt = 0;
808 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
809 if (i == aspm_policy)
810 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
811 else
812 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
813 return cnt;
814}
815
816module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
817 NULL, 0644);
818
819#ifdef CONFIG_PCIEASPM_DEBUG
820static ssize_t link_state_show(struct device *dev,
821 struct device_attribute *attr,
822 char *buf)
823{
824 struct pci_dev *pci_device = to_pci_dev(dev);
825 struct pcie_link_state *link_state = pci_device->link_state;
826
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900827 return sprintf(buf, "%d\n", link_state->aspm_enabled);
Shaohua Li7d715a62008-02-25 09:46:41 +0800828}
829
830static ssize_t link_state_store(struct device *dev,
831 struct device_attribute *attr,
832 const char *buf,
833 size_t n)
834{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900835 struct pci_dev *pdev = to_pci_dev(dev);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900836 struct pcie_link_state *link, *root = pdev->link_state->root;
Andy Lutomirski57d86a02015-11-19 08:05:35 -0800837 u32 state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800838
Naga Chumbalkarbbfa3062011-03-21 03:29:14 +0000839 if (aspm_disabled)
840 return -EPERM;
Shaohua Li7d715a62008-02-25 09:46:41 +0800841
Andy Lutomirski57d86a02015-11-19 08:05:35 -0800842 if (kstrtouint(buf, 10, &state))
843 return -EINVAL;
844 if ((state & ~ASPM_STATE_ALL) != 0)
845 return -EINVAL;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900846
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900847 down_read(&pci_bus_sem);
848 mutex_lock(&aspm_lock);
849 list_for_each_entry(link, &link_list, sibling) {
850 if (link->root != root)
851 continue;
852 pcie_config_aspm_link(link, state);
853 }
854 mutex_unlock(&aspm_lock);
855 up_read(&pci_bus_sem);
856 return n;
Shaohua Li7d715a62008-02-25 09:46:41 +0800857}
858
859static ssize_t clk_ctl_show(struct device *dev,
860 struct device_attribute *attr,
861 char *buf)
862{
863 struct pci_dev *pci_device = to_pci_dev(dev);
864 struct pcie_link_state *link_state = pci_device->link_state;
865
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900866 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
Shaohua Li7d715a62008-02-25 09:46:41 +0800867}
868
869static ssize_t clk_ctl_store(struct device *dev,
870 struct device_attribute *attr,
871 const char *buf,
872 size_t n)
873{
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900874 struct pci_dev *pdev = to_pci_dev(dev);
Chris J Arges94a90312014-12-05 17:02:42 -0600875 bool state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800876
Chris J Arges94a90312014-12-05 17:02:42 -0600877 if (strtobool(buf, &state))
Shaohua Li7d715a62008-02-25 09:46:41 +0800878 return -EINVAL;
Shaohua Li7d715a62008-02-25 09:46:41 +0800879
880 down_read(&pci_bus_sem);
881 mutex_lock(&aspm_lock);
Chris J Arges94a90312014-12-05 17:02:42 -0600882 pcie_set_clkpm_nocheck(pdev->link_state, state);
Shaohua Li7d715a62008-02-25 09:46:41 +0800883 mutex_unlock(&aspm_lock);
884 up_read(&pci_bus_sem);
885
886 return n;
887}
888
889static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
890static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
891
892static char power_group[] = "power";
893void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
894{
895 struct pcie_link_state *link_state = pdev->link_state;
896
Yijing Wangf9b8cd72015-05-19 11:41:34 +0800897 if (!link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800898 return;
899
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900900 if (link_state->aspm_support)
Shaohua Li7d715a62008-02-25 09:46:41 +0800901 sysfs_add_file_to_group(&pdev->dev.kobj,
902 &dev_attr_link_state.attr, power_group);
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900903 if (link_state->clkpm_capable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800904 sysfs_add_file_to_group(&pdev->dev.kobj,
905 &dev_attr_clk_ctl.attr, power_group);
906}
907
908void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
909{
910 struct pcie_link_state *link_state = pdev->link_state;
911
Yijing Wangf9b8cd72015-05-19 11:41:34 +0800912 if (!link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800913 return;
914
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900915 if (link_state->aspm_support)
Shaohua Li7d715a62008-02-25 09:46:41 +0800916 sysfs_remove_file_from_group(&pdev->dev.kobj,
917 &dev_attr_link_state.attr, power_group);
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900918 if (link_state->clkpm_capable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800919 sysfs_remove_file_from_group(&pdev->dev.kobj,
920 &dev_attr_clk_ctl.attr, power_group);
921}
922#endif
923
924static int __init pcie_aspm_disable(char *str)
925{
Shaohua Lid6d38572008-07-23 10:32:42 +0800926 if (!strcmp(str, "off")) {
Matthew Garrett3c076352011-11-10 16:38:33 -0500927 aspm_policy = POLICY_DEFAULT;
Shaohua Lid6d38572008-07-23 10:32:42 +0800928 aspm_disabled = 1;
Rafael J. Wysocki8b8bae92011-03-05 13:21:51 +0100929 aspm_support_enabled = false;
Shaohua Lid6d38572008-07-23 10:32:42 +0800930 printk(KERN_INFO "PCIe ASPM is disabled\n");
931 } else if (!strcmp(str, "force")) {
932 aspm_force = 1;
Michael Witten8072ba12011-06-28 06:15:05 +0000933 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
Shaohua Lid6d38572008-07-23 10:32:42 +0800934 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800935 return 1;
936}
937
Shaohua Lid6d38572008-07-23 10:32:42 +0800938__setup("pcie_aspm=", pcie_aspm_disable);
Shaohua Li7d715a62008-02-25 09:46:41 +0800939
Shaohua Li5fde2442008-07-23 10:32:24 +0800940void pcie_no_aspm(void)
941{
Matthew Garrett3c076352011-11-10 16:38:33 -0500942 /*
943 * Disabling ASPM is intended to prevent the kernel from modifying
944 * existing hardware state, not to clear existing state. To that end:
945 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
946 * (b) prevent userspace from changing policy
947 */
948 if (!aspm_force) {
949 aspm_policy = POLICY_DEFAULT;
Shaohua Lid6d38572008-07-23 10:32:42 +0800950 aspm_disabled = 1;
Matthew Garrett3c076352011-11-10 16:38:33 -0500951 }
Shaohua Li5fde2442008-07-23 10:32:24 +0800952}
953
Rafael J. Wysocki8b8bae92011-03-05 13:21:51 +0100954bool pcie_aspm_support_enabled(void)
955{
956 return aspm_support_enabled;
957}
958EXPORT_SYMBOL(pcie_aspm_support_enabled);