Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 - 2006 NetXen, Inc. |
| 3 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 4 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 9 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 14 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 18 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 19 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 20 | * The full GNU General Public License is included in this distribution |
| 21 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 22 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 23 | * Contact Information: |
| 24 | * info@netxen.com |
| 25 | * NetXen, |
| 26 | * 3965 Freedom Circle, Fourth floor, |
| 27 | * Santa Clara, CA 95054 |
| 28 | * |
| 29 | * |
| 30 | * Source file for NIC routines to access the Phantom hardware |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include "netxen_nic.h" |
| 35 | #include "netxen_nic_hw.h" |
| 36 | #include "netxen_nic_phan_reg.h" |
| 37 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 38 | |
Arnaldo Carvalho de Melo | c9bdd4b | 2007-03-12 20:09:15 -0300 | [diff] [blame] | 39 | #include <net/ip.h> |
| 40 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 41 | #define MASK(n) ((1ULL<<(n))-1) |
| 42 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 43 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 44 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
| 45 | |
| 46 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) |
| 47 | |
| 48 | #define CRB_BLK(off) ((off >> 20) & 0x3f) |
| 49 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) |
| 50 | #define CRB_WINDOW_2M (0x130060) |
| 51 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) |
| 52 | #define CRB_INDIRECT_2M (0x1e0000UL) |
| 53 | |
| 54 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 55 | static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { |
| 56 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
| 57 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ |
| 58 | {1, 0x0110000, 0x0120000, 0x130000}, |
| 59 | {1, 0x0120000, 0x0122000, 0x124000}, |
| 60 | {1, 0x0130000, 0x0132000, 0x126000}, |
| 61 | {1, 0x0140000, 0x0142000, 0x128000}, |
| 62 | {1, 0x0150000, 0x0152000, 0x12a000}, |
| 63 | {1, 0x0160000, 0x0170000, 0x110000}, |
| 64 | {1, 0x0170000, 0x0172000, 0x12e000}, |
| 65 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 66 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 67 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 68 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 69 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 70 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 71 | {1, 0x01e0000, 0x01e0800, 0x122000}, |
| 72 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 73 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ |
| 74 | {{{0, 0, 0, 0} } }, /* 3: */ |
| 75 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ |
| 76 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ |
| 77 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ |
| 78 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ |
| 79 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ |
| 80 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 81 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 82 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 83 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 84 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 85 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 86 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 87 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 88 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 89 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 90 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 91 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 92 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 93 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 94 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, |
| 95 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ |
| 96 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 97 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 98 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 99 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 100 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 101 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 102 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 103 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 104 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 105 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 106 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 107 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 108 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 109 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 110 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, |
| 111 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ |
| 112 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 113 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 114 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 115 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 116 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 117 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 118 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 119 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 120 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 121 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 122 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 123 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 124 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 125 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 126 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, |
| 127 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ |
| 128 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 129 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 130 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 131 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 132 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 133 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 134 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 135 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 136 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 137 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 138 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 139 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 140 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 141 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 142 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, |
| 143 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ |
| 144 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ |
| 145 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ |
| 146 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ |
| 147 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ |
| 148 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ |
| 149 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ |
| 150 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ |
| 151 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ |
| 152 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ |
| 153 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ |
| 154 | {{{0, 0, 0, 0} } }, /* 23: */ |
| 155 | {{{0, 0, 0, 0} } }, /* 24: */ |
| 156 | {{{0, 0, 0, 0} } }, /* 25: */ |
| 157 | {{{0, 0, 0, 0} } }, /* 26: */ |
| 158 | {{{0, 0, 0, 0} } }, /* 27: */ |
| 159 | {{{0, 0, 0, 0} } }, /* 28: */ |
| 160 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ |
| 161 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ |
| 162 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ |
| 163 | {{{0} } }, /* 32: PCI */ |
| 164 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ |
| 165 | {1, 0x2110000, 0x2120000, 0x130000}, |
| 166 | {1, 0x2120000, 0x2122000, 0x124000}, |
| 167 | {1, 0x2130000, 0x2132000, 0x126000}, |
| 168 | {1, 0x2140000, 0x2142000, 0x128000}, |
| 169 | {1, 0x2150000, 0x2152000, 0x12a000}, |
| 170 | {1, 0x2160000, 0x2170000, 0x110000}, |
| 171 | {1, 0x2170000, 0x2172000, 0x12e000}, |
| 172 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 173 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 174 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 175 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 176 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 177 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 178 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 179 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 180 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ |
| 181 | {{{0} } }, /* 35: */ |
| 182 | {{{0} } }, /* 36: */ |
| 183 | {{{0} } }, /* 37: */ |
| 184 | {{{0} } }, /* 38: */ |
| 185 | {{{0} } }, /* 39: */ |
| 186 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ |
| 187 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ |
| 188 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ |
| 189 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ |
| 190 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ |
| 191 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ |
| 192 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ |
| 193 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ |
| 194 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ |
| 195 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ |
| 196 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ |
| 197 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ |
| 198 | {{{0} } }, /* 52: */ |
| 199 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ |
| 200 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ |
| 201 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ |
| 202 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ |
| 203 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ |
| 204 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ |
| 205 | {{{0} } }, /* 59: I2C0 */ |
| 206 | {{{0} } }, /* 60: I2C1 */ |
| 207 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ |
| 208 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ |
| 209 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ |
| 210 | }; |
| 211 | |
| 212 | /* |
| 213 | * top 12 bits of crb internal address (hub, agent) |
| 214 | */ |
| 215 | static unsigned crb_hub_agt[64] = |
| 216 | { |
| 217 | 0, |
| 218 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 219 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, |
| 220 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, |
| 221 | 0, |
| 222 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, |
| 223 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, |
| 224 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, |
| 225 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, |
| 226 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, |
| 227 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, |
| 228 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, |
| 229 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 230 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 231 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 232 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, |
| 233 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 234 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, |
| 235 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, |
| 236 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, |
| 237 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, |
| 238 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, |
| 239 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, |
| 240 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, |
| 241 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, |
| 242 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, |
| 243 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, |
| 244 | 0, |
| 245 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, |
| 246 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, |
| 247 | 0, |
| 248 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, |
| 249 | 0, |
| 250 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 251 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, |
| 252 | 0, |
| 253 | 0, |
| 254 | 0, |
| 255 | 0, |
| 256 | 0, |
| 257 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 258 | 0, |
| 259 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, |
| 260 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, |
| 261 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, |
| 262 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, |
| 263 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, |
| 264 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, |
| 265 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, |
| 266 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 267 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 268 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 269 | 0, |
| 270 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, |
| 271 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, |
| 272 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, |
| 273 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, |
| 274 | 0, |
| 275 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, |
| 276 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, |
| 277 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, |
| 278 | 0, |
| 279 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, |
| 280 | 0, |
| 281 | }; |
| 282 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 283 | /* PCI Windowing for DDR regions. */ |
| 284 | |
| 285 | #define ADDR_IN_RANGE(addr, low, high) \ |
| 286 | (((addr) <= (high)) && ((addr) >= (low))) |
| 287 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 288 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 289 | #define NETXEN_MIN_MTU 64 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 290 | #define NETXEN_ETH_FCS_SIZE 4 |
| 291 | #define NETXEN_ENET_HEADER_SIZE 14 |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 292 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 293 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) |
| 294 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) |
| 295 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) |
| 296 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 297 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL |
| 298 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL |
| 299 | #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL |
| 300 | #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL |
| 301 | |
| 302 | #define NETXEN_NIC_WINDOW_MARGIN 0x100000 |
| 303 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 304 | int netxen_nic_set_mac(struct net_device *netdev, void *p) |
| 305 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 306 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 307 | struct sockaddr *addr = p; |
| 308 | |
| 309 | if (netif_running(netdev)) |
| 310 | return -EBUSY; |
| 311 | |
| 312 | if (!is_valid_ether_addr(addr->sa_data)) |
| 313 | return -EADDRNOTAVAIL; |
| 314 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 315 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
| 316 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 317 | /* For P3, MAC addr is not set in NIU */ |
| 318 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 319 | if (adapter->macaddr_set) |
| 320 | adapter->macaddr_set(adapter, addr->sa_data); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 325 | #define NETXEN_UNICAST_ADDR(port, index) \ |
| 326 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) |
| 327 | #define NETXEN_MCAST_ADDR(port, index) \ |
| 328 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) |
| 329 | #define MAC_HI(addr) \ |
| 330 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) |
| 331 | #define MAC_LO(addr) \ |
| 332 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) |
| 333 | |
| 334 | static int |
| 335 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) |
| 336 | { |
| 337 | u32 val = 0; |
| 338 | u16 port = adapter->physical_port; |
| 339 | u8 *addr = adapter->netdev->dev_addr; |
| 340 | |
| 341 | if (adapter->mc_enabled) |
| 342 | return 0; |
| 343 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 344 | adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 345 | val |= (1UL << (28+port)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 346 | adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 347 | |
| 348 | /* add broadcast addr to filter */ |
| 349 | val = 0xffffff; |
| 350 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
| 351 | netxen_crb_writelit_adapter(adapter, |
| 352 | NETXEN_UNICAST_ADDR(port, 0)+4, val); |
| 353 | |
| 354 | /* add station addr to filter */ |
| 355 | val = MAC_HI(addr); |
| 356 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
| 357 | val = MAC_LO(addr); |
| 358 | netxen_crb_writelit_adapter(adapter, |
| 359 | NETXEN_UNICAST_ADDR(port, 1)+4, val); |
| 360 | |
| 361 | adapter->mc_enabled = 1; |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static int |
| 366 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) |
| 367 | { |
| 368 | u32 val = 0; |
| 369 | u16 port = adapter->physical_port; |
| 370 | u8 *addr = adapter->netdev->dev_addr; |
| 371 | |
| 372 | if (!adapter->mc_enabled) |
| 373 | return 0; |
| 374 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 375 | adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 376 | val &= ~(1UL << (28+port)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 377 | adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 378 | |
| 379 | val = MAC_HI(addr); |
| 380 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
| 381 | val = MAC_LO(addr); |
| 382 | netxen_crb_writelit_adapter(adapter, |
| 383 | NETXEN_UNICAST_ADDR(port, 0)+4, val); |
| 384 | |
| 385 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
| 386 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); |
| 387 | |
| 388 | adapter->mc_enabled = 0; |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static int |
| 393 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, |
| 394 | int index, u8 *addr) |
| 395 | { |
| 396 | u32 hi = 0, lo = 0; |
| 397 | u16 port = adapter->physical_port; |
| 398 | |
| 399 | lo = MAC_LO(addr); |
| 400 | hi = MAC_HI(addr); |
| 401 | |
| 402 | netxen_crb_writelit_adapter(adapter, |
| 403 | NETXEN_MCAST_ADDR(port, index), hi); |
| 404 | netxen_crb_writelit_adapter(adapter, |
| 405 | NETXEN_MCAST_ADDR(port, index)+4, lo); |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 410 | void netxen_p2_nic_set_multi(struct net_device *netdev) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 411 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 412 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 413 | struct dev_mc_list *mc_ptr; |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 414 | u8 null_addr[6]; |
| 415 | int index = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 416 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 417 | memset(null_addr, 0, 6); |
| 418 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 419 | if (netdev->flags & IFF_PROMISC) { |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 420 | |
| 421 | adapter->set_promisc(adapter, |
| 422 | NETXEN_NIU_PROMISC_MODE); |
| 423 | |
| 424 | /* Full promiscuous mode */ |
| 425 | netxen_nic_disable_mcast_filter(adapter); |
| 426 | |
| 427 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 428 | } |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 429 | |
| 430 | if (netdev->mc_count == 0) { |
| 431 | adapter->set_promisc(adapter, |
| 432 | NETXEN_NIU_NON_PROMISC_MODE); |
| 433 | netxen_nic_disable_mcast_filter(adapter); |
| 434 | return; |
| 435 | } |
| 436 | |
| 437 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); |
| 438 | if (netdev->flags & IFF_ALLMULTI || |
| 439 | netdev->mc_count > adapter->max_mc_count) { |
| 440 | netxen_nic_disable_mcast_filter(adapter); |
| 441 | return; |
| 442 | } |
| 443 | |
| 444 | netxen_nic_enable_mcast_filter(adapter); |
| 445 | |
| 446 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++) |
| 447 | netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr); |
| 448 | |
| 449 | if (index != netdev->mc_count) |
| 450 | printk(KERN_WARNING "%s: %s multicast address count mismatch\n", |
| 451 | netxen_nic_driver_name, netdev->name); |
| 452 | |
| 453 | /* Clear out remaining addresses */ |
| 454 | for (; index < adapter->max_mc_count; index++) |
| 455 | netxen_nic_set_mcast_addr(adapter, index, null_addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 456 | } |
| 457 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 458 | static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, |
| 459 | u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list) |
| 460 | { |
| 461 | nx_mac_list_t *cur, *prev; |
| 462 | |
| 463 | /* if in del_list, move it to adapter->mac_list */ |
| 464 | for (cur = *del_list, prev = NULL; cur;) { |
| 465 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { |
| 466 | if (prev == NULL) |
| 467 | *del_list = cur->next; |
| 468 | else |
| 469 | prev->next = cur->next; |
| 470 | cur->next = adapter->mac_list; |
| 471 | adapter->mac_list = cur; |
| 472 | return 0; |
| 473 | } |
| 474 | prev = cur; |
| 475 | cur = cur->next; |
| 476 | } |
| 477 | |
| 478 | /* make sure to add each mac address only once */ |
| 479 | for (cur = adapter->mac_list; cur; cur = cur->next) { |
| 480 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) |
| 481 | return 0; |
| 482 | } |
| 483 | /* not in del_list, create new entry and add to add_list */ |
| 484 | cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL); |
| 485 | if (cur == NULL) { |
| 486 | printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may" |
| 487 | "not work properly from now.\n", __func__); |
| 488 | return -1; |
| 489 | } |
| 490 | |
| 491 | memcpy(cur->mac_addr, addr, ETH_ALEN); |
| 492 | cur->next = *add_list; |
| 493 | *add_list = cur; |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | static int |
| 498 | netxen_send_cmd_descs(struct netxen_adapter *adapter, |
| 499 | struct cmd_desc_type0 *cmd_desc_arr, int nr_elements) |
| 500 | { |
| 501 | uint32_t i, producer; |
| 502 | struct netxen_cmd_buffer *pbuf; |
| 503 | struct cmd_desc_type0 *cmd_desc; |
| 504 | |
| 505 | if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) { |
| 506 | printk(KERN_WARNING "%s: Too many command descriptors in a " |
| 507 | "request\n", __func__); |
| 508 | return -EINVAL; |
| 509 | } |
| 510 | |
| 511 | i = 0; |
| 512 | |
| 513 | producer = adapter->cmd_producer; |
| 514 | do { |
| 515 | cmd_desc = &cmd_desc_arr[i]; |
| 516 | |
| 517 | pbuf = &adapter->cmd_buf_arr[producer]; |
| 518 | pbuf->mss = 0; |
| 519 | pbuf->total_length = 0; |
| 520 | pbuf->skb = NULL; |
| 521 | pbuf->cmd = 0; |
| 522 | pbuf->frag_count = 0; |
| 523 | pbuf->port = 0; |
| 524 | |
| 525 | /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */ |
| 526 | memcpy(&adapter->ahw.cmd_desc_head[producer], |
| 527 | &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); |
| 528 | |
| 529 | producer = get_next_index(producer, |
| 530 | adapter->max_tx_desc_count); |
| 531 | i++; |
| 532 | |
| 533 | } while (i != nr_elements); |
| 534 | |
| 535 | adapter->cmd_producer = producer; |
| 536 | |
| 537 | /* write producer index to start the xmit */ |
| 538 | |
| 539 | netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer); |
| 540 | |
| 541 | return 0; |
| 542 | } |
| 543 | |
| 544 | #define NIC_REQUEST 0x14 |
| 545 | #define NETXEN_MAC_EVENT 0x1 |
| 546 | |
| 547 | static int nx_p3_sre_macaddr_change(struct net_device *dev, |
| 548 | u8 *addr, unsigned op) |
| 549 | { |
| 550 | struct netxen_adapter *adapter = (struct netxen_adapter *)dev->priv; |
| 551 | nx_nic_req_t req; |
| 552 | nx_mac_req_t mac_req; |
| 553 | int rv; |
| 554 | |
| 555 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 556 | req.qhdr |= (NIC_REQUEST << 23); |
| 557 | req.req_hdr |= NETXEN_MAC_EVENT; |
| 558 | req.req_hdr |= ((u64)adapter->portnum << 16); |
| 559 | mac_req.op = op; |
| 560 | memcpy(&mac_req.mac_addr, addr, 6); |
| 561 | req.words[0] = cpu_to_le64(*(u64 *)&mac_req); |
| 562 | |
| 563 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 564 | if (rv != 0) { |
| 565 | printk(KERN_ERR "ERROR. Could not send mac update\n"); |
| 566 | return rv; |
| 567 | } |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | void netxen_p3_nic_set_multi(struct net_device *netdev) |
| 573 | { |
| 574 | struct netxen_adapter *adapter = netdev_priv(netdev); |
| 575 | nx_mac_list_t *cur, *next, *del_list, *add_list = NULL; |
| 576 | struct dev_mc_list *mc_ptr; |
| 577 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 578 | |
| 579 | adapter->set_promisc(adapter, NETXEN_NIU_PROMISC_MODE); |
| 580 | |
| 581 | /* |
| 582 | * Programming mac addresses will automaticly enabling L2 filtering. |
| 583 | * HW will replace timestamp with L2 conid when L2 filtering is |
| 584 | * enabled. This causes problem for LSA. Do not enabling L2 filtering |
| 585 | * until that problem is fixed. |
| 586 | */ |
| 587 | if ((netdev->flags & IFF_PROMISC) || |
| 588 | (netdev->mc_count > adapter->max_mc_count)) |
| 589 | return; |
| 590 | |
| 591 | del_list = adapter->mac_list; |
| 592 | adapter->mac_list = NULL; |
| 593 | |
| 594 | nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list); |
| 595 | if (netdev->mc_count > 0) { |
| 596 | nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list); |
| 597 | for (mc_ptr = netdev->mc_list; mc_ptr; |
| 598 | mc_ptr = mc_ptr->next) { |
| 599 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, |
| 600 | &add_list, &del_list); |
| 601 | } |
| 602 | } |
| 603 | for (cur = del_list; cur;) { |
| 604 | nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL); |
| 605 | next = cur->next; |
| 606 | kfree(cur); |
| 607 | cur = next; |
| 608 | } |
| 609 | for (cur = add_list; cur;) { |
| 610 | nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD); |
| 611 | next = cur->next; |
| 612 | cur->next = adapter->mac_list; |
| 613 | adapter->mac_list = cur; |
| 614 | cur = next; |
| 615 | } |
| 616 | } |
| 617 | |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 618 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
| 619 | |
| 620 | /* |
| 621 | * Send the interrupt coalescing parameter set by ethtool to the card. |
| 622 | */ |
| 623 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter) |
| 624 | { |
| 625 | nx_nic_req_t req; |
| 626 | int rv; |
| 627 | |
| 628 | memset(&req, 0, sizeof(nx_nic_req_t)); |
| 629 | |
| 630 | req.qhdr |= (NIC_REQUEST << 23); |
| 631 | req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE; |
| 632 | req.req_hdr |= ((u64)adapter->portnum << 16); |
| 633 | |
| 634 | memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal)); |
| 635 | |
| 636 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
| 637 | if (rv != 0) { |
| 638 | printk(KERN_ERR "ERROR. Could not send " |
| 639 | "interrupt coalescing parameters\n"); |
| 640 | } |
| 641 | |
| 642 | return rv; |
| 643 | } |
| 644 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 645 | /* |
| 646 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit |
| 647 | * @returns 0 on success, negative on failure |
| 648 | */ |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 649 | |
| 650 | #define MTU_FUDGE_FACTOR 100 |
| 651 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 652 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
| 653 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 654 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 655 | int max_mtu; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 656 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 657 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
| 658 | max_mtu = P3_MAX_MTU; |
| 659 | else |
| 660 | max_mtu = P2_MAX_MTU; |
| 661 | |
| 662 | if (mtu > max_mtu) { |
| 663 | printk(KERN_ERR "%s: mtu > %d bytes unsupported\n", |
| 664 | netdev->name, max_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 665 | return -EINVAL; |
| 666 | } |
| 667 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 668 | if (adapter->set_mtu) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 669 | adapter->set_mtu(adapter, mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 670 | netdev->mtu = mtu; |
| 671 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 672 | mtu += MTU_FUDGE_FACTOR; |
| 673 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
| 674 | nx_fw_cmd_set_mtu(adapter, mtu); |
| 675 | else if (adapter->set_mtu) |
| 676 | adapter->set_mtu(adapter, mtu); |
| 677 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 678 | return 0; |
| 679 | } |
| 680 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 681 | int netxen_is_flash_supported(struct netxen_adapter *adapter) |
| 682 | { |
| 683 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; |
| 684 | int addr, val01, val02, i, j; |
| 685 | |
| 686 | /* if the flash size less than 4Mb, make huge war cry and die */ |
| 687 | for (j = 1; j < 4; j++) { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 688 | addr = j * NETXEN_NIC_WINDOW_MARGIN; |
Denis Cheng | ff8ac60 | 2007-09-02 18:30:18 +0800 | [diff] [blame] | 689 | for (i = 0; i < ARRAY_SIZE(locs); i++) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 690 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 |
| 691 | && netxen_rom_fast_read(adapter, (addr + locs[i]), |
| 692 | &val02) == 0) { |
| 693 | if (val01 == val02) |
| 694 | return -1; |
| 695 | } else |
| 696 | return -1; |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 704 | int size, __le32 * buf) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 705 | { |
| 706 | int i, addr; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 707 | __le32 *ptr32; |
| 708 | u32 v; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 709 | |
| 710 | addr = base; |
| 711 | ptr32 = buf; |
| 712 | for (i = 0; i < size / sizeof(u32); i++) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 713 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 714 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 715 | *ptr32 = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 716 | ptr32++; |
| 717 | addr += sizeof(u32); |
| 718 | } |
| 719 | if ((char *)buf + size > (char *)ptr32) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 720 | __le32 local; |
| 721 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 722 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 723 | local = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 724 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
| 725 | } |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 730 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 731 | { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 732 | __le32 *pmac = (__le32 *) & mac[0]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 733 | |
| 734 | if (netxen_get_flash_block(adapter, |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 735 | NETXEN_USER_START + |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 736 | offsetof(struct netxen_new_user_info, |
| 737 | mac_addr), |
| 738 | FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { |
| 739 | return -1; |
| 740 | } |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 741 | if (*mac == cpu_to_le64(~0ULL)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 742 | if (netxen_get_flash_block(adapter, |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 743 | NETXEN_USER_START_OLD + |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 744 | offsetof(struct netxen_user_old_info, |
| 745 | mac_addr), |
| 746 | FLASH_NUM_PORTS * sizeof(u64), |
| 747 | pmac) == -1) |
| 748 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 749 | if (*mac == cpu_to_le64(~0ULL)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 750 | return -1; |
| 751 | } |
| 752 | return 0; |
| 753 | } |
| 754 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 755 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 756 | |
| 757 | static int crb_win_lock(struct netxen_adapter *adapter) |
| 758 | { |
| 759 | int done = 0, timeout = 0; |
| 760 | |
| 761 | while (!done) { |
| 762 | /* acquire semaphore3 from PCI HW block */ |
| 763 | adapter->hw_read_wx(adapter, |
| 764 | NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4); |
| 765 | if (done == 1) |
| 766 | break; |
| 767 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) |
| 768 | return -1; |
| 769 | timeout++; |
| 770 | udelay(1); |
| 771 | } |
| 772 | netxen_crb_writelit_adapter(adapter, |
| 773 | NETXEN_CRB_WIN_LOCK_ID, adapter->portnum); |
| 774 | return 0; |
| 775 | } |
| 776 | |
| 777 | static void crb_win_unlock(struct netxen_adapter *adapter) |
| 778 | { |
| 779 | int val; |
| 780 | |
| 781 | adapter->hw_read_wx(adapter, |
| 782 | NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4); |
| 783 | } |
| 784 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 785 | /* |
| 786 | * Changes the CRB window to the specified window. |
| 787 | */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 788 | void |
| 789 | netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 790 | { |
| 791 | void __iomem *offset; |
| 792 | u32 tmp; |
| 793 | int count = 0; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 794 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 795 | |
| 796 | if (adapter->curr_window == wndw) |
| 797 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 798 | /* |
| 799 | * Move the CRB window. |
| 800 | * We need to write to the "direct access" region of PCI |
| 801 | * to avoid a race condition where the window register has |
| 802 | * not been successfully written across CRB before the target |
| 803 | * register address is received by PCI. The direct region bypasses |
| 804 | * the CRB bus. |
| 805 | */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 806 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 807 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 808 | |
| 809 | if (wndw & 0x1) |
| 810 | wndw = NETXEN_WINDOW_ONE; |
| 811 | |
| 812 | writel(wndw, offset); |
| 813 | |
| 814 | /* MUST make sure window is set before we forge on... */ |
| 815 | while ((tmp = readl(offset)) != wndw) { |
| 816 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " |
| 817 | "registered properly: 0x%08x.\n", |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 818 | netxen_nic_driver_name, __func__, tmp); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 819 | mdelay(1); |
| 820 | if (count >= 10) |
| 821 | break; |
| 822 | count++; |
| 823 | } |
| 824 | |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 825 | if (wndw == NETXEN_WINDOW_ONE) |
| 826 | adapter->curr_window = 1; |
| 827 | else |
| 828 | adapter->curr_window = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 829 | } |
| 830 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 831 | /* |
| 832 | * Return -1 if off is not valid, |
| 833 | * 1 if window access is needed. 'off' is set to offset from |
| 834 | * CRB space in 128M pci map |
| 835 | * 0 if no window access is needed. 'off' is set to 2M addr |
| 836 | * In: 'off' is offset from base in 128M pci map |
| 837 | */ |
| 838 | static int |
| 839 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, |
| 840 | ulong *off, int len) |
| 841 | { |
| 842 | unsigned long end = *off + len; |
| 843 | crb_128M_2M_sub_block_map_t *m; |
| 844 | |
| 845 | |
| 846 | if (*off >= NETXEN_CRB_MAX) |
| 847 | return -1; |
| 848 | |
| 849 | if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) { |
| 850 | *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE + |
| 851 | (ulong)adapter->ahw.pci_base0; |
| 852 | return 0; |
| 853 | } |
| 854 | |
| 855 | if (*off < NETXEN_PCI_CRBSPACE) |
| 856 | return -1; |
| 857 | |
| 858 | *off -= NETXEN_PCI_CRBSPACE; |
| 859 | end = *off + len; |
| 860 | |
| 861 | /* |
| 862 | * Try direct map |
| 863 | */ |
| 864 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; |
| 865 | |
| 866 | if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) { |
| 867 | *off = *off + m->start_2M - m->start_128M + |
| 868 | (ulong)adapter->ahw.pci_base0; |
| 869 | return 0; |
| 870 | } |
| 871 | |
| 872 | /* |
| 873 | * Not in direct map, use crb window |
| 874 | */ |
| 875 | return 1; |
| 876 | } |
| 877 | |
| 878 | /* |
| 879 | * In: 'off' is offset from CRB space in 128M pci map |
| 880 | * Out: 'off' is 2M pci map addr |
| 881 | * side effect: lock crb window |
| 882 | */ |
| 883 | static void |
| 884 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off) |
| 885 | { |
| 886 | u32 win_read; |
| 887 | |
| 888 | adapter->crb_win = CRB_HI(*off); |
| 889 | writel(adapter->crb_win, (void *)(CRB_WINDOW_2M + |
| 890 | adapter->ahw.pci_base0)); |
| 891 | /* |
| 892 | * Read back value to make sure write has gone through before trying |
| 893 | * to use it. |
| 894 | */ |
| 895 | win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0)); |
| 896 | if (win_read != adapter->crb_win) { |
| 897 | printk(KERN_ERR "%s: Written crbwin (0x%x) != " |
| 898 | "Read crbwin (0x%x), off=0x%lx\n", |
| 899 | __func__, adapter->crb_win, win_read, *off); |
| 900 | } |
| 901 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + |
| 902 | (ulong)adapter->ahw.pci_base0; |
| 903 | } |
| 904 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 905 | int netxen_load_firmware(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 906 | { |
| 907 | int i; |
Linsys Contractor Mithlesh Thukral | e0e20a1 | 2007-02-28 05:16:40 -0800 | [diff] [blame] | 908 | u32 data, size = 0; |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 909 | u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 910 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 911 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4; |
| 912 | |
| 913 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 914 | adapter->pci_write_normalize(adapter, |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 915 | NETXEN_ROMUSB_GLB_CAS_RST, 1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 916 | |
| 917 | for (i = 0; i < size; i++) { |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 918 | if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) |
| 919 | return -EIO; |
| 920 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 921 | adapter->pci_mem_write(adapter, memaddr, &data, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 922 | flashaddr += 4; |
| 923 | memaddr += 4; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 924 | cond_resched(); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 925 | } |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 926 | msleep(1); |
| 927 | |
| 928 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
| 929 | adapter->pci_write_normalize(adapter, |
| 930 | NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); |
| 931 | else { |
| 932 | adapter->pci_write_normalize(adapter, |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 933 | NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 934 | adapter->pci_write_normalize(adapter, |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 935 | NETXEN_ROMUSB_GLB_CAS_RST, 0); |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 936 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 937 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 938 | return 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 939 | } |
| 940 | |
| 941 | int |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 942 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, |
| 943 | ulong off, void *data, int len) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 944 | { |
| 945 | void __iomem *addr; |
| 946 | |
| 947 | if (ADDR_IN_WINDOW1(off)) { |
| 948 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 949 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 950 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 951 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 952 | } |
| 953 | |
| 954 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p" |
| 955 | " data %llx len %d\n", |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 956 | pci_base(adapter, off), off, addr, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 957 | *(unsigned long long *)data, len); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 958 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 959 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 960 | return 1; |
| 961 | } |
| 962 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 963 | switch (len) { |
| 964 | case 1: |
| 965 | writeb(*(u8 *) data, addr); |
| 966 | break; |
| 967 | case 2: |
| 968 | writew(*(u16 *) data, addr); |
| 969 | break; |
| 970 | case 4: |
| 971 | writel(*(u32 *) data, addr); |
| 972 | break; |
| 973 | case 8: |
| 974 | writeq(*(u64 *) data, addr); |
| 975 | break; |
| 976 | default: |
| 977 | DPRINTK(INFO, |
| 978 | "writing data %lx to offset %llx, num words=%d\n", |
| 979 | *(unsigned long *)data, off, (len >> 3)); |
| 980 | |
| 981 | netxen_nic_hw_block_write64((u64 __iomem *) data, addr, |
| 982 | (len >> 3)); |
| 983 | break; |
| 984 | } |
| 985 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 986 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 987 | |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | int |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 992 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, |
| 993 | ulong off, void *data, int len) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 994 | { |
| 995 | void __iomem *addr; |
| 996 | |
| 997 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
| 998 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 999 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1000 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1001 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1002 | } |
| 1003 | |
| 1004 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1005 | pci_base(adapter, off), off, addr); |
| 1006 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1007 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1008 | return 1; |
| 1009 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1010 | switch (len) { |
| 1011 | case 1: |
| 1012 | *(u8 *) data = readb(addr); |
| 1013 | break; |
| 1014 | case 2: |
| 1015 | *(u16 *) data = readw(addr); |
| 1016 | break; |
| 1017 | case 4: |
| 1018 | *(u32 *) data = readl(addr); |
| 1019 | break; |
| 1020 | case 8: |
| 1021 | *(u64 *) data = readq(addr); |
| 1022 | break; |
| 1023 | default: |
| 1024 | netxen_nic_hw_block_read64((u64 __iomem *) data, addr, |
| 1025 | (len >> 3)); |
| 1026 | break; |
| 1027 | } |
| 1028 | DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); |
| 1029 | |
| 1030 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1031 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1032 | |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
| 1036 | int |
| 1037 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, |
| 1038 | ulong off, void *data, int len) |
| 1039 | { |
| 1040 | unsigned long flags = 0; |
| 1041 | int rv; |
| 1042 | |
| 1043 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); |
| 1044 | |
| 1045 | if (rv == -1) { |
| 1046 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1047 | __func__, off); |
| 1048 | dump_stack(); |
| 1049 | return -1; |
| 1050 | } |
| 1051 | |
| 1052 | if (rv == 1) { |
| 1053 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1054 | crb_win_lock(adapter); |
| 1055 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
| 1056 | } |
| 1057 | |
| 1058 | DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n", |
| 1059 | *(unsigned long *)data, off, len); |
| 1060 | |
| 1061 | switch (len) { |
| 1062 | case 1: |
| 1063 | writeb(*(uint8_t *)data, (void *)off); |
| 1064 | break; |
| 1065 | case 2: |
| 1066 | writew(*(uint16_t *)data, (void *)off); |
| 1067 | break; |
| 1068 | case 4: |
| 1069 | writel(*(uint32_t *)data, (void *)off); |
| 1070 | break; |
| 1071 | case 8: |
| 1072 | writeq(*(uint64_t *)data, (void *)off); |
| 1073 | break; |
| 1074 | default: |
| 1075 | DPRINTK(1, INFO, |
| 1076 | "writing data %lx to offset %llx, num words=%d\n", |
| 1077 | *(unsigned long *)data, off, (len>>3)); |
| 1078 | break; |
| 1079 | } |
| 1080 | if (rv == 1) { |
| 1081 | crb_win_unlock(adapter); |
| 1082 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1083 | } |
| 1084 | |
| 1085 | return 0; |
| 1086 | } |
| 1087 | |
| 1088 | int |
| 1089 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, |
| 1090 | ulong off, void *data, int len) |
| 1091 | { |
| 1092 | unsigned long flags = 0; |
| 1093 | int rv; |
| 1094 | |
| 1095 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); |
| 1096 | |
| 1097 | if (rv == -1) { |
| 1098 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1099 | __func__, off); |
| 1100 | dump_stack(); |
| 1101 | return -1; |
| 1102 | } |
| 1103 | |
| 1104 | if (rv == 1) { |
| 1105 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1106 | crb_win_lock(adapter); |
| 1107 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
| 1108 | } |
| 1109 | |
| 1110 | DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len); |
| 1111 | |
| 1112 | switch (len) { |
| 1113 | case 1: |
| 1114 | *(uint8_t *)data = readb((void *)off); |
| 1115 | break; |
| 1116 | case 2: |
| 1117 | *(uint16_t *)data = readw((void *)off); |
| 1118 | break; |
| 1119 | case 4: |
| 1120 | *(uint32_t *)data = readl((void *)off); |
| 1121 | break; |
| 1122 | case 8: |
| 1123 | *(uint64_t *)data = readq((void *)off); |
| 1124 | break; |
| 1125 | default: |
| 1126 | break; |
| 1127 | } |
| 1128 | |
| 1129 | DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data); |
| 1130 | |
| 1131 | if (rv == 1) { |
| 1132 | crb_win_unlock(adapter); |
| 1133 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1134 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1135 | |
| 1136 | return 0; |
| 1137 | } |
| 1138 | |
| 1139 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1140 | { |
| 1141 | adapter->hw_write_wx(adapter, off, &val, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1142 | } |
| 1143 | |
| 1144 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1145 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1146 | int val; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1147 | adapter->hw_read_wx(adapter, off, &val, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1148 | return val; |
| 1149 | } |
| 1150 | |
| 1151 | /* Change the window to 0, write and change back to window 1. */ |
| 1152 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) |
| 1153 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1154 | adapter->hw_write_wx(adapter, index, &value, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1155 | } |
| 1156 | |
| 1157 | /* Change the window to 0, read and change back to window 1. */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1158 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1159 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1160 | adapter->hw_read_wx(adapter, index, value, 4); |
| 1161 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1162 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1163 | void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value) |
| 1164 | { |
| 1165 | adapter->hw_write_wx(adapter, index, &value, 4); |
| 1166 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1167 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1168 | void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value) |
| 1169 | { |
| 1170 | adapter->hw_read_wx(adapter, index, value, 4); |
| 1171 | } |
| 1172 | |
| 1173 | /* |
| 1174 | * check memory access boundary. |
| 1175 | * used by test agent. support ddr access only for now |
| 1176 | */ |
| 1177 | static unsigned long |
| 1178 | netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter, |
| 1179 | unsigned long long addr, int size) |
| 1180 | { |
| 1181 | if (!ADDR_IN_RANGE(addr, |
| 1182 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1183 | !ADDR_IN_RANGE(addr+size-1, |
| 1184 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1185 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
| 1186 | return 0; |
| 1187 | } |
| 1188 | |
| 1189 | return 1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1190 | } |
| 1191 | |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1192 | static int netxen_pci_set_window_warning_count; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1193 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1194 | unsigned long |
| 1195 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, |
| 1196 | unsigned long long addr) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1197 | { |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1198 | void __iomem *offset; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1199 | int window; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1200 | unsigned long long qdr_max; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1201 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1202 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1203 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
| 1204 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1205 | } else { |
| 1206 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1207 | } |
| 1208 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1209 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1210 | /* DDR network side */ |
| 1211 | addr -= NETXEN_ADDR_DDR_NET; |
| 1212 | window = (addr >> 25) & 0x3ff; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1213 | if (adapter->ahw.ddr_mn_window != window) { |
| 1214 | adapter->ahw.ddr_mn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1215 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1216 | NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func))); |
| 1217 | writel(window, offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1218 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1219 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1220 | } |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1221 | addr -= (window * NETXEN_WINDOW_ONE); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1222 | addr += NETXEN_PCI_DDR_NET; |
| 1223 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1224 | addr -= NETXEN_ADDR_OCM0; |
| 1225 | addr += NETXEN_PCI_OCM0; |
| 1226 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1227 | addr -= NETXEN_ADDR_OCM1; |
| 1228 | addr += NETXEN_PCI_OCM1; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1229 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1230 | /* QDR network side */ |
| 1231 | addr -= NETXEN_ADDR_QDR_NET; |
| 1232 | window = (addr >> 22) & 0x3f; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1233 | if (adapter->ahw.qdr_sn_window != window) { |
| 1234 | adapter->ahw.qdr_sn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1235 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1236 | NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func))); |
| 1237 | writel((window << 22), offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1238 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1239 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1240 | } |
| 1241 | addr -= (window * 0x400000); |
| 1242 | addr += NETXEN_PCI_QDR_NET; |
| 1243 | } else { |
| 1244 | /* |
| 1245 | * peg gdb frequently accesses memory that doesn't exist, |
| 1246 | * this limits the chit chat so debugging isn't slowed down. |
| 1247 | */ |
| 1248 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1249 | || (netxen_pci_set_window_warning_count % 64 == 0)) |
| 1250 | printk("%s: Warning:netxen_nic_pci_set_window()" |
| 1251 | " Unknown address range!\n", |
| 1252 | netxen_nic_driver_name); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1253 | addr = -1UL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1254 | } |
| 1255 | return addr; |
| 1256 | } |
| 1257 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1258 | /* |
| 1259 | * Note : only 32-bit writes! |
| 1260 | */ |
| 1261 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, |
| 1262 | u64 off, u32 data) |
| 1263 | { |
| 1264 | writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off))); |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off) |
| 1269 | { |
| 1270 | return readl((void __iomem *)(pci_base_offset(adapter, off))); |
| 1271 | } |
| 1272 | |
| 1273 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, |
| 1274 | u64 off, u32 data) |
| 1275 | { |
| 1276 | writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); |
| 1277 | } |
| 1278 | |
| 1279 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off) |
| 1280 | { |
| 1281 | return readl(NETXEN_CRB_NORMALIZE(adapter, off)); |
| 1282 | } |
| 1283 | |
| 1284 | unsigned long |
| 1285 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, |
| 1286 | unsigned long long addr) |
| 1287 | { |
| 1288 | int window; |
| 1289 | u32 win_read; |
| 1290 | |
| 1291 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1292 | /* DDR network side */ |
| 1293 | window = MN_WIN(addr); |
| 1294 | adapter->ahw.ddr_mn_window = window; |
| 1295 | adapter->hw_write_wx(adapter, |
| 1296 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1297 | &window, 4); |
| 1298 | adapter->hw_read_wx(adapter, |
| 1299 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1300 | &win_read, 4); |
| 1301 | if ((win_read << 17) != window) { |
| 1302 | printk(KERN_INFO "Written MNwin (0x%x) != " |
| 1303 | "Read MNwin (0x%x)\n", window, win_read); |
| 1304 | } |
| 1305 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET; |
| 1306 | } else if (ADDR_IN_RANGE(addr, |
| 1307 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1308 | if ((addr & 0x00ff800) == 0xff800) { |
| 1309 | printk("%s: QM access not handled.\n", __func__); |
| 1310 | addr = -1UL; |
| 1311 | } |
| 1312 | |
| 1313 | window = OCM_WIN(addr); |
| 1314 | adapter->ahw.ddr_mn_window = window; |
| 1315 | adapter->hw_write_wx(adapter, |
| 1316 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1317 | &window, 4); |
| 1318 | adapter->hw_read_wx(adapter, |
| 1319 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1320 | &win_read, 4); |
| 1321 | if ((win_read >> 7) != window) { |
| 1322 | printk(KERN_INFO "%s: Written OCMwin (0x%x) != " |
| 1323 | "Read OCMwin (0x%x)\n", |
| 1324 | __func__, window, win_read); |
| 1325 | } |
| 1326 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M; |
| 1327 | |
| 1328 | } else if (ADDR_IN_RANGE(addr, |
| 1329 | NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) { |
| 1330 | /* QDR network side */ |
| 1331 | window = MS_WIN(addr); |
| 1332 | adapter->ahw.qdr_sn_window = window; |
| 1333 | adapter->hw_write_wx(adapter, |
| 1334 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, |
| 1335 | &window, 4); |
| 1336 | adapter->hw_read_wx(adapter, |
| 1337 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, |
| 1338 | &win_read, 4); |
| 1339 | if (win_read != window) { |
| 1340 | printk(KERN_INFO "%s: Written MSwin (0x%x) != " |
| 1341 | "Read MSwin (0x%x)\n", |
| 1342 | __func__, window, win_read); |
| 1343 | } |
| 1344 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET; |
| 1345 | |
| 1346 | } else { |
| 1347 | /* |
| 1348 | * peg gdb frequently accesses memory that doesn't exist, |
| 1349 | * this limits the chit chat so debugging isn't slowed down. |
| 1350 | */ |
| 1351 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1352 | || (netxen_pci_set_window_warning_count%64 == 0)) { |
| 1353 | printk("%s: Warning:%s Unknown address range!\n", |
| 1354 | __func__, netxen_nic_driver_name); |
| 1355 | } |
| 1356 | addr = -1UL; |
| 1357 | } |
| 1358 | return addr; |
| 1359 | } |
| 1360 | |
| 1361 | static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter, |
| 1362 | unsigned long long addr) |
| 1363 | { |
| 1364 | int window; |
| 1365 | unsigned long long qdr_max; |
| 1366 | |
| 1367 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 1368 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1369 | else |
| 1370 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1371 | |
| 1372 | if (ADDR_IN_RANGE(addr, |
| 1373 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1374 | /* DDR network side */ |
| 1375 | BUG(); /* MN access can not come here */ |
| 1376 | } else if (ADDR_IN_RANGE(addr, |
| 1377 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1378 | return 1; |
| 1379 | } else if (ADDR_IN_RANGE(addr, |
| 1380 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1381 | return 1; |
| 1382 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
| 1383 | /* QDR network side */ |
| 1384 | window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f; |
| 1385 | if (adapter->ahw.qdr_sn_window == window) |
| 1386 | return 1; |
| 1387 | } |
| 1388 | |
| 1389 | return 0; |
| 1390 | } |
| 1391 | |
| 1392 | static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, |
| 1393 | u64 off, void *data, int size) |
| 1394 | { |
| 1395 | unsigned long flags; |
| 1396 | void *addr; |
| 1397 | int ret = 0; |
| 1398 | u64 start; |
| 1399 | uint8_t *mem_ptr = NULL; |
| 1400 | unsigned long mem_base; |
| 1401 | unsigned long mem_page; |
| 1402 | |
| 1403 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1404 | |
| 1405 | /* |
| 1406 | * If attempting to access unknown address or straddle hw windows, |
| 1407 | * do not access. |
| 1408 | */ |
| 1409 | start = adapter->pci_set_window(adapter, off); |
| 1410 | if ((start == -1UL) || |
| 1411 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1412 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1413 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1414 | "offset is 0x%llx\n", netxen_nic_driver_name, off); |
| 1415 | return -1; |
| 1416 | } |
| 1417 | |
| 1418 | addr = (void *)(pci_base_offset(adapter, start)); |
| 1419 | if (!addr) { |
| 1420 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1421 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1422 | mem_page = start & PAGE_MASK; |
| 1423 | /* Map two pages whenever user tries to access addresses in two |
| 1424 | consecutive pages. |
| 1425 | */ |
| 1426 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1427 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); |
| 1428 | else |
| 1429 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 1430 | if (mem_ptr == 0UL) { |
| 1431 | *(uint8_t *)data = 0; |
| 1432 | return -1; |
| 1433 | } |
| 1434 | addr = mem_ptr; |
| 1435 | addr += start & (PAGE_SIZE - 1); |
| 1436 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1437 | } |
| 1438 | |
| 1439 | switch (size) { |
| 1440 | case 1: |
| 1441 | *(uint8_t *)data = readb(addr); |
| 1442 | break; |
| 1443 | case 2: |
| 1444 | *(uint16_t *)data = readw(addr); |
| 1445 | break; |
| 1446 | case 4: |
| 1447 | *(uint32_t *)data = readl(addr); |
| 1448 | break; |
| 1449 | case 8: |
| 1450 | *(uint64_t *)data = readq(addr); |
| 1451 | break; |
| 1452 | default: |
| 1453 | ret = -1; |
| 1454 | break; |
| 1455 | } |
| 1456 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1457 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 1458 | |
| 1459 | if (mem_ptr) |
| 1460 | iounmap(mem_ptr); |
| 1461 | return ret; |
| 1462 | } |
| 1463 | |
| 1464 | static int |
| 1465 | netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, |
| 1466 | void *data, int size) |
| 1467 | { |
| 1468 | unsigned long flags; |
| 1469 | void *addr; |
| 1470 | int ret = 0; |
| 1471 | u64 start; |
| 1472 | uint8_t *mem_ptr = NULL; |
| 1473 | unsigned long mem_base; |
| 1474 | unsigned long mem_page; |
| 1475 | |
| 1476 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1477 | |
| 1478 | /* |
| 1479 | * If attempting to access unknown address or straddle hw windows, |
| 1480 | * do not access. |
| 1481 | */ |
| 1482 | start = adapter->pci_set_window(adapter, off); |
| 1483 | if ((start == -1UL) || |
| 1484 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1485 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1486 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1487 | "offset is 0x%llx\n", netxen_nic_driver_name, off); |
| 1488 | return -1; |
| 1489 | } |
| 1490 | |
| 1491 | addr = (void *)(pci_base_offset(adapter, start)); |
| 1492 | if (!addr) { |
| 1493 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1494 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1495 | mem_page = start & PAGE_MASK; |
| 1496 | /* Map two pages whenever user tries to access addresses in two |
| 1497 | * consecutive pages. |
| 1498 | */ |
| 1499 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1500 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); |
| 1501 | else |
| 1502 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 1503 | if (mem_ptr == 0UL) |
| 1504 | return -1; |
| 1505 | addr = mem_ptr; |
| 1506 | addr += start & (PAGE_SIZE - 1); |
| 1507 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1508 | } |
| 1509 | |
| 1510 | switch (size) { |
| 1511 | case 1: |
| 1512 | writeb(*(uint8_t *)data, addr); |
| 1513 | break; |
| 1514 | case 2: |
| 1515 | writew(*(uint16_t *)data, addr); |
| 1516 | break; |
| 1517 | case 4: |
| 1518 | writel(*(uint32_t *)data, addr); |
| 1519 | break; |
| 1520 | case 8: |
| 1521 | writeq(*(uint64_t *)data, addr); |
| 1522 | break; |
| 1523 | default: |
| 1524 | ret = -1; |
| 1525 | break; |
| 1526 | } |
| 1527 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1528 | DPRINTK(1, INFO, "writing data %llx to offset %llx\n", |
| 1529 | *(unsigned long long *)data, start); |
| 1530 | if (mem_ptr) |
| 1531 | iounmap(mem_ptr); |
| 1532 | return ret; |
| 1533 | } |
| 1534 | |
| 1535 | #define MAX_CTL_CHECK 1000 |
| 1536 | |
| 1537 | int |
| 1538 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
| 1539 | u64 off, void *data, int size) |
| 1540 | { |
| 1541 | unsigned long flags, mem_crb; |
| 1542 | int i, j, ret = 0, loop, sz[2], off0; |
| 1543 | uint32_t temp; |
| 1544 | uint64_t off8, tmpw, word[2] = {0, 0}; |
| 1545 | |
| 1546 | /* |
| 1547 | * If not MN, go check for MS or invalid. |
| 1548 | */ |
| 1549 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1550 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1551 | off, data, size); |
| 1552 | |
| 1553 | off8 = off & 0xfffffff8; |
| 1554 | off0 = off & 0x7; |
| 1555 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1556 | sz[1] = size - sz[0]; |
| 1557 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1558 | mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
| 1559 | |
| 1560 | if ((size != 8) || (off0 != 0)) { |
| 1561 | for (i = 0; i < loop; i++) { |
| 1562 | if (adapter->pci_mem_read(adapter, |
| 1563 | off8 + (i << 3), &word[i], 8)) |
| 1564 | return -1; |
| 1565 | } |
| 1566 | } |
| 1567 | |
| 1568 | switch (size) { |
| 1569 | case 1: |
| 1570 | tmpw = *((uint8_t *)data); |
| 1571 | break; |
| 1572 | case 2: |
| 1573 | tmpw = *((uint16_t *)data); |
| 1574 | break; |
| 1575 | case 4: |
| 1576 | tmpw = *((uint32_t *)data); |
| 1577 | break; |
| 1578 | case 8: |
| 1579 | default: |
| 1580 | tmpw = *((uint64_t *)data); |
| 1581 | break; |
| 1582 | } |
| 1583 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1584 | word[0] |= tmpw << (off0 * 8); |
| 1585 | |
| 1586 | if (loop == 2) { |
| 1587 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1588 | word[1] |= tmpw >> (sz[0] * 8); |
| 1589 | } |
| 1590 | |
| 1591 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1592 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1593 | |
| 1594 | for (i = 0; i < loop; i++) { |
| 1595 | writel((uint32_t)(off8 + (i << 3)), |
| 1596 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); |
| 1597 | writel(0, |
| 1598 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); |
| 1599 | writel(word[i] & 0xffffffff, |
| 1600 | (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO)); |
| 1601 | writel((word[i] >> 32) & 0xffffffff, |
| 1602 | (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI)); |
| 1603 | writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
| 1604 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1605 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
| 1606 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1607 | |
| 1608 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1609 | temp = readl( |
| 1610 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1611 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1612 | break; |
| 1613 | } |
| 1614 | |
| 1615 | if (j >= MAX_CTL_CHECK) { |
| 1616 | printk("%s: %s Fail to write through agent\n", |
| 1617 | __func__, netxen_nic_driver_name); |
| 1618 | ret = -1; |
| 1619 | break; |
| 1620 | } |
| 1621 | } |
| 1622 | |
| 1623 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1624 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1625 | return ret; |
| 1626 | } |
| 1627 | |
| 1628 | int |
| 1629 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
| 1630 | u64 off, void *data, int size) |
| 1631 | { |
| 1632 | unsigned long flags, mem_crb; |
| 1633 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1634 | uint32_t temp; |
| 1635 | uint64_t off8, val, word[2] = {0, 0}; |
| 1636 | |
| 1637 | |
| 1638 | /* |
| 1639 | * If not MN, go check for MS or invalid. |
| 1640 | */ |
| 1641 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1642 | return netxen_nic_pci_mem_read_direct(adapter, off, data, size); |
| 1643 | |
| 1644 | off8 = off & 0xfffffff8; |
| 1645 | off0[0] = off & 0x7; |
| 1646 | off0[1] = 0; |
| 1647 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1648 | sz[1] = size - sz[0]; |
| 1649 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1650 | mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
| 1651 | |
| 1652 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1653 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1654 | |
| 1655 | for (i = 0; i < loop; i++) { |
| 1656 | writel((uint32_t)(off8 + (i << 3)), |
| 1657 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); |
| 1658 | writel(0, |
| 1659 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); |
| 1660 | writel(MIU_TA_CTL_ENABLE, |
| 1661 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1662 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE, |
| 1663 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1664 | |
| 1665 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1666 | temp = readl( |
| 1667 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1668 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1669 | break; |
| 1670 | } |
| 1671 | |
| 1672 | if (j >= MAX_CTL_CHECK) { |
| 1673 | printk(KERN_ERR "%s: %s Fail to read through agent\n", |
| 1674 | __func__, netxen_nic_driver_name); |
| 1675 | break; |
| 1676 | } |
| 1677 | |
| 1678 | start = off0[i] >> 2; |
| 1679 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1680 | for (k = start; k <= end; k++) { |
| 1681 | word[i] |= ((uint64_t) readl( |
| 1682 | (void *)(mem_crb + |
| 1683 | MIU_TEST_AGT_RDDATA(k))) << (32*k)); |
| 1684 | } |
| 1685 | } |
| 1686 | |
| 1687 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1688 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1689 | |
| 1690 | if (j >= MAX_CTL_CHECK) |
| 1691 | return -1; |
| 1692 | |
| 1693 | if (sz[0] == 8) { |
| 1694 | val = word[0]; |
| 1695 | } else { |
| 1696 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1697 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1698 | } |
| 1699 | |
| 1700 | switch (size) { |
| 1701 | case 1: |
| 1702 | *(uint8_t *)data = val; |
| 1703 | break; |
| 1704 | case 2: |
| 1705 | *(uint16_t *)data = val; |
| 1706 | break; |
| 1707 | case 4: |
| 1708 | *(uint32_t *)data = val; |
| 1709 | break; |
| 1710 | case 8: |
| 1711 | *(uint64_t *)data = val; |
| 1712 | break; |
| 1713 | } |
| 1714 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 1715 | return 0; |
| 1716 | } |
| 1717 | |
| 1718 | int |
| 1719 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
| 1720 | u64 off, void *data, int size) |
| 1721 | { |
| 1722 | int i, j, ret = 0, loop, sz[2], off0; |
| 1723 | uint32_t temp; |
| 1724 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; |
| 1725 | |
| 1726 | /* |
| 1727 | * If not MN, go check for MS or invalid. |
| 1728 | */ |
| 1729 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1730 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1731 | else { |
| 1732 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1733 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1734 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1735 | off, data, size); |
| 1736 | } |
| 1737 | |
| 1738 | off8 = off & 0xfffffff8; |
| 1739 | off0 = off & 0x7; |
| 1740 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1741 | sz[1] = size - sz[0]; |
| 1742 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1743 | |
| 1744 | if ((size != 8) || (off0 != 0)) { |
| 1745 | for (i = 0; i < loop; i++) { |
| 1746 | if (adapter->pci_mem_read(adapter, off8 + (i << 3), |
| 1747 | &word[i], 8)) |
| 1748 | return -1; |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | switch (size) { |
| 1753 | case 1: |
| 1754 | tmpw = *((uint8_t *)data); |
| 1755 | break; |
| 1756 | case 2: |
| 1757 | tmpw = *((uint16_t *)data); |
| 1758 | break; |
| 1759 | case 4: |
| 1760 | tmpw = *((uint32_t *)data); |
| 1761 | break; |
| 1762 | case 8: |
| 1763 | default: |
| 1764 | tmpw = *((uint64_t *)data); |
| 1765 | break; |
| 1766 | } |
| 1767 | |
| 1768 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1769 | word[0] |= tmpw << (off0 * 8); |
| 1770 | |
| 1771 | if (loop == 2) { |
| 1772 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1773 | word[1] |= tmpw >> (sz[0] * 8); |
| 1774 | } |
| 1775 | |
| 1776 | /* |
| 1777 | * don't lock here - write_wx gets the lock if each time |
| 1778 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1779 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1780 | */ |
| 1781 | |
| 1782 | for (i = 0; i < loop; i++) { |
| 1783 | temp = off8 + (i << 3); |
| 1784 | adapter->hw_write_wx(adapter, |
| 1785 | mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4); |
| 1786 | temp = 0; |
| 1787 | adapter->hw_write_wx(adapter, |
| 1788 | mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4); |
| 1789 | temp = word[i] & 0xffffffff; |
| 1790 | adapter->hw_write_wx(adapter, |
| 1791 | mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4); |
| 1792 | temp = (word[i] >> 32) & 0xffffffff; |
| 1793 | adapter->hw_write_wx(adapter, |
| 1794 | mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4); |
| 1795 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
| 1796 | adapter->hw_write_wx(adapter, |
| 1797 | mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); |
| 1798 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
| 1799 | adapter->hw_write_wx(adapter, |
| 1800 | mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); |
| 1801 | |
| 1802 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1803 | adapter->hw_read_wx(adapter, |
| 1804 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1805 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1806 | break; |
| 1807 | } |
| 1808 | |
| 1809 | if (j >= MAX_CTL_CHECK) { |
| 1810 | printk(KERN_ERR "%s: Fail to write through agent\n", |
| 1811 | netxen_nic_driver_name); |
| 1812 | ret = -1; |
| 1813 | break; |
| 1814 | } |
| 1815 | } |
| 1816 | |
| 1817 | /* |
| 1818 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1819 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1820 | */ |
| 1821 | return ret; |
| 1822 | } |
| 1823 | |
| 1824 | int |
| 1825 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
| 1826 | u64 off, void *data, int size) |
| 1827 | { |
| 1828 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1829 | uint32_t temp; |
| 1830 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; |
| 1831 | |
| 1832 | /* |
| 1833 | * If not MN, go check for MS or invalid. |
| 1834 | */ |
| 1835 | |
| 1836 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1837 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1838 | else { |
| 1839 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1840 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1841 | return netxen_nic_pci_mem_read_direct(adapter, |
| 1842 | off, data, size); |
| 1843 | } |
| 1844 | |
| 1845 | off8 = off & 0xfffffff8; |
| 1846 | off0[0] = off & 0x7; |
| 1847 | off0[1] = 0; |
| 1848 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1849 | sz[1] = size - sz[0]; |
| 1850 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1851 | |
| 1852 | /* |
| 1853 | * don't lock here - write_wx gets the lock if each time |
| 1854 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1855 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1856 | */ |
| 1857 | |
| 1858 | for (i = 0; i < loop; i++) { |
| 1859 | temp = off8 + (i << 3); |
| 1860 | adapter->hw_write_wx(adapter, |
| 1861 | mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4); |
| 1862 | temp = 0; |
| 1863 | adapter->hw_write_wx(adapter, |
| 1864 | mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4); |
| 1865 | temp = MIU_TA_CTL_ENABLE; |
| 1866 | adapter->hw_write_wx(adapter, |
| 1867 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1868 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; |
| 1869 | adapter->hw_write_wx(adapter, |
| 1870 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1871 | |
| 1872 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1873 | adapter->hw_read_wx(adapter, |
| 1874 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1875 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1876 | break; |
| 1877 | } |
| 1878 | |
| 1879 | if (j >= MAX_CTL_CHECK) { |
| 1880 | printk(KERN_ERR "%s: Fail to read through agent\n", |
| 1881 | netxen_nic_driver_name); |
| 1882 | break; |
| 1883 | } |
| 1884 | |
| 1885 | start = off0[i] >> 2; |
| 1886 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1887 | for (k = start; k <= end; k++) { |
| 1888 | adapter->hw_read_wx(adapter, |
| 1889 | mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4); |
| 1890 | word[i] |= ((uint64_t)temp << (32 * k)); |
| 1891 | } |
| 1892 | } |
| 1893 | |
| 1894 | /* |
| 1895 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1896 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1897 | */ |
| 1898 | |
| 1899 | if (j >= MAX_CTL_CHECK) |
| 1900 | return -1; |
| 1901 | |
| 1902 | if (sz[0] == 8) { |
| 1903 | val = word[0]; |
| 1904 | } else { |
| 1905 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1906 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1907 | } |
| 1908 | |
| 1909 | switch (size) { |
| 1910 | case 1: |
| 1911 | *(uint8_t *)data = val; |
| 1912 | break; |
| 1913 | case 2: |
| 1914 | *(uint16_t *)data = val; |
| 1915 | break; |
| 1916 | case 4: |
| 1917 | *(uint32_t *)data = val; |
| 1918 | break; |
| 1919 | case 8: |
| 1920 | *(uint64_t *)data = val; |
| 1921 | break; |
| 1922 | } |
| 1923 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 1924 | return 0; |
| 1925 | } |
| 1926 | |
| 1927 | /* |
| 1928 | * Note : only 32-bit writes! |
| 1929 | */ |
| 1930 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
| 1931 | u64 off, u32 data) |
| 1932 | { |
| 1933 | adapter->hw_write_wx(adapter, off, &data, 4); |
| 1934 | |
| 1935 | return 0; |
| 1936 | } |
| 1937 | |
| 1938 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) |
| 1939 | { |
| 1940 | u32 temp; |
| 1941 | adapter->hw_read_wx(adapter, off, &temp, 4); |
| 1942 | return temp; |
| 1943 | } |
| 1944 | |
| 1945 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, |
| 1946 | u64 off, u32 data) |
| 1947 | { |
| 1948 | adapter->hw_write_wx(adapter, off, &data, 4); |
| 1949 | } |
| 1950 | |
| 1951 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off) |
| 1952 | { |
| 1953 | u32 temp; |
| 1954 | adapter->hw_read_wx(adapter, off, &temp, 4); |
| 1955 | return temp; |
| 1956 | } |
| 1957 | |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 1958 | #if 0 |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1959 | int |
| 1960 | netxen_nic_erase_pxe(struct netxen_adapter *adapter) |
| 1961 | { |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 1962 | if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) { |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1963 | printk(KERN_ERR "%s: erase pxe failed\n", |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1964 | netxen_nic_driver_name); |
| 1965 | return -1; |
| 1966 | } |
| 1967 | return 0; |
| 1968 | } |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 1969 | #endif /* 0 */ |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 1970 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1971 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
| 1972 | { |
| 1973 | int rv = 0; |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 1974 | int addr = NETXEN_BRDCFG_START; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1975 | struct netxen_board_info *boardinfo; |
| 1976 | int index; |
| 1977 | u32 *ptr32; |
| 1978 | |
| 1979 | boardinfo = &adapter->ahw.boardcfg; |
| 1980 | ptr32 = (u32 *) boardinfo; |
| 1981 | |
| 1982 | for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); |
| 1983 | index++) { |
| 1984 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { |
| 1985 | return -EIO; |
| 1986 | } |
| 1987 | ptr32++; |
| 1988 | addr += sizeof(u32); |
| 1989 | } |
| 1990 | if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { |
| 1991 | printk("%s: ERROR reading %s board config." |
| 1992 | " Read %x, expected %x\n", netxen_nic_driver_name, |
| 1993 | netxen_nic_driver_name, |
| 1994 | boardinfo->magic, NETXEN_BDINFO_MAGIC); |
| 1995 | rv = -1; |
| 1996 | } |
| 1997 | if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { |
| 1998 | printk("%s: Unknown board config version." |
| 1999 | " Read %x, expected %x\n", netxen_nic_driver_name, |
| 2000 | boardinfo->header_version, NETXEN_BDINFO_VERSION); |
| 2001 | rv = -1; |
| 2002 | } |
| 2003 | |
| 2004 | DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type); |
| 2005 | switch ((netxen_brdtype_t) boardinfo->board_type) { |
| 2006 | case NETXEN_BRDTYPE_P2_SB35_4G: |
| 2007 | adapter->ahw.board_type = NETXEN_NIC_GBE; |
| 2008 | break; |
| 2009 | case NETXEN_BRDTYPE_P2_SB31_10G: |
| 2010 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: |
| 2011 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: |
| 2012 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 2013 | case NETXEN_BRDTYPE_P3_HMEZ: |
| 2014 | case NETXEN_BRDTYPE_P3_XG_LOM: |
| 2015 | case NETXEN_BRDTYPE_P3_10G_CX4: |
| 2016 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: |
| 2017 | case NETXEN_BRDTYPE_P3_IMEZ: |
| 2018 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
| 2019 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 2020 | case NETXEN_BRDTYPE_P3_10000_BASE_T: |
| 2021 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2022 | adapter->ahw.board_type = NETXEN_NIC_XGBE; |
| 2023 | break; |
| 2024 | case NETXEN_BRDTYPE_P1_BD: |
| 2025 | case NETXEN_BRDTYPE_P1_SB: |
| 2026 | case NETXEN_BRDTYPE_P1_SMAX: |
| 2027 | case NETXEN_BRDTYPE_P1_SOCK: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 2028 | case NETXEN_BRDTYPE_P3_REF_QG: |
| 2029 | case NETXEN_BRDTYPE_P3_4_GB: |
| 2030 | case NETXEN_BRDTYPE_P3_4_GB_MM: |
| 2031 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2032 | adapter->ahw.board_type = NETXEN_NIC_GBE; |
| 2033 | break; |
| 2034 | default: |
| 2035 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, |
| 2036 | boardinfo->board_type); |
| 2037 | break; |
| 2038 | } |
| 2039 | |
| 2040 | return rv; |
| 2041 | } |
| 2042 | |
| 2043 | /* NIU access sections */ |
| 2044 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2045 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2046 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2047 | netxen_nic_write_w0(adapter, |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 2048 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
| 2049 | new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2050 | return 0; |
| 2051 | } |
| 2052 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2053 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2054 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2055 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 2056 | if (adapter->physical_port == 0) |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 2057 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 2058 | new_mtu); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 2059 | else |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 2060 | netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, |
| 2061 | new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2062 | return 0; |
| 2063 | } |
| 2064 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2065 | void |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 2066 | netxen_crb_writelit_adapter(struct netxen_adapter *adapter, |
| 2067 | unsigned long off, int data) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2068 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 2069 | adapter->hw_write_wx(adapter, off, &data, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2070 | } |
| 2071 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2072 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2073 | { |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 2074 | __u32 status; |
| 2075 | __u32 autoneg; |
| 2076 | __u32 mode; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2077 | |
| 2078 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); |
| 2079 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 2080 | if (adapter->phy_read |
| 2081 | && adapter-> |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2082 | phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2083 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
| 2084 | &status) == 0) { |
| 2085 | if (netxen_get_phy_link(status)) { |
| 2086 | switch (netxen_get_phy_speed(status)) { |
| 2087 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2088 | adapter->link_speed = SPEED_10; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2089 | break; |
| 2090 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2091 | adapter->link_speed = SPEED_100; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2092 | break; |
| 2093 | case 2: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2094 | adapter->link_speed = SPEED_1000; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2095 | break; |
| 2096 | default: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2097 | adapter->link_speed = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2098 | break; |
| 2099 | } |
| 2100 | switch (netxen_get_phy_duplex(status)) { |
| 2101 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2102 | adapter->link_duplex = DUPLEX_HALF; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2103 | break; |
| 2104 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2105 | adapter->link_duplex = DUPLEX_FULL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2106 | break; |
| 2107 | default: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2108 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2109 | break; |
| 2110 | } |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 2111 | if (adapter->phy_read |
| 2112 | && adapter-> |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2113 | phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2114 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 2115 | &autoneg) != 0) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2116 | adapter->link_autoneg = autoneg; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2117 | } else |
| 2118 | goto link_down; |
| 2119 | } else { |
| 2120 | link_down: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2121 | adapter->link_speed = -1; |
| 2122 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2123 | } |
| 2124 | } |
| 2125 | } |
| 2126 | |
| 2127 | void netxen_nic_flash_print(struct netxen_adapter *adapter) |
| 2128 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2129 | u32 fw_major = 0; |
| 2130 | u32 fw_minor = 0; |
| 2131 | u32 fw_build = 0; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 2132 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2133 | char serial_num[32]; |
| 2134 | int i, addr; |
Mithlesh Thukral | 6d1495f | 2007-04-20 07:56:42 -0700 | [diff] [blame] | 2135 | __le32 *ptr32; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2136 | |
| 2137 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2138 | |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2139 | adapter->driver_mismatch = 0; |
| 2140 | |
| 2141 | ptr32 = (u32 *)&serial_num; |
| 2142 | addr = NETXEN_USER_START + |
| 2143 | offsetof(struct netxen_new_user_info, serial_num); |
| 2144 | for (i = 0; i < 8; i++) { |
| 2145 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { |
| 2146 | printk("%s: ERROR reading %s board userarea.\n", |
| 2147 | netxen_nic_driver_name, |
| 2148 | netxen_nic_driver_name); |
| 2149 | adapter->driver_mismatch = 1; |
| 2150 | return; |
| 2151 | } |
| 2152 | ptr32++; |
| 2153 | addr += sizeof(u32); |
| 2154 | } |
| 2155 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 2156 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4); |
| 2157 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4); |
| 2158 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2159 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 2160 | adapter->fw_major = fw_major; |
| 2161 | |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2162 | if (adapter->portnum == 0) { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 2163 | get_brd_name_by_type(board_info->board_type, brd_name); |
| 2164 | |
| 2165 | printk("NetXen %s Board S/N %s Chip id 0x%x\n", |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2166 | brd_name, serial_num, board_info->chip_id); |
| 2167 | printk("NetXen Firmware version %d.%d.%d\n", fw_major, |
| 2168 | fw_minor, fw_build); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2169 | } |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2170 | |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame^] | 2171 | if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) < |
| 2172 | NETXEN_VERSION_CODE(3, 4, 216)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2173 | adapter->driver_mismatch = 1; |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame^] | 2174 | printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n", |
| 2175 | netxen_nic_driver_name, |
| 2176 | fw_major, fw_minor, fw_build); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2177 | return; |
| 2178 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2179 | } |
| 2180 | |