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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053024#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053025#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/of_device.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040028
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/initval.h>
33#include <sound/soc.h>
34
35#include "davinci-pcm.h"
36#include "davinci-mcasp.h"
37
38/*
39 * McASP register definitions
40 */
41#define DAVINCI_MCASP_PID_REG 0x00
42#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44#define DAVINCI_MCASP_PFUNC_REG 0x10
45#define DAVINCI_MCASP_PDIR_REG 0x14
46#define DAVINCI_MCASP_PDOUT_REG 0x18
47#define DAVINCI_MCASP_PDSET_REG 0x1c
48
49#define DAVINCI_MCASP_PDCLR_REG 0x20
50
51#define DAVINCI_MCASP_TLGC_REG 0x30
52#define DAVINCI_MCASP_TLMR_REG 0x34
53
54#define DAVINCI_MCASP_GBLCTL_REG 0x44
55#define DAVINCI_MCASP_AMUTE_REG 0x48
56#define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58#define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60#define DAVINCI_MCASP_GBLCTLR_REG 0x60
61#define DAVINCI_MCASP_RXMASK_REG 0x64
62#define DAVINCI_MCASP_RXFMT_REG 0x68
63#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67#define DAVINCI_MCASP_RXTDM_REG 0x78
68#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70#define DAVINCI_MCASP_RXSTAT_REG 0x80
71#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73#define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76#define DAVINCI_MCASP_TXMASK_REG 0xa4
77#define DAVINCI_MCASP_TXFMT_REG 0xa8
78#define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82#define DAVINCI_MCASP_TXTDM_REG 0xb8
83#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85#define DAVINCI_MCASP_TXSTAT_REG 0xc0
86#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90/* Left(even TDM Slot) Channel Status Register File */
91#define DAVINCI_MCASP_DITCSRA_REG 0x100
92/* Right(odd TDM slot) Channel Status Register File */
93#define DAVINCI_MCASP_DITCSRB_REG 0x118
94/* Left(even TDM slot) User Data Register File */
95#define DAVINCI_MCASP_DITUDRA_REG 0x130
96/* Right(odd TDM Slot) User Data Register File */
97#define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99/* Serializer n Control Register */
100#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104/* Transmit Buffer for Serializer n */
105#define DAVINCI_MCASP_TXBUF_REG 0x200
106/* Receive Buffer for Serializer n */
107#define DAVINCI_MCASP_RXBUF_REG 0x280
108
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400109/* McASP FIFO Registers */
110#define DAVINCI_MCASP_WFIFOCTL (0x1010)
111#define DAVINCI_MCASP_WFIFOSTS (0x1014)
112#define DAVINCI_MCASP_RFIFOCTL (0x1018)
113#define DAVINCI_MCASP_RFIFOSTS (0x101C)
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530114#define MCASP_VER3_WFIFOCTL (0x1000)
115#define MCASP_VER3_WFIFOSTS (0x1004)
116#define MCASP_VER3_RFIFOCTL (0x1008)
117#define MCASP_VER3_RFIFOSTS (0x100C)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400118
119/*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123#define MCASP_FREE BIT(0)
124#define MCASP_SOFT BIT(1)
125
126/*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129#define AXR(n) (1<<n)
130#define PFUNC_AMUTE BIT(25)
131#define ACLKX BIT(26)
132#define AHCLKX BIT(27)
133#define AFSX BIT(28)
134#define ACLKR BIT(29)
135#define AHCLKR BIT(30)
136#define AFSR BIT(31)
137
138/*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141#define AXR(n) (1<<n)
142#define PDIR_AMUTE BIT(25)
143#define ACLKX BIT(26)
144#define AHCLKX BIT(27)
145#define AFSX BIT(28)
146#define ACLKR BIT(29)
147#define AHCLKR BIT(30)
148#define AFSR BIT(31)
149
150/*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154#define VA BIT(2)
155#define VB BIT(3)
156
157/*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160#define TXROT(val) (val)
161#define TXSEL BIT(3)
162#define TXSSZ(val) (val<<4)
163#define TXPBIT(val) (val<<8)
164#define TXPAD(val) (val<<13)
165#define TXORD BIT(15)
166#define FSXDLY(val) (val<<16)
167
168/*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171#define RXROT(val) (val)
172#define RXSEL BIT(3)
173#define RXSSZ(val) (val<<4)
174#define RXPBIT(val) (val<<8)
175#define RXPAD(val) (val<<13)
176#define RXORD BIT(15)
177#define FSRDLY(val) (val<<16)
178
179/*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182#define FSXPOL BIT(0)
183#define AFSXE BIT(1)
184#define FSXDUR BIT(4)
185#define FSXMOD(val) (val<<7)
186
187/*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190#define FSRPOL BIT(0)
191#define AFSRE BIT(1)
192#define FSRDUR BIT(4)
193#define FSRMOD(val) (val<<7)
194
195/*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198#define ACLKXDIV(val) (val)
199#define ACLKXE BIT(5)
200#define TX_ASYNC BIT(6)
201#define ACLKXPOL BIT(7)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200202#define ACLKXDIV_MASK 0x1f
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400203
204/*
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 */
207#define ACLKRDIV(val) (val)
208#define ACLKRE BIT(5)
209#define RX_ASYNC BIT(6)
210#define ACLKRPOL BIT(7)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200211#define ACLKRDIV_MASK 0x1f
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400212
213/*
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 * Register Bits
216 */
217#define AHCLKXDIV(val) (val)
218#define AHCLKXPOL BIT(14)
219#define AHCLKXE BIT(15)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200220#define AHCLKXDIV_MASK 0xfff
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400221
222/*
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
224 * Register Bits
225 */
226#define AHCLKRDIV(val) (val)
227#define AHCLKRPOL BIT(14)
228#define AHCLKRE BIT(15)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200229#define AHCLKRDIV_MASK 0xfff
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400230
231/*
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
233 */
234#define MODE(val) (val)
235#define DISMOD (val)(val<<2)
236#define TXSTATE BIT(4)
237#define RXSTATE BIT(5)
Michal Bachraty2952b272013-02-28 16:07:08 +0100238#define SRMOD_MASK 3
239#define SRMOD_INACTIVE 0
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400240
241/*
242 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
243 */
244#define LBEN BIT(0)
245#define LBORD BIT(1)
246#define LBGENMODE(val) (val<<2)
247
248/*
249 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
250 */
251#define TXTDMS(n) (1<<n)
252
253/*
254 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
255 */
256#define RXTDMS(n) (1<<n)
257
258/*
259 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
260 */
261#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
262#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
263#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
264#define RXSMRST BIT(3) /* Receiver State Machine Reset */
265#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
266#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
267#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
268#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
269#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
270#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
271
272/*
273 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
274 */
275#define MUTENA(val) (val)
276#define MUTEINPOL BIT(2)
277#define MUTEINENA BIT(3)
278#define MUTEIN BIT(4)
279#define MUTER BIT(5)
280#define MUTEX BIT(6)
281#define MUTEFSR BIT(7)
282#define MUTEFSX BIT(8)
283#define MUTEBADCLKR BIT(9)
284#define MUTEBADCLKX BIT(10)
285#define MUTERXDMAERR BIT(11)
286#define MUTETXDMAERR BIT(12)
287
288/*
289 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
290 */
291#define RXDATADMADIS BIT(0)
292
293/*
294 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
295 */
296#define TXDATADMADIS BIT(0)
297
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400298/*
299 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
300 */
301#define FIFO_ENABLE BIT(16)
302#define NUMEVT_MASK (0xFF << 8)
303#define NUMDMA_MASK (0xFF)
304
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400305#define DAVINCI_MCASP_NUM_SERIALIZER 16
306
307static inline void mcasp_set_bits(void __iomem *reg, u32 val)
308{
309 __raw_writel(__raw_readl(reg) | val, reg);
310}
311
312static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
313{
314 __raw_writel((__raw_readl(reg) & ~(val)), reg);
315}
316
317static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
318{
319 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
320}
321
322static inline void mcasp_set_reg(void __iomem *reg, u32 val)
323{
324 __raw_writel(val, reg);
325}
326
327static inline u32 mcasp_get_reg(void __iomem *reg)
328{
329 return (unsigned int)__raw_readl(reg);
330}
331
332static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
333{
334 int i = 0;
335
336 mcasp_set_bits(regs, val);
337
338 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
339 /* loop count is to avoid the lock-up */
340 for (i = 0; i < 1000; i++) {
341 if ((mcasp_get_reg(regs) & val) == val)
342 break;
343 }
344
345 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
346 printk(KERN_ERR "GBLCTL write error\n");
347}
348
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400349static void mcasp_start_rx(struct davinci_audio_dev *dev)
350{
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
352 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
353 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
354 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
355
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
359
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
362}
363
364static void mcasp_start_tx(struct davinci_audio_dev *dev)
365{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400366 u8 offset = 0, i;
367 u32 cnt;
368
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
370 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
371 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
372 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
373
374 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
375 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400377 for (i = 0; i < dev->num_serializer; i++) {
378 if (dev->serial_dir[i] == TX_MODE) {
379 offset = i;
380 break;
381 }
382 }
383
384 /* wait for TX ready */
385 cnt = 0;
386 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
387 TXSTATE) && (cnt < 100000))
388 cnt++;
389
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400390 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
391}
392
393static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
394{
Chaithrika U S539d3d82009-09-23 10:12:08 -0400395 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530396 if (dev->txnumevt) { /* enable FIFO */
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530397 switch (dev->version) {
398 case MCASP_VERSION_3:
399 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530400 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530401 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
Chaithrika U S539d3d82009-09-23 10:12:08 -0400402 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530403 break;
404 default:
405 mcasp_clr_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 mcasp_set_bits(dev->base +
408 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
409 }
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530410 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400411 mcasp_start_tx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400412 } else {
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530413 if (dev->rxnumevt) { /* enable FIFO */
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530414 switch (dev->version) {
415 case MCASP_VERSION_3:
416 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530417 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530418 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
Chaithrika U S539d3d82009-09-23 10:12:08 -0400419 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530420 break;
421 default:
422 mcasp_clr_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 mcasp_set_bits(dev->base +
425 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
426 }
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530427 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400428 mcasp_start_rx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400429 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400430}
431
432static void mcasp_stop_rx(struct davinci_audio_dev *dev)
433{
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
436}
437
438static void mcasp_stop_tx(struct davinci_audio_dev *dev)
439{
440 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
441 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
442}
443
444static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
445{
Chaithrika U S539d3d82009-09-23 10:12:08 -0400446 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530447 if (dev->txnumevt) { /* disable FIFO */
448 switch (dev->version) {
449 case MCASP_VERSION_3:
450 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
Chaithrika U S539d3d82009-09-23 10:12:08 -0400451 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530452 break;
453 default:
454 mcasp_clr_bits(dev->base +
455 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
456 }
457 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400458 mcasp_stop_tx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400459 } else {
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530460 if (dev->rxnumevt) { /* disable FIFO */
461 switch (dev->version) {
462 case MCASP_VERSION_3:
463 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
Chaithrika U S539d3d82009-09-23 10:12:08 -0400464 FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530465 break;
466
467 default:
468 mcasp_clr_bits(dev->base +
469 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
470 }
471 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400472 mcasp_stop_rx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400473 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400474}
475
476static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
477 unsigned int fmt)
478{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000479 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400480 void __iomem *base = dev->base;
481
Daniel Mack5296cf22012-10-04 15:08:42 +0200482 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_DSP_B:
484 case SND_SOC_DAIFMT_AC97:
485 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
486 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
487 break;
488 default:
489 /* configure a full-word SYNC pulse (LRCLK) */
490 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
491 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
492
493 /* make 1st data bit occur one ACLK cycle after the frame sync */
494 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
495 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
496 break;
497 }
498
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400499 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
500 case SND_SOC_DAIFMT_CBS_CFS:
501 /* codec is clock and frame slave */
502 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
503 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
504
505 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
506 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
507
Marek Belisko81ee6832013-04-26 14:38:11 +0200508 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
509 ACLKX | ACLKR);
510 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
511 AFSX | AFSR);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400512 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400513 case SND_SOC_DAIFMT_CBM_CFS:
514 /* codec is clock master and frame slave */
Ben Gardinera90f5492011-04-21 14:19:03 -0400515 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400516 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517
Ben Gardinera90f5492011-04-21 14:19:03 -0400518 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400519 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520
Ben Gardinerdb92f432011-04-21 14:19:04 -0400521 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
522 ACLKX | ACLKR);
Ben Gardiner9595c8f2011-04-21 14:19:02 -0400523 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
Ben Gardinerdb92f432011-04-21 14:19:04 -0400524 AFSX | AFSR);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400525 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400526 case SND_SOC_DAIFMT_CBM_CFM:
527 /* codec is clock and frame master */
528 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
529 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530
531 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
532 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
533
Ben Gardiner9595c8f2011-04-21 14:19:02 -0400534 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
535 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400536 break;
537
538 default:
539 return -EINVAL;
540 }
541
542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543 case SND_SOC_DAIFMT_IB_NF:
544 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
545 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
546
547 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
548 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
549 break;
550
551 case SND_SOC_DAIFMT_NB_IF:
552 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
553 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
554
555 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
556 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
557 break;
558
559 case SND_SOC_DAIFMT_IB_IF:
560 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
562
563 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
564 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
565 break;
566
567 case SND_SOC_DAIFMT_NB_NF:
568 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
569 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
570
Marek Beliskodf4a4ee2013-05-03 07:37:36 +0200571 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400572 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
573 break;
574
575 default:
576 return -EINVAL;
577 }
578
579 return 0;
580}
581
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200582static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
583{
584 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
585
586 switch (div_id) {
587 case 0: /* MCLK divider */
588 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
589 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
590 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
591 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
592 break;
593
594 case 1: /* BCLK divider */
595 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
596 ACLKXDIV(div - 1), ACLKXDIV_MASK);
597 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
598 ACLKRDIV(div - 1), ACLKRDIV_MASK);
599 break;
600
Daniel Mack1b3bc062012-12-05 18:20:38 +0100601 case 2: /* BCLK/LRCLK ratio */
602 dev->bclk_lrclk_ratio = div;
603 break;
604
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200605 default:
606 return -EINVAL;
607 }
608
609 return 0;
610}
611
Daniel Mack5b66aa22012-10-04 15:08:41 +0200612static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
613 unsigned int freq, int dir)
614{
615 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
616
617 if (dir == SND_SOC_CLOCK_OUT) {
618 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
619 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
620 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
621 } else {
622 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
623 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
624 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
625 }
626
627 return 0;
628}
629
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400630static int davinci_config_channel_size(struct davinci_audio_dev *dev,
Daniel Mackba764b32012-12-05 18:20:37 +0100631 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400632{
Daniel Mackba764b32012-12-05 18:20:37 +0100633 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200634 u32 tx_rotate = (word_length / 4) & 0x7;
635 u32 rx_rotate = (32 - word_length) / 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100636 u32 mask = (1ULL << word_length) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400637
Daniel Mack1b3bc062012-12-05 18:20:38 +0100638 /*
639 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
640 * callback, take it into account here. That allows us to for example
641 * send 32 bits per channel to the codec, while only 16 of them carry
642 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200643 * The clock ratio is given for a full period of data (for I2S format
644 * both left and right channels), so it has to be divided by number of
645 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100646 */
647 if (dev->bclk_lrclk_ratio)
Michal Bachratyd486fea2013-04-19 15:28:44 +0200648 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100649
Daniel Mackba764b32012-12-05 18:20:37 +0100650 /* mapping of the XSSZ bit-field as described in the datasheet */
651 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400652
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200653 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
654 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
655 RXSSZ(fmt), RXSSZ(0x0F));
656 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
657 TXSSZ(fmt), TXSSZ(0x0F));
658 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
Daniel Mack79671892013-05-16 15:25:01 +0200659 TXROT(tx_rotate), TXROT(7));
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200660 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
Daniel Mack79671892013-05-16 15:25:01 +0200661 RXROT(rx_rotate), RXROT(7));
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200662 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
663 mask);
664 }
665
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400666 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400667
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400668 return 0;
669}
670
Michal Bachraty2952b272013-02-28 16:07:08 +0100671static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
672 int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400673{
674 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400675 u8 tx_ser = 0;
676 u8 rx_ser = 0;
Michal Bachraty2952b272013-02-28 16:07:08 +0100677 u8 ser;
678 u8 slots = dev->tdm_slots;
679 u8 max_active_serializers = (channels + slots - 1) / slots;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400680 /* Default configuration */
681 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
682
683 /* All PINS as McASP */
684 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
685
686 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
687 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
688 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
689 TXDATADMADIS);
690 } else {
691 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
692 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
693 RXDATADMADIS);
694 }
695
696 for (i = 0; i < dev->num_serializer; i++) {
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
698 dev->serial_dir[i]);
Michal Bachraty2952b272013-02-28 16:07:08 +0100699 if (dev->serial_dir[i] == TX_MODE &&
700 tx_ser < max_active_serializers) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400701 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
702 AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400703 tx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100704 } else if (dev->serial_dir[i] == RX_MODE &&
705 rx_ser < max_active_serializers) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400706 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
707 AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400708 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100709 } else {
710 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
711 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400712 }
713 }
714
Daniel Mackecf327c2013-03-08 14:19:38 +0100715 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
716 ser = tx_ser;
717 else
718 ser = rx_ser;
719
720 if (ser < max_active_serializers) {
721 dev_warn(dev->dev, "stream has more channels (%d) than are "
722 "enabled in mcasp (%d)\n", channels, ser * slots);
723 return -EINVAL;
724 }
725
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400726 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
727 if (dev->txnumevt * tx_ser > 64)
728 dev->txnumevt = 1;
729
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530730 switch (dev->version) {
731 case MCASP_VERSION_3:
732 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400733 NUMDMA_MASK);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530734 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400735 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530736 break;
737 default:
738 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
739 tx_ser, NUMDMA_MASK);
740 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
741 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
742 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400743 }
744
745 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
746 if (dev->rxnumevt * rx_ser > 64)
747 dev->rxnumevt = 1;
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530748 switch (dev->version) {
749 case MCASP_VERSION_3:
750 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400751 NUMDMA_MASK);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530752 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400753 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530754 break;
755 default:
756 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
757 rx_ser, NUMDMA_MASK);
758 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
759 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
760 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400761 }
Michal Bachraty2952b272013-02-28 16:07:08 +0100762
763 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400764}
765
766static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
767{
768 int i, active_slots;
769 u32 mask = 0;
770
771 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
772 for (i = 0; i < active_slots; i++)
773 mask |= (1 << i);
774
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400775 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
776
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400777 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
778 /* bit stream is MSB first with no delay */
779 /* DSP_B mode */
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400780 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
781 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
782
Ben Gardiner049cfaa2011-04-21 14:19:01 -0400783 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400784 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
785 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
786 else
787 printk(KERN_ERR "playback tdm slot %d not supported\n",
788 dev->tdm_slots);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400789 } else {
790 /* bit stream is MSB first with no delay */
791 /* DSP_B mode */
792 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400793 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
794
Ben Gardiner049cfaa2011-04-21 14:19:01 -0400795 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400796 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
797 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
798 else
799 printk(KERN_ERR "capture tdm slot %d not supported\n",
800 dev->tdm_slots);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400801 }
802}
803
804/* S/PDIF */
805static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
806{
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400807 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
808 and LSB first */
809 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
810 TXROT(6) | TXSSZ(15));
811
812 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
813 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
814 AFSXE | FSXMOD(0x180));
815
816 /* Set the TX tdm : for all the slots */
817 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
818
819 /* Set the TX clock controls : div = 1 and internal */
820 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
821 ACLKXE | TX_ASYNC);
822
823 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
824
825 /* Only 44100 and 48000 are valid, both have the same setting */
826 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
827
828 /* Enable the DIT */
829 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
830}
831
832static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
833 struct snd_pcm_hw_params *params,
834 struct snd_soc_dai *cpu_dai)
835{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000836 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400837 struct davinci_pcm_dma_params *dma_params =
Troy Kisky92e2a6f2009-09-11 14:29:03 -0700838 &dev->dma_params[substream->stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400839 int word_length;
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400840 u8 fifo_level;
Michal Bachraty2952b272013-02-28 16:07:08 +0100841 u8 slots = dev->tdm_slots;
Michal Bachraty7c21a782013-04-19 15:28:03 +0200842 u8 active_serializers;
Michal Bachraty2952b272013-02-28 16:07:08 +0100843 int channels;
844 struct snd_interval *pcm_channels = hw_param_interval(params,
845 SNDRV_PCM_HW_PARAM_CHANNELS);
846 channels = pcm_channels->min;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400847
Michal Bachraty7c21a782013-04-19 15:28:03 +0200848 active_serializers = (channels + slots - 1) / slots;
849
Michal Bachraty2952b272013-02-28 16:07:08 +0100850 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
851 return -EINVAL;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400852 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Michal Bachraty7c21a782013-04-19 15:28:03 +0200853 fifo_level = dev->txnumevt * active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400854 else
Michal Bachraty7c21a782013-04-19 15:28:03 +0200855 fifo_level = dev->rxnumevt * active_serializers;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400856
857 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
858 davinci_hw_dit_param(dev);
859 else
860 davinci_hw_param(dev, substream->stream);
861
862 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400863 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400864 case SNDRV_PCM_FORMAT_S8:
865 dma_params->data_type = 1;
Daniel Mackba764b32012-12-05 18:20:37 +0100866 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400867 break;
868
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400869 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400870 case SNDRV_PCM_FORMAT_S16_LE:
871 dma_params->data_type = 2;
Daniel Mackba764b32012-12-05 18:20:37 +0100872 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400873 break;
874
Daniel Mack21eb24d2012-10-09 09:35:16 +0200875 case SNDRV_PCM_FORMAT_U24_3LE:
876 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mack21eb24d2012-10-09 09:35:16 +0200877 dma_params->data_type = 3;
Daniel Mackba764b32012-12-05 18:20:37 +0100878 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200879 break;
880
Daniel Mack6b7fa012012-10-09 11:56:40 +0200881 case SNDRV_PCM_FORMAT_U24_LE:
882 case SNDRV_PCM_FORMAT_S24_LE:
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400883 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400884 case SNDRV_PCM_FORMAT_S32_LE:
885 dma_params->data_type = 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100886 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400887 break;
888
889 default:
890 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
891 return -EINVAL;
892 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400893
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400894 if (dev->version == MCASP_VERSION_2 && !fifo_level)
895 dma_params->acnt = 4;
896 else
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400897 dma_params->acnt = dma_params->data_type;
898
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400899 dma_params->fifo_level = fifo_level;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400900 davinci_config_channel_size(dev, word_length);
901
902 return 0;
903}
904
905static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
906 int cmd, struct snd_soc_dai *cpu_dai)
907{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000908 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400909 int ret = 0;
910
911 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400912 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530913 case SNDRV_PCM_TRIGGER_START:
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Hebbar, Gururaja10884342012-08-08 20:40:32 +0530915 ret = pm_runtime_get_sync(dev->dev);
916 if (IS_ERR_VALUE(ret))
917 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400918 davinci_mcasp_start(dev, substream->stream);
919 break;
920
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400921 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +0530922 davinci_mcasp_stop(dev, substream->stream);
Hebbar, Gururaja10884342012-08-08 20:40:32 +0530923 ret = pm_runtime_put_sync(dev->dev);
924 if (IS_ERR_VALUE(ret))
925 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
Chaithrika U Sa47979b2009-12-03 18:56:56 +0530926 break;
927
928 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400929 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
930 davinci_mcasp_stop(dev, substream->stream);
931 break;
932
933 default:
934 ret = -EINVAL;
935 }
936
937 return ret;
938}
939
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000940static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
941 struct snd_soc_dai *dai)
942{
943 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
944
945 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
946 return 0;
947}
948
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100949static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000950 .startup = davinci_mcasp_startup,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400951 .trigger = davinci_mcasp_trigger,
952 .hw_params = davinci_mcasp_hw_params,
953 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200954 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +0200955 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400956};
957
Peter Ujfalusied29cd52013-11-14 11:35:22 +0200958#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
959
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400960#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
961 SNDRV_PCM_FMTBIT_U8 | \
962 SNDRV_PCM_FMTBIT_S16_LE | \
963 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +0200964 SNDRV_PCM_FMTBIT_S24_LE | \
965 SNDRV_PCM_FMTBIT_U24_LE | \
966 SNDRV_PCM_FMTBIT_S24_3LE | \
967 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400968 SNDRV_PCM_FMTBIT_S32_LE | \
969 SNDRV_PCM_FMTBIT_U32_LE)
970
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000971static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400972 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000973 .name = "davinci-mcasp.0",
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400974 .playback = {
975 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100976 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400977 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400978 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400979 },
980 .capture = {
981 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100982 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400983 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400984 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400985 },
986 .ops = &davinci_mcasp_dai_ops,
987
988 },
989 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000990 "davinci-mcasp.1",
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400991 .playback = {
992 .channels_min = 1,
993 .channels_max = 384,
994 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400995 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400996 },
997 .ops = &davinci_mcasp_dai_ops,
998 },
999
1000};
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001001
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001002static const struct snd_soc_component_driver davinci_mcasp_component = {
1003 .name = "davinci-mcasp",
1004};
1005
Jyri Sarha256ba182013-10-18 18:37:42 +03001006/* Some HW specific values and defaults. The rest is filled in from DT. */
1007static struct snd_platform_data dm646x_mcasp_pdata = {
1008 .tx_dma_offset = 0x400,
1009 .rx_dma_offset = 0x400,
1010 .asp_chan_q = EVENTQ_0,
1011 .version = MCASP_VERSION_1,
1012};
1013
1014static struct snd_platform_data da830_mcasp_pdata = {
1015 .tx_dma_offset = 0x2000,
1016 .rx_dma_offset = 0x2000,
1017 .asp_chan_q = EVENTQ_0,
1018 .version = MCASP_VERSION_2,
1019};
1020
1021static struct snd_platform_data omap2_mcasp_pdata = {
1022 .tx_dma_offset = 0,
1023 .rx_dma_offset = 0,
1024 .asp_chan_q = EVENTQ_0,
1025 .version = MCASP_VERSION_3,
1026};
1027
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301028static const struct of_device_id mcasp_dt_ids[] = {
1029 {
1030 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001031 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301032 },
1033 {
1034 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001035 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301036 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301037 {
Jyri Sarha3af9e032013-10-18 18:37:44 +03001038 .compatible = "ti,am33xx-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001039 .data = &omap2_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301040 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301041 { /* sentinel */ }
1042};
1043MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1044
1045static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1046 struct platform_device *pdev)
1047{
1048 struct device_node *np = pdev->dev.of_node;
1049 struct snd_platform_data *pdata = NULL;
1050 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +05301051 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001052 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301053
1054 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301055 u32 val;
1056 int i, ret = 0;
1057
1058 if (pdev->dev.platform_data) {
1059 pdata = pdev->dev.platform_data;
1060 return pdata;
1061 } else if (match) {
Jyri Sarha256ba182013-10-18 18:37:42 +03001062 pdata = (struct snd_platform_data *) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301063 } else {
1064 /* control shouldn't reach here. something is wrong */
1065 ret = -EINVAL;
1066 goto nodata;
1067 }
1068
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301069 ret = of_property_read_u32(np, "op-mode", &val);
1070 if (ret >= 0)
1071 pdata->op_mode = val;
1072
1073 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +01001074 if (ret >= 0) {
1075 if (val < 2 || val > 32) {
1076 dev_err(&pdev->dev,
1077 "tdm-slots must be in rage [2-32]\n");
1078 ret = -EINVAL;
1079 goto nodata;
1080 }
1081
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301082 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +01001083 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301084
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301085 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1086 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301087 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001088 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1089 (sizeof(*of_serial_dir) * val),
1090 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301091 if (!of_serial_dir) {
1092 ret = -ENOMEM;
1093 goto nodata;
1094 }
1095
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001096 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301097 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1098
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001099 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301100 pdata->serial_dir = of_serial_dir;
1101 }
1102
Jyri Sarha4023fe62013-10-18 18:37:43 +03001103 ret = of_property_match_string(np, "dma-names", "tx");
1104 if (ret < 0)
1105 goto nodata;
1106
1107 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1108 &dma_spec);
1109 if (ret < 0)
1110 goto nodata;
1111
1112 pdata->tx_dma_channel = dma_spec.args[0];
1113
1114 ret = of_property_match_string(np, "dma-names", "rx");
1115 if (ret < 0)
1116 goto nodata;
1117
1118 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1119 &dma_spec);
1120 if (ret < 0)
1121 goto nodata;
1122
1123 pdata->rx_dma_channel = dma_spec.args[0];
1124
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301125 ret = of_property_read_u32(np, "tx-num-evt", &val);
1126 if (ret >= 0)
1127 pdata->txnumevt = val;
1128
1129 ret = of_property_read_u32(np, "rx-num-evt", &val);
1130 if (ret >= 0)
1131 pdata->rxnumevt = val;
1132
1133 ret = of_property_read_u32(np, "sram-size-playback", &val);
1134 if (ret >= 0)
1135 pdata->sram_size_playback = val;
1136
1137 ret = of_property_read_u32(np, "sram-size-capture", &val);
1138 if (ret >= 0)
1139 pdata->sram_size_capture = val;
1140
1141 return pdata;
1142
1143nodata:
1144 if (ret < 0) {
1145 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1146 ret);
1147 pdata = NULL;
1148 }
1149 return pdata;
1150}
1151
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001152static int davinci_mcasp_probe(struct platform_device *pdev)
1153{
1154 struct davinci_pcm_dma_params *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +03001155 struct resource *mem, *ioarea, *res, *dat;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001156 struct snd_platform_data *pdata;
1157 struct davinci_audio_dev *dev;
Julia Lawall96d31e22011-12-29 17:51:21 +01001158 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001159
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301160 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1161 dev_err(&pdev->dev, "No platform data supplied\n");
1162 return -EINVAL;
1163 }
1164
Julia Lawall96d31e22011-12-29 17:51:21 +01001165 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1166 GFP_KERNEL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001167 if (!dev)
1168 return -ENOMEM;
1169
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301170 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1171 if (!pdata) {
1172 dev_err(&pdev->dev, "no platform data\n");
1173 return -EINVAL;
1174 }
1175
Jyri Sarha256ba182013-10-18 18:37:42 +03001176 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001177 if (!mem) {
Jyri Sarha256ba182013-10-18 18:37:42 +03001178 dev_warn(dev->dev,
1179 "\"mpu\" mem resource not found, using index 0\n");
1180 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1181 if (!mem) {
1182 dev_err(&pdev->dev, "no mem resource?\n");
1183 return -ENODEV;
1184 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001185 }
1186
Julia Lawall96d31e22011-12-29 17:51:21 +01001187 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301188 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001189 if (!ioarea) {
1190 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001191 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001192 }
1193
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301194 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001195
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301196 ret = pm_runtime_get_sync(&pdev->dev);
1197 if (IS_ERR_VALUE(ret)) {
1198 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1199 return ret;
1200 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001201
Julia Lawall96d31e22011-12-29 17:51:21 +01001202 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301203 if (!dev->base) {
1204 dev_err(&pdev->dev, "ioremap failed\n");
1205 ret = -ENOMEM;
1206 goto err_release_clk;
1207 }
1208
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001209 dev->op_mode = pdata->op_mode;
1210 dev->tdm_slots = pdata->tdm_slots;
1211 dev->num_serializer = pdata->num_serializer;
1212 dev->serial_dir = pdata->serial_dir;
Chaithrika U S6a99fb52009-08-11 16:58:52 -04001213 dev->version = pdata->version;
1214 dev->txnumevt = pdata->txnumevt;
1215 dev->rxnumevt = pdata->rxnumevt;
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301216 dev->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001217
Jyri Sarha256ba182013-10-18 18:37:42 +03001218 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1219 if (!dat)
1220 dat = mem;
1221
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001222 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
Sekhar Nori48519f02010-07-19 12:31:16 +05301223 dma_data->asp_chan_q = pdata->asp_chan_q;
1224 dma_data->ram_chan_q = pdata->ram_chan_q;
Matt Porterb8ec56d2012-10-17 16:08:03 +02001225 dma_data->sram_pool = pdata->sram_pool;
Ben Gardinera0c83262011-05-18 09:27:45 -04001226 dma_data->sram_size = pdata->sram_size_playback;
Jyri Sarha256ba182013-10-18 18:37:42 +03001227 dma_data->dma_addr = dat->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001228
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001229 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001230 if (res)
1231 dma_data->channel = res->start;
1232 else
1233 dma_data->channel = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001234
1235 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
Sekhar Nori48519f02010-07-19 12:31:16 +05301236 dma_data->asp_chan_q = pdata->asp_chan_q;
1237 dma_data->ram_chan_q = pdata->ram_chan_q;
Matt Porterb8ec56d2012-10-17 16:08:03 +02001238 dma_data->sram_pool = pdata->sram_pool;
Ben Gardinera0c83262011-05-18 09:27:45 -04001239 dma_data->sram_size = pdata->sram_size_capture;
Jyri Sarha256ba182013-10-18 18:37:42 +03001240 dma_data->dma_addr = dat->start + pdata->rx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001241
1242 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001243 if (res)
1244 dma_data->channel = res->start;
1245 else
1246 dma_data->channel = pdata->rx_dma_channel;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001247
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001248 dev_set_drvdata(&pdev->dev, dev);
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001249 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1250 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001251
1252 if (ret != 0)
Julia Lawall96d31e22011-12-29 17:51:21 +01001253 goto err_release_clk;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301254
1255 ret = davinci_soc_platform_register(&pdev->dev);
1256 if (ret) {
1257 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001258 goto err_unregister_component;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301259 }
1260
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001261 return 0;
1262
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001263err_unregister_component:
1264 snd_soc_unregister_component(&pdev->dev);
Vaibhav Bediaeef6d7b2011-02-09 18:39:53 +05301265err_release_clk:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301266 pm_runtime_put_sync(&pdev->dev);
1267 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001268 return ret;
1269}
1270
1271static int davinci_mcasp_remove(struct platform_device *pdev)
1272{
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001273
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001274 snd_soc_unregister_component(&pdev->dev);
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301275 davinci_soc_platform_unregister(&pdev->dev);
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301276
1277 pm_runtime_put_sync(&pdev->dev);
1278 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001279
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001280 return 0;
1281}
1282
Daniel Macka85e4192013-10-01 14:50:02 +02001283#ifdef CONFIG_PM_SLEEP
1284static int davinci_mcasp_suspend(struct device *dev)
1285{
1286 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1287 void __iomem *base = a->base;
1288
1289 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
1290 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
1291 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
1292 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
1293 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
1294 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
1295 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1296
1297 return 0;
1298}
1299
1300static int davinci_mcasp_resume(struct device *dev)
1301{
1302 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1303 void __iomem *base = a->base;
1304
1305 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl);
1306 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl);
1307 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt);
1308 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt);
1309 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl);
1310 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl);
1311 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
1312
1313 return 0;
1314}
1315#endif
1316
1317SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1318 davinci_mcasp_suspend,
1319 davinci_mcasp_resume);
1320
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001321static struct platform_driver davinci_mcasp_driver = {
1322 .probe = davinci_mcasp_probe,
1323 .remove = davinci_mcasp_remove,
1324 .driver = {
1325 .name = "davinci-mcasp",
1326 .owner = THIS_MODULE,
Daniel Macka85e4192013-10-01 14:50:02 +02001327 .pm = &davinci_mcasp_pm_ops,
Sachin Kamatea421eb2013-05-22 16:53:37 +05301328 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001329 },
1330};
1331
Axel Linf9b8a512011-11-25 10:09:27 +08001332module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001333
1334MODULE_AUTHOR("Steve Chen");
1335MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1336MODULE_LICENSE("GPL");