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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33#include <linux/device.h>
34#include <linux/interrupt.h>
35#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030037#include "musb_core.h"
Bryan Wu6995eb62008-12-02 21:33:47 +020038#include "musbhsdma.h"
Felipe Balbi550a7372008-07-24 12:27:36 +030039
Felipe Balbi458e6a52008-09-11 11:53:24 +030040static void dma_channel_release(struct dma_channel *channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030041
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +020042static void dma_controller_stop(struct musb_dma_controller *controller)
Felipe Balbi550a7372008-07-24 12:27:36 +030043{
Felipe Balbi458e6a52008-09-11 11:53:24 +030044 struct musb *musb = controller->private_data;
45 struct dma_channel *channel;
46 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +030047
Felipe Balbi458e6a52008-09-11 11:53:24 +030048 if (controller->used_channels != 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +030049 dev_err(musb->controller,
50 "Stopping DMA controller while channel active\n");
51
Felipe Balbi458e6a52008-09-11 11:53:24 +030052 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
53 if (controller->used_channels & (1 << bit)) {
54 channel = &controller->channel[bit].channel;
55 dma_channel_release(channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030056
Felipe Balbi458e6a52008-09-11 11:53:24 +030057 if (!controller->used_channels)
Felipe Balbi550a7372008-07-24 12:27:36 +030058 break;
59 }
60 }
61 }
Felipe Balbi550a7372008-07-24 12:27:36 +030062}
63
64static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
65 struct musb_hw_ep *hw_ep, u8 transmit)
66{
Felipe Balbi458e6a52008-09-11 11:53:24 +030067 struct musb_dma_controller *controller = container_of(c,
68 struct musb_dma_controller, controller);
69 struct musb_dma_channel *musb_channel = NULL;
70 struct dma_channel *channel = NULL;
71 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +030072
Felipe Balbi458e6a52008-09-11 11:53:24 +030073 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
74 if (!(controller->used_channels & (1 << bit))) {
75 controller->used_channels |= (1 << bit);
76 musb_channel = &(controller->channel[bit]);
77 musb_channel->controller = controller;
78 musb_channel->idx = bit;
79 musb_channel->epnum = hw_ep->epnum;
80 musb_channel->transmit = transmit;
81 channel = &(musb_channel->channel);
82 channel->private_data = musb_channel;
83 channel->status = MUSB_DMA_STATUS_FREE;
Anil Shetty6587cc02010-09-24 13:44:05 +030084 channel->max_len = 0x100000;
Felipe Balbi550a7372008-07-24 12:27:36 +030085 /* Tx => mode 1; Rx => mode 0 */
Felipe Balbi458e6a52008-09-11 11:53:24 +030086 channel->desired_mode = transmit;
87 channel->actual_len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +030088 break;
89 }
90 }
Felipe Balbi458e6a52008-09-11 11:53:24 +030091
92 return channel;
Felipe Balbi550a7372008-07-24 12:27:36 +030093}
94
Felipe Balbi458e6a52008-09-11 11:53:24 +030095static void dma_channel_release(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +030096{
Felipe Balbi458e6a52008-09-11 11:53:24 +030097 struct musb_dma_channel *musb_channel = channel->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +030098
Felipe Balbi458e6a52008-09-11 11:53:24 +030099 channel->actual_len = 0;
100 musb_channel->start_addr = 0;
101 musb_channel->len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300102
Felipe Balbi458e6a52008-09-11 11:53:24 +0300103 musb_channel->controller->used_channels &=
104 ~(1 << musb_channel->idx);
Felipe Balbi550a7372008-07-24 12:27:36 +0300105
Felipe Balbi458e6a52008-09-11 11:53:24 +0300106 channel->status = MUSB_DMA_STATUS_UNKNOWN;
Felipe Balbi550a7372008-07-24 12:27:36 +0300107}
108
Felipe Balbi458e6a52008-09-11 11:53:24 +0300109static void configure_channel(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300110 u16 packet_sz, u8 mode,
111 dma_addr_t dma_addr, u32 len)
112{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300113 struct musb_dma_channel *musb_channel = channel->private_data;
114 struct musb_dma_controller *controller = musb_channel->controller;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300115 struct musb *musb = controller->private_data;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300116 void __iomem *mbase = controller->base;
117 u8 bchannel = musb_channel->idx;
Felipe Balbi550a7372008-07-24 12:27:36 +0300118 u16 csr = 0;
119
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300120 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300121 channel, packet_sz, dma_addr, len, mode);
Felipe Balbi550a7372008-07-24 12:27:36 +0300122
123 if (mode) {
124 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
125 BUG_ON(len < packet_sz);
Felipe Balbi550a7372008-07-24 12:27:36 +0300126 }
Hema HKc0f1f8e2010-06-24 23:07:09 +0530127 csr |= MUSB_HSDMA_BURSTMODE_INCR16
128 << MUSB_HSDMA_BURSTMODE_SHIFT;
Felipe Balbi550a7372008-07-24 12:27:36 +0300129
Felipe Balbi458e6a52008-09-11 11:53:24 +0300130 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
Felipe Balbi550a7372008-07-24 12:27:36 +0300131 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
132 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300133 | (musb_channel->transmit
Felipe Balbi550a7372008-07-24 12:27:36 +0300134 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
135 : 0);
136
137 /* address/count */
Bryan Wu6995eb62008-12-02 21:33:47 +0200138 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
139 musb_write_hsdma_count(mbase, bchannel, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300140
141 /* control (this should start things) */
142 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300143 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300144 csr);
145}
146
Felipe Balbi458e6a52008-09-11 11:53:24 +0300147static int dma_channel_program(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300148 u16 packet_sz, u8 mode,
149 dma_addr_t dma_addr, u32 len)
150{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300151 struct musb_dma_channel *musb_channel = channel->private_data;
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600152 struct musb_dma_controller *controller = musb_channel->controller;
153 struct musb *musb = controller->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +0300154
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300155 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300156 musb_channel->epnum,
157 musb_channel->transmit ? "Tx" : "Rx",
Felipe Balbi550a7372008-07-24 12:27:36 +0300158 packet_sz, dma_addr, len, mode);
159
Felipe Balbi458e6a52008-09-11 11:53:24 +0300160 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
161 channel->status == MUSB_DMA_STATUS_BUSY);
Felipe Balbi550a7372008-07-24 12:27:36 +0300162
Mike Frysinger13254302011-03-30 22:48:54 -0400163 /* Let targets check/tweak the arguments */
164 if (musb->ops->adjust_channel_params) {
165 int ret = musb->ops->adjust_channel_params(channel,
166 packet_sz, &mode, &dma_addr, &len);
167 if (ret)
168 return ret;
169 }
170
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600171 /*
172 * The DMA engine in RTL1.8 and above cannot handle
173 * DMA addresses that are not aligned to a 4 byte boundary.
174 * It ends up masking the last two bits of the address
175 * programmed in DMA_ADDR.
176 *
177 * Fail such DMA transfers, so that the backup PIO mode
178 * can carry out the transfer
179 */
180 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
181 return false;
182
Felipe Balbi458e6a52008-09-11 11:53:24 +0300183 channel->actual_len = 0;
184 musb_channel->start_addr = dma_addr;
185 musb_channel->len = len;
186 musb_channel->max_packet_sz = packet_sz;
187 channel->status = MUSB_DMA_STATUS_BUSY;
Felipe Balbi550a7372008-07-24 12:27:36 +0300188
Anand Gadiyar8ca47c82010-07-08 16:34:55 +0530189 configure_channel(channel, packet_sz, mode, dma_addr, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300190
191 return true;
192}
193
Felipe Balbi458e6a52008-09-11 11:53:24 +0300194static int dma_channel_abort(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +0300195{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300196 struct musb_dma_channel *musb_channel = channel->private_data;
197 void __iomem *mbase = musb_channel->controller->base;
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800198 struct musb *musb = musb_channel->controller->private_data;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300199
200 u8 bchannel = musb_channel->idx;
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700201 int offset;
Felipe Balbi550a7372008-07-24 12:27:36 +0300202 u16 csr;
203
Felipe Balbi458e6a52008-09-11 11:53:24 +0300204 if (channel->status == MUSB_DMA_STATUS_BUSY) {
205 if (musb_channel->transmit) {
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800206 offset = musb->io.ep_offset(musb_channel->epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700207 MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300208
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700209 /*
210 * The programming guide says that we must clear
211 * the DMAENAB bit before the DMAMODE bit...
212 */
213 csr = musb_readw(mbase, offset);
214 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
215 musb_writew(mbase, offset, csr);
216 csr &= ~MUSB_TXCSR_DMAMODE;
217 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300218 } else {
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800219 offset = musb->io.ep_offset(musb_channel->epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700220 MUSB_RXCSR);
221
222 csr = musb_readw(mbase, offset);
Felipe Balbi550a7372008-07-24 12:27:36 +0300223 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
224 MUSB_RXCSR_DMAENAB |
225 MUSB_RXCSR_DMAMODE);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700226 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300227 }
228
229 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300230 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300231 0);
Bryan Wu6995eb62008-12-02 21:33:47 +0200232 musb_write_hsdma_addr(mbase, bchannel, 0);
233 musb_write_hsdma_count(mbase, bchannel, 0);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300234 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300235 }
Felipe Balbi458e6a52008-09-11 11:53:24 +0300236
Felipe Balbi550a7372008-07-24 12:27:36 +0300237 return 0;
238}
239
240static irqreturn_t dma_controller_irq(int irq, void *private_data)
241{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300242 struct musb_dma_controller *controller = private_data;
243 struct musb *musb = controller->private_data;
244 struct musb_dma_channel *musb_channel;
245 struct dma_channel *channel;
246
247 void __iomem *mbase = controller->base;
248
Felipe Balbi550a7372008-07-24 12:27:36 +0300249 irqreturn_t retval = IRQ_NONE;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300250
Felipe Balbi550a7372008-07-24 12:27:36 +0300251 unsigned long flags;
252
Felipe Balbi458e6a52008-09-11 11:53:24 +0300253 u8 bchannel;
254 u8 int_hsdma;
255
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200256 u32 addr, count;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300257 u16 csr;
258
Felipe Balbi550a7372008-07-24 12:27:36 +0300259 spin_lock_irqsave(&musb->lock, flags);
260
261 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300262
Cliff Cai6bd03e72009-11-16 16:19:26 +0530263#ifdef CONFIG_BLACKFIN
264 /* Clear DMA interrupt flags */
265 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
266#endif
267
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200268 if (!int_hsdma) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300269 dev_dbg(musb->controller, "spurious DMA irq\n");
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200270
271 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
272 musb_channel = (struct musb_dma_channel *)
273 &(controller->channel[bchannel]);
274 channel = &musb_channel->channel;
275 if (channel->status == MUSB_DMA_STATUS_BUSY) {
276 count = musb_read_hsdma_count(mbase, bchannel);
277
278 if (count == 0)
279 int_hsdma |= (1 << bchannel);
280 }
281 }
282
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300283 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200284
285 if (!int_hsdma)
286 goto done;
287 }
288
Felipe Balbi458e6a52008-09-11 11:53:24 +0300289 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
290 if (int_hsdma & (1 << bchannel)) {
291 musb_channel = (struct musb_dma_channel *)
292 &(controller->channel[bchannel]);
293 channel = &musb_channel->channel;
Felipe Balbi550a7372008-07-24 12:27:36 +0300294
295 csr = musb_readw(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300296 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300297 MUSB_HSDMA_CONTROL));
298
Felipe Balbi458e6a52008-09-11 11:53:24 +0300299 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
300 musb_channel->channel.status =
Felipe Balbi550a7372008-07-24 12:27:36 +0300301 MUSB_DMA_STATUS_BUS_ABORT;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300302 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +0300303 u8 devctl;
304
Bryan Wu6995eb62008-12-02 21:33:47 +0200305 addr = musb_read_hsdma_addr(mbase,
306 bchannel);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300307 channel->actual_len = addr
308 - musb_channel->start_addr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300309
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300310 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300311 channel, musb_channel->start_addr,
312 addr, channel->actual_len,
313 musb_channel->len,
314 (channel->actual_len
315 < musb_channel->len) ?
Felipe Balbi550a7372008-07-24 12:27:36 +0300316 "=> reconfig 0" : "=> complete");
317
318 devctl = musb_readb(mbase, MUSB_DEVCTL);
319
Felipe Balbi458e6a52008-09-11 11:53:24 +0300320 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300321
322 /* completed */
323 if ((devctl & MUSB_DEVCTL_HM)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300324 && (musb_channel->transmit)
325 && ((channel->desired_mode == 0)
326 || (channel->actual_len &
327 (musb_channel->max_packet_sz - 1)))
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700328 ) {
329 u8 epnum = musb_channel->epnum;
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800330 int offset = musb->io.ep_offset(epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700331 MUSB_TXCSR);
332 u16 txcsr;
333
334 /*
335 * The programming guide says that we
336 * must clear DMAENAB before DMAMODE.
337 */
338 musb_ep_select(mbase, epnum);
339 txcsr = musb_readw(mbase, offset);
340 txcsr &= ~(MUSB_TXCSR_DMAENAB
341 | MUSB_TXCSR_AUTOSET);
342 musb_writew(mbase, offset, txcsr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300343 /* Send out the packet */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700344 txcsr &= ~MUSB_TXCSR_DMAMODE;
345 txcsr |= MUSB_TXCSR_TXPKTRDY;
346 musb_writew(mbase, offset, txcsr);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300347 }
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700348 musb_dma_completion(musb, musb_channel->epnum,
349 musb_channel->transmit);
Felipe Balbi550a7372008-07-24 12:27:36 +0300350 }
351 }
352 }
Bryan Wu6995eb62008-12-02 21:33:47 +0200353
Felipe Balbi550a7372008-07-24 12:27:36 +0300354 retval = IRQ_HANDLED;
355done:
356 spin_unlock_irqrestore(&musb->lock, flags);
357 return retval;
358}
359
360void dma_controller_destroy(struct dma_controller *c)
361{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300362 struct musb_dma_controller *controller = container_of(c,
363 struct musb_dma_controller, controller);
Felipe Balbi550a7372008-07-24 12:27:36 +0300364
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200365 dma_controller_stop(controller);
366
Felipe Balbi550a7372008-07-24 12:27:36 +0300367 if (controller->irq)
368 free_irq(controller->irq, c);
369
370 kfree(controller);
371}
372
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500373struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base)
Felipe Balbi550a7372008-07-24 12:27:36 +0300374{
375 struct musb_dma_controller *controller;
376 struct device *dev = musb->controller;
377 struct platform_device *pdev = to_platform_device(dev);
Hema Kalliguddifcf173e2010-09-29 11:26:39 -0500378 int irq = platform_get_irq_byname(pdev, "dma");
Felipe Balbi550a7372008-07-24 12:27:36 +0300379
Sergei Shtylyov7effdbd2012-08-20 22:34:46 +0400380 if (irq <= 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300381 dev_err(dev, "No DMA interrupt line!\n");
382 return NULL;
383 }
384
Felipe Balbi458e6a52008-09-11 11:53:24 +0300385 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
Felipe Balbi550a7372008-07-24 12:27:36 +0300386 if (!controller)
387 return NULL;
388
Felipe Balbi458e6a52008-09-11 11:53:24 +0300389 controller->channel_count = MUSB_HSDMA_CHANNELS;
390 controller->private_data = musb;
391 controller->base = base;
Felipe Balbi550a7372008-07-24 12:27:36 +0300392
Felipe Balbi458e6a52008-09-11 11:53:24 +0300393 controller->controller.channel_alloc = dma_channel_allocate;
394 controller->controller.channel_release = dma_channel_release;
395 controller->controller.channel_program = dma_channel_program;
396 controller->controller.channel_abort = dma_channel_abort;
Felipe Balbi550a7372008-07-24 12:27:36 +0300397
Yong Zhangb5dd18d2011-09-07 16:10:52 +0800398 if (request_irq(irq, dma_controller_irq, 0,
Kay Sievers427c4f32008-11-07 01:52:53 +0100399 dev_name(musb->controller), &controller->controller)) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300400 dev_err(dev, "request_irq %d failed!\n", irq);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300401 dma_controller_destroy(&controller->controller);
402
Felipe Balbi550a7372008-07-24 12:27:36 +0300403 return NULL;
404 }
405
406 controller->irq = irq;
407
Felipe Balbi458e6a52008-09-11 11:53:24 +0300408 return &controller->controller;
Felipe Balbi550a7372008-07-24 12:27:36 +0300409}