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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +02006 * Portions Copyright (C) 2005-2008 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
Alan Coxccd32e22008-11-02 21:40:08 +010055 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 */
119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120#include <linux/types.h>
121#include <linux/module.h>
122#include <linux/kernel.h>
123#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125#include <linux/interrupt.h>
126#include <linux/pci.h>
127#include <linux/init.h>
128#include <linux/ide.h>
129
130#include <asm/uaccess.h>
131#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200133#define DRV_NAME "hpt366"
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135/* various tuning parameters */
136#define HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800137#undef HPT_DELAY_INTERRUPT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138
139static const char *quirk_drives[] = {
140 "QUANTUM FIREBALLlct08 08",
141 "QUANTUM FIREBALLP KA6.4",
142 "QUANTUM FIREBALLP LM20.4",
143 "QUANTUM FIREBALLP LM20.5",
144 NULL
145};
146
147static const char *bad_ata100_5[] = {
148 "IBM-DTLA-307075",
149 "IBM-DTLA-307060",
150 "IBM-DTLA-307045",
151 "IBM-DTLA-307030",
152 "IBM-DTLA-307020",
153 "IBM-DTLA-307015",
154 "IBM-DTLA-305040",
155 "IBM-DTLA-305030",
156 "IBM-DTLA-305020",
157 "IC35L010AVER07-0",
158 "IC35L020AVER07-0",
159 "IC35L030AVER07-0",
160 "IC35L040AVER07-0",
161 "IC35L060AVER07-0",
162 "WDC AC310200R",
163 NULL
164};
165
166static const char *bad_ata66_4[] = {
167 "IBM-DTLA-307075",
168 "IBM-DTLA-307060",
169 "IBM-DTLA-307045",
170 "IBM-DTLA-307030",
171 "IBM-DTLA-307020",
172 "IBM-DTLA-307015",
173 "IBM-DTLA-305040",
174 "IBM-DTLA-305030",
175 "IBM-DTLA-305020",
176 "IC35L010AVER07-0",
177 "IC35L020AVER07-0",
178 "IC35L030AVER07-0",
179 "IC35L040AVER07-0",
180 "IC35L060AVER07-0",
181 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200182 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 NULL
184};
185
186static const char *bad_ata66_3[] = {
187 "WDC AC310200R",
188 NULL
189};
190
191static const char *bad_ata33[] = {
192 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
193 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
194 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
195 "Maxtor 90510D4",
196 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
197 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
198 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
199 NULL
200};
201
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800202static u8 xfer_speeds[] = {
203 XFER_UDMA_6,
204 XFER_UDMA_5,
205 XFER_UDMA_4,
206 XFER_UDMA_3,
207 XFER_UDMA_2,
208 XFER_UDMA_1,
209 XFER_UDMA_0,
210
211 XFER_MW_DMA_2,
212 XFER_MW_DMA_1,
213 XFER_MW_DMA_0,
214
215 XFER_PIO_4,
216 XFER_PIO_3,
217 XFER_PIO_2,
218 XFER_PIO_1,
219 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220};
221
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800222/* Key for bus clock timings
223 * 36x 37x
224 * bits bits
225 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
226 * cycles = value + 1
227 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
228 * cycles = value + 1
229 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
230 * register access.
231 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
232 * register access.
233 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
234 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
235 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
236 * MW DMA xfer.
237 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
238 * task file register access.
239 * 28 28 UDMA enable.
240 * 29 29 DMA enable.
241 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
242 * PIO xfer.
243 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800246static u32 forty_base_hpt36x[] = {
247 /* XFER_UDMA_6 */ 0x900fd943,
248 /* XFER_UDMA_5 */ 0x900fd943,
249 /* XFER_UDMA_4 */ 0x900fd943,
250 /* XFER_UDMA_3 */ 0x900ad943,
251 /* XFER_UDMA_2 */ 0x900bd943,
252 /* XFER_UDMA_1 */ 0x9008d943,
253 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800255 /* XFER_MW_DMA_2 */ 0xa008d943,
256 /* XFER_MW_DMA_1 */ 0xa010d955,
257 /* XFER_MW_DMA_0 */ 0xa010d9fc,
258
259 /* XFER_PIO_4 */ 0xc008d963,
260 /* XFER_PIO_3 */ 0xc010d974,
261 /* XFER_PIO_2 */ 0xc010d997,
262 /* XFER_PIO_1 */ 0xc010d9c7,
263 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264};
265
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800266static u32 thirty_three_base_hpt36x[] = {
267 /* XFER_UDMA_6 */ 0x90c9a731,
268 /* XFER_UDMA_5 */ 0x90c9a731,
269 /* XFER_UDMA_4 */ 0x90c9a731,
270 /* XFER_UDMA_3 */ 0x90cfa731,
271 /* XFER_UDMA_2 */ 0x90caa731,
272 /* XFER_UDMA_1 */ 0x90cba731,
273 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800275 /* XFER_MW_DMA_2 */ 0xa0c8a731,
276 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
277 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800279 /* XFER_PIO_4 */ 0xc0c8a731,
280 /* XFER_PIO_3 */ 0xc0c8a742,
281 /* XFER_PIO_2 */ 0xc0d0a753,
282 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
283 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284};
285
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800286static u32 twenty_five_base_hpt36x[] = {
287 /* XFER_UDMA_6 */ 0x90c98521,
288 /* XFER_UDMA_5 */ 0x90c98521,
289 /* XFER_UDMA_4 */ 0x90c98521,
290 /* XFER_UDMA_3 */ 0x90cf8521,
291 /* XFER_UDMA_2 */ 0x90cf8521,
292 /* XFER_UDMA_1 */ 0x90cb8521,
293 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800295 /* XFER_MW_DMA_2 */ 0xa0ca8521,
296 /* XFER_MW_DMA_1 */ 0xa0ca8532,
297 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800299 /* XFER_PIO_4 */ 0xc0ca8521,
300 /* XFER_PIO_3 */ 0xc0ca8532,
301 /* XFER_PIO_2 */ 0xc0ca8542,
302 /* XFER_PIO_1 */ 0xc0d08572,
303 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304};
305
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100306#if 0
307/* These are the timing tables from the HighPoint open source drivers... */
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800308static u32 thirty_three_base_hpt37x[] = {
309 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
310 /* XFER_UDMA_5 */ 0x12446231,
311 /* XFER_UDMA_4 */ 0x12446231,
312 /* XFER_UDMA_3 */ 0x126c6231,
313 /* XFER_UDMA_2 */ 0x12486231,
314 /* XFER_UDMA_1 */ 0x124c6233,
315 /* XFER_UDMA_0 */ 0x12506297,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800317 /* XFER_MW_DMA_2 */ 0x22406c31,
318 /* XFER_MW_DMA_1 */ 0x22406c33,
319 /* XFER_MW_DMA_0 */ 0x22406c97,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800321 /* XFER_PIO_4 */ 0x06414e31,
322 /* XFER_PIO_3 */ 0x06414e42,
323 /* XFER_PIO_2 */ 0x06414e53,
324 /* XFER_PIO_1 */ 0x06814e93,
325 /* XFER_PIO_0 */ 0x06814ea7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326};
327
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800328static u32 fifty_base_hpt37x[] = {
329 /* XFER_UDMA_6 */ 0x12848242,
330 /* XFER_UDMA_5 */ 0x12848242,
331 /* XFER_UDMA_4 */ 0x12ac8242,
332 /* XFER_UDMA_3 */ 0x128c8242,
333 /* XFER_UDMA_2 */ 0x120c8242,
334 /* XFER_UDMA_1 */ 0x12148254,
335 /* XFER_UDMA_0 */ 0x121882ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800337 /* XFER_MW_DMA_2 */ 0x22808242,
338 /* XFER_MW_DMA_1 */ 0x22808254,
339 /* XFER_MW_DMA_0 */ 0x228082ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800341 /* XFER_PIO_4 */ 0x0a81f442,
342 /* XFER_PIO_3 */ 0x0a81f443,
343 /* XFER_PIO_2 */ 0x0a81f454,
344 /* XFER_PIO_1 */ 0x0ac1f465,
345 /* XFER_PIO_0 */ 0x0ac1f48a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346};
347
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800348static u32 sixty_six_base_hpt37x[] = {
349 /* XFER_UDMA_6 */ 0x1c869c62,
350 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
351 /* XFER_UDMA_4 */ 0x1c8a9c62,
352 /* XFER_UDMA_3 */ 0x1c8e9c62,
353 /* XFER_UDMA_2 */ 0x1c929c62,
354 /* XFER_UDMA_1 */ 0x1c9a9c62,
355 /* XFER_UDMA_0 */ 0x1c829c62,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800357 /* XFER_MW_DMA_2 */ 0x2c829c62,
358 /* XFER_MW_DMA_1 */ 0x2c829c66,
359 /* XFER_MW_DMA_0 */ 0x2c829d2e,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800361 /* XFER_PIO_4 */ 0x0c829c62,
362 /* XFER_PIO_3 */ 0x0c829c84,
363 /* XFER_PIO_2 */ 0x0c829ca6,
364 /* XFER_PIO_1 */ 0x0d029d26,
365 /* XFER_PIO_0 */ 0x0d029d5e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366};
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100367#else
368/*
369 * The following are the new timing tables with PIO mode data/taskfile transfer
370 * overclocking fixed...
371 */
372
373/* This table is taken from the HPT370 data manual rev. 1.02 */
374static u32 thirty_three_base_hpt37x[] = {
375 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
376 /* XFER_UDMA_5 */ 0x16455031,
377 /* XFER_UDMA_4 */ 0x16455031,
378 /* XFER_UDMA_3 */ 0x166d5031,
379 /* XFER_UDMA_2 */ 0x16495031,
380 /* XFER_UDMA_1 */ 0x164d5033,
381 /* XFER_UDMA_0 */ 0x16515097,
382
383 /* XFER_MW_DMA_2 */ 0x26515031,
384 /* XFER_MW_DMA_1 */ 0x26515033,
385 /* XFER_MW_DMA_0 */ 0x26515097,
386
387 /* XFER_PIO_4 */ 0x06515021,
388 /* XFER_PIO_3 */ 0x06515022,
389 /* XFER_PIO_2 */ 0x06515033,
390 /* XFER_PIO_1 */ 0x06915065,
391 /* XFER_PIO_0 */ 0x06d1508a
392};
393
394static u32 fifty_base_hpt37x[] = {
395 /* XFER_UDMA_6 */ 0x1a861842,
396 /* XFER_UDMA_5 */ 0x1a861842,
397 /* XFER_UDMA_4 */ 0x1aae1842,
398 /* XFER_UDMA_3 */ 0x1a8e1842,
399 /* XFER_UDMA_2 */ 0x1a0e1842,
400 /* XFER_UDMA_1 */ 0x1a161854,
401 /* XFER_UDMA_0 */ 0x1a1a18ea,
402
403 /* XFER_MW_DMA_2 */ 0x2a821842,
404 /* XFER_MW_DMA_1 */ 0x2a821854,
405 /* XFER_MW_DMA_0 */ 0x2a8218ea,
406
407 /* XFER_PIO_4 */ 0x0a821842,
408 /* XFER_PIO_3 */ 0x0a821843,
409 /* XFER_PIO_2 */ 0x0a821855,
410 /* XFER_PIO_1 */ 0x0ac218a8,
411 /* XFER_PIO_0 */ 0x0b02190c
412};
413
414static u32 sixty_six_base_hpt37x[] = {
415 /* XFER_UDMA_6 */ 0x1c86fe62,
416 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
417 /* XFER_UDMA_4 */ 0x1c8afe62,
418 /* XFER_UDMA_3 */ 0x1c8efe62,
419 /* XFER_UDMA_2 */ 0x1c92fe62,
420 /* XFER_UDMA_1 */ 0x1c9afe62,
421 /* XFER_UDMA_0 */ 0x1c82fe62,
422
423 /* XFER_MW_DMA_2 */ 0x2c82fe62,
424 /* XFER_MW_DMA_1 */ 0x2c82fe66,
425 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
426
427 /* XFER_PIO_4 */ 0x0c82fe62,
428 /* XFER_PIO_3 */ 0x0c82fe84,
429 /* XFER_PIO_2 */ 0x0c82fea6,
430 /* XFER_PIO_1 */ 0x0d02ff26,
431 /* XFER_PIO_0 */ 0x0d42ff7f
432};
433#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435#define HPT366_DEBUG_DRIVE_INFO 0
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100436#define HPT371_ALLOW_ATA133_6 1
437#define HPT302_ALLOW_ATA133_6 1
438#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100439#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440#define HPT366_ALLOW_ATA66_4 1
441#define HPT366_ALLOW_ATA66_3 1
442#define HPT366_MAX_DEVS 8
443
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100444/* Supported ATA clock frequencies */
445enum ata_clock {
446 ATA_CLOCK_25MHZ,
447 ATA_CLOCK_33MHZ,
448 ATA_CLOCK_40MHZ,
449 ATA_CLOCK_50MHZ,
450 ATA_CLOCK_66MHZ,
451 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700452};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100454struct hpt_timings {
455 u32 pio_mask;
456 u32 dma_mask;
457 u32 ultra_mask;
458 u32 *clock_table[NUM_ATA_CLOCKS];
459};
460
Alan Coxb39b01f2005-06-27 15:24:27 -0700461/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100462 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700463 */
464
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100465struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200466 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100467 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200468 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100469 u8 dpll_clk; /* DPLL clock in MHz */
470 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100471 struct hpt_timings *timings; /* Chipset timing data */
472 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100473};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100474
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100475/* Supported HighPoint chips */
476enum {
477 HPT36x,
478 HPT370,
479 HPT370A,
480 HPT374,
481 HPT372,
482 HPT372A,
483 HPT302,
484 HPT371,
485 HPT372N,
486 HPT302N,
487 HPT371N
488};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100490static struct hpt_timings hpt36x_timings = {
491 .pio_mask = 0xc1f8ffff,
492 .dma_mask = 0x303800ff,
493 .ultra_mask = 0x30070000,
494 .clock_table = {
495 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
496 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
497 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
498 [ATA_CLOCK_50MHZ] = NULL,
499 [ATA_CLOCK_66MHZ] = NULL
500 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100501};
502
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100503static struct hpt_timings hpt37x_timings = {
504 .pio_mask = 0xcfc3ffff,
505 .dma_mask = 0x31c001ff,
506 .ultra_mask = 0x303c0000,
507 .clock_table = {
508 [ATA_CLOCK_25MHZ] = NULL,
509 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
510 [ATA_CLOCK_40MHZ] = NULL,
511 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
512 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
513 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100514};
515
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200516static const struct hpt_info hpt36x __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200517 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100518 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200519 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100520 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100521 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100522};
523
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200524static const struct hpt_info hpt370 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200525 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100526 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200527 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100528 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100529 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100530};
531
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200532static const struct hpt_info hpt370a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200533 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100534 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200535 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100536 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100537 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100538};
539
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200540static const struct hpt_info hpt374 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200541 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100542 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200543 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100544 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100545 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100546};
547
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200548static const struct hpt_info hpt372 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200549 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100550 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200551 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100552 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100553 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100554};
555
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200556static const struct hpt_info hpt372a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200557 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100558 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200559 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100560 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100561 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100562};
563
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200564static const struct hpt_info hpt302 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200565 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100566 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200567 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100568 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100569 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100570};
571
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200572static const struct hpt_info hpt371 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200573 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100574 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200575 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100576 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100577 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100578};
579
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200580static const struct hpt_info hpt372n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200581 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100582 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200583 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100584 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100585 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100586};
587
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200588static const struct hpt_info hpt302n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200589 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100590 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200591 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100592 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100593 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100594};
595
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200596static const struct hpt_info hpt371n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200597 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100598 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200599 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100600 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100601 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100602};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100604static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200606 char *m = (char *)&drive->id[ATA_ID_PROD];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100608 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200609 if (!strcmp(*list++, m))
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100610 return 1;
611 return 0;
612}
Alan Coxb39b01f2005-06-27 15:24:27 -0700613
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200614static struct hpt_info *hpt3xx_get_info(struct device *dev)
615{
616 struct ide_host *host = dev_get_drvdata(dev);
617 struct hpt_info *info = (struct hpt_info *)host->host_priv;
618
619 return dev == host->dev[1] ? info + 1 : info;
620}
621
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200623 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
624 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200626
627static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100629 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200630 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200631 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200633 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200634 case HPT36x:
635 if (!HPT366_ALLOW_ATA66_4 ||
636 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200637 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100638
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200639 if (!HPT366_ALLOW_ATA66_3 ||
640 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200641 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200642 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200643 case HPT370:
644 if (!HPT370_ALLOW_ATA100_5 ||
645 check_in_drive_list(drive, bad_ata100_5))
646 mask = ATA_UDMA4;
647 break;
648 case HPT370A:
649 if (!HPT370_ALLOW_ATA100_5 ||
650 check_in_drive_list(drive, bad_ata100_5))
651 return ATA_UDMA4;
652 case HPT372 :
653 case HPT372A:
654 case HPT372N:
655 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200656 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200657 mask &= ~0x0e;
658 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200659 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200660 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200662
663 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664}
665
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200666static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
667{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100668 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200669 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200670
671 switch (info->chip_type) {
672 case HPT372 :
673 case HPT372A:
674 case HPT372N:
675 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200676 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200677 return 0x00;
678 /* Fall thru */
679 default:
680 return 0x07;
681 }
682}
683
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100684static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800686 int i;
687
688 /*
689 * Lookup the transfer mode table to get the index into
690 * the timing table.
691 *
692 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
693 */
694 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
695 if (xfer_speeds[i] == speed)
696 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100697
698 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699}
700
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100701static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200703 ide_hwif_t *hwif = drive->hwif;
704 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200705 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100706 struct hpt_timings *t = info->timings;
707 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100708 u32 old_itr = 0;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100709 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100710 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
711 (speed < XFER_UDMA_0 ? t->dma_mask :
712 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200713
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100714 pci_read_config_dword(dev, itr_addr, &old_itr);
715 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100717 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
718 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100720 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100722 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723}
724
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200725static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726{
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100727 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728}
729
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100730static void hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200732 char *m = (char *)&drive->id[ATA_ID_PROD];
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100733 const char **list = quirk_drives;
734
735 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200736 if (strstr(m, *list++)) {
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100737 drive->quirk_list = 1;
738 return;
739 }
740
741 drive->quirk_list = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742}
743
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100744static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100746 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100747 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200748 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200750 if (drive->quirk_list == 0)
751 return;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100752
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200753 if (info->chip_type >= HPT370) {
754 u8 scr1 = 0;
755
756 pci_read_config_byte(dev, 0x5a, &scr1);
757 if (((scr1 & 0x10) >> 4) != mask) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100758 if (mask)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200759 scr1 |= 0x10;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100760 else
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200761 scr1 &= ~0x10;
762 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 }
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200764 } else if (mask)
765 disable_irq(hwif->irq);
766 else
767 enable_irq(hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768}
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100771 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 * by HighPoint|Triones Technologies, Inc.
773 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200774static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100776 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100777 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100779 pci_read_config_byte(dev, 0x50, &mcr1);
780 pci_read_config_byte(dev, 0x52, &mcr3);
781 pci_read_config_byte(dev, 0x5a, &scr1);
782 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200783 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100784 if (scr1 & 0x10)
785 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200786 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787}
788
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100789static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100791 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100792 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100793
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100794 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 udelay(10);
796}
797
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100798static void hpt370_irq_timeout(ide_drive_t *drive)
799{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100800 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100801 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100802 u16 bfifo = 0;
803 u8 dma_cmd;
804
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100805 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100806 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
807
808 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200809 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100810 /* stop DMA */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200811 outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100812 hpt370_clear_engine(drive);
813}
814
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200815static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816{
817#ifdef HPT_RESET_STATE_ENGINE
818 hpt370_clear_engine(drive);
819#endif
820 ide_dma_start(drive);
821}
822
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200823static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100825 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200826 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827
828 if (dma_stat & 0x01) {
829 /* wait a little */
830 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200831 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100832 if (dma_stat & 0x01)
833 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 }
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200835 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836}
837
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200838static void hpt370_dma_timeout(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839{
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100840 hpt370_irq_timeout(drive);
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200841 ide_dma_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842}
843
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200845static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100847 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100848 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100850 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100852 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 if (bfifo & 0x1FF) {
854// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
855 return 0;
856 }
857
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200858 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 /* return 1 if INTR asserted */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100860 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 return 1;
862
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 return 0;
864}
865
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200866static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100868 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100869 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100870 u8 mcr = 0, mcr_addr = hwif->select_data;
871 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100873 pci_read_config_byte(dev, 0x6a, &bwsr);
874 pci_read_config_byte(dev, mcr_addr, &mcr);
875 if (bwsr & mask)
876 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200877 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878}
879
880/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800881 * hpt3xxn_set_clock - perform clock switching dance
882 * @hwif: hwif to switch
883 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800885 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800887
888static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100890 unsigned long base = hwif->extra_base;
891 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800892
893 if ((scr2 & 0x7f) == mode)
894 return;
895
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100897 outb(0x80, base + 0x63);
898 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800899
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100901 outb(mode, base + 0x6b);
902 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800903
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100904 /*
905 * Reset the state machines.
906 * NOTE: avoid accidentally enabling the disabled channels.
907 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100908 outb(inb(base + 0x60) | 0x32, base + 0x60);
909 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800910
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100912 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800913
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100915 outb(0x00, base + 0x63);
916 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917}
918
919/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800920 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 * @drive: drive for command
922 * @rq: block request structure
923 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800924 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 * We need it because of the clock switching.
926 */
927
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800928static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100930 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931}
932
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100933/**
934 * hpt37x_calibrate_dpll - calibrate the DPLL
935 * @dev: PCI device
936 *
937 * Perform a calibration cycle on the DPLL.
938 * Returns 1 if this succeeds
939 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200940static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100942 u32 dpll = (f_high << 16) | f_low | 0x100;
943 u8 scr2;
944 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700945
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100946 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700947
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100948 /* Wait for oscillator ready */
949 for(i = 0; i < 0x5000; ++i) {
950 udelay(50);
951 pci_read_config_byte(dev, 0x5b, &scr2);
952 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700953 break;
954 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100955 /* See if it stays ready (we'll just bail out if it's not yet) */
956 for(i = 0; i < 0x1000; ++i) {
957 pci_read_config_byte(dev, 0x5b, &scr2);
958 /* DPLL destabilized? */
959 if(!(scr2 & 0x80))
960 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100961 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100962 /* Turn off tuning, we have the DPLL set */
963 pci_read_config_dword (dev, 0x5c, &dpll);
964 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
965 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700966}
967
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200968static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200969{
970 struct ide_host *host = pci_get_drvdata(dev);
971 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
972 u8 chip_type = info->chip_type;
973 u8 new_mcr, old_mcr = 0;
974
975 /*
976 * Disable the "fast interrupt" prediction. Don't hold off
977 * on interrupts. (== 0x01 despite what the docs say)
978 */
979 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
980
981 if (chip_type >= HPT374)
982 new_mcr = old_mcr & ~0x07;
983 else if (chip_type >= HPT370) {
984 new_mcr = old_mcr;
985 new_mcr &= ~0x02;
986#ifdef HPT_DELAY_INTERRUPT
987 new_mcr &= ~0x01;
988#else
989 new_mcr |= 0x01;
990#endif
991 } else /* HPT366 and HPT368 */
992 new_mcr = old_mcr & ~0x80;
993
994 if (new_mcr != old_mcr)
995 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
996}
997
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200998static unsigned int init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001000 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001001 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +02001002 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001003 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001004 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001005 enum ata_clock clock;
1006
Sergei Shtylyov72931362007-09-11 22:28:35 +02001007 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001008
Alan Coxb39b01f2005-06-27 15:24:27 -07001009 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1010 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1011 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1012 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001014 /*
1015 * First, try to estimate the PCI clock frequency...
1016 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001017 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001018 u8 scr1 = 0;
1019 u16 f_cnt = 0;
1020 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -07001021
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001022 /* Interrupt force enable. */
1023 pci_read_config_byte(dev, 0x5a, &scr1);
1024 if (scr1 & 0x10)
1025 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001026
1027 /*
1028 * HighPoint does this for HPT372A.
1029 * NOTE: This register is only writeable via I/O space.
1030 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001031 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001032 outb(0x0e, io_base + 0x9c);
1033
1034 /*
1035 * Default to PCI clock. Make sure MA15/16 are set to output
1036 * to prevent drives having problems with 40-pin cables.
1037 */
1038 pci_write_config_byte(dev, 0x5b, 0x23);
1039
1040 /*
1041 * We'll have to read f_CNT value in order to determine
1042 * the PCI clock frequency according to the following ratio:
1043 *
1044 * f_CNT = Fpci * 192 / Fdpll
1045 *
1046 * First try reading the register in which the HighPoint BIOS
1047 * saves f_CNT value before reprogramming the DPLL from its
1048 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001049 *
Sergei Shtylyov72931362007-09-11 22:28:35 +02001050 * NOTE: This register is only accessible via I/O space;
1051 * HPT374 BIOS only saves it for the function 0, so we have to
1052 * always read it from there -- no need to check the result of
1053 * pci_get_slot() for the function 0 as the whole device has
1054 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001055 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001056 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1057 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1058 dev->devfn - 1);
1059 unsigned long io_base = pci_resource_start(dev1, 4);
1060
1061 temp = inl(io_base + 0x90);
1062 pci_dev_put(dev1);
1063 } else
1064 temp = inl(io_base + 0x90);
1065
1066 /*
1067 * In case the signature check fails, we'll have to
1068 * resort to reading the f_CNT register itself in hopes
1069 * that nobody has touched the DPLL yet...
1070 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001071 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1072 int i;
1073
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001074 printk(KERN_WARNING "%s %s: no clock data saved by "
1075 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001076
1077 /* Calculate the average value of f_CNT. */
1078 for (temp = i = 0; i < 128; i++) {
1079 pci_read_config_word(dev, 0x78, &f_cnt);
1080 temp += f_cnt & 0x1ff;
1081 mdelay(1);
1082 }
1083 f_cnt = temp / 128;
1084 } else
1085 f_cnt = temp & 0x1ff;
1086
1087 dpll_clk = info->dpll_clk;
1088 pci_clk = (f_cnt * dpll_clk) / 192;
1089
1090 /* Clamp PCI clock to bands. */
1091 if (pci_clk < 40)
1092 pci_clk = 33;
1093 else if(pci_clk < 45)
1094 pci_clk = 40;
1095 else if(pci_clk < 55)
1096 pci_clk = 50;
1097 else
1098 pci_clk = 66;
1099
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001100 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1101 "assuming %d MHz PCI\n", name, pci_name(dev),
1102 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001103 } else {
1104 u32 itr1 = 0;
1105
1106 pci_read_config_dword(dev, 0x40, &itr1);
1107
1108 /* Detect PCI clock by looking at cmd_high_time. */
1109 switch((itr1 >> 8) & 0x07) {
1110 case 0x09:
1111 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001112 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001113 case 0x05:
1114 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001115 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001116 case 0x07:
1117 default:
1118 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001119 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001120 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001121 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001123 /* Let's assume we'll use PCI clock for the ATA clock... */
1124 switch (pci_clk) {
1125 case 25:
1126 clock = ATA_CLOCK_25MHZ;
1127 break;
1128 case 33:
1129 default:
1130 clock = ATA_CLOCK_33MHZ;
1131 break;
1132 case 40:
1133 clock = ATA_CLOCK_40MHZ;
1134 break;
1135 case 50:
1136 clock = ATA_CLOCK_50MHZ;
1137 break;
1138 case 66:
1139 clock = ATA_CLOCK_66MHZ;
1140 break;
1141 }
1142
1143 /*
1144 * Only try the DPLL if we don't have a table for the PCI clock that
1145 * we are running at for HPT370/A, always use it for anything newer...
1146 *
1147 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1148 * We also don't like using the DPLL because this causes glitches
1149 * on PRST-/SRST- when the state engine gets reset...
1150 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001151 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001152 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1153 int adjust;
1154
1155 /*
1156 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1157 * supported/enabled, use 50 MHz DPLL clock otherwise...
1158 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001159 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001160 dpll_clk = 66;
1161 clock = ATA_CLOCK_66MHZ;
1162 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1163 dpll_clk = 50;
1164 clock = ATA_CLOCK_50MHZ;
1165 }
1166
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001167 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001168 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1169 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001170 return -EIO;
1171 }
1172
1173 /* Select the DPLL clock. */
1174 pci_write_config_byte(dev, 0x5b, 0x21);
1175
1176 /*
1177 * Adjust the DPLL based upon PCI clock, enable it,
1178 * and wait for stabilization...
1179 */
1180 f_low = (pci_clk * 48) / dpll_clk;
1181
1182 for (adjust = 0; adjust < 8; adjust++) {
1183 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1184 break;
1185
1186 /*
1187 * See if it'll settle at a fractionally different clock
1188 */
1189 if (adjust & 1)
1190 f_low -= adjust >> 1;
1191 else
1192 f_low += adjust >> 1;
1193 }
1194 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001195 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1196 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001197 return -EIO;
1198 }
1199
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001200 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1201 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001202 } else {
1203 /* Mark the fact that we're not using the DPLL. */
1204 dpll_clk = 0;
1205
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001206 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1207 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001208 }
1209
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001210 /* Store the clock frequencies. */
1211 info->dpll_clk = dpll_clk;
1212 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001213 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001214
Sergei Shtylyov72931362007-09-11 22:28:35 +02001215 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001216 u8 mcr1, mcr4;
1217
1218 /*
1219 * Reset the state engines.
1220 * NOTE: Avoid accidentally enabling the disabled channels.
1221 */
1222 pci_read_config_byte (dev, 0x50, &mcr1);
1223 pci_read_config_byte (dev, 0x54, &mcr4);
1224 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1225 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1226 udelay(100);
1227 }
1228
1229 /*
1230 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1231 * the MISC. register to stretch the UltraDMA Tss timing.
1232 * NOTE: This register is only writeable via I/O space.
1233 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001234 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001235 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1236
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001237 hpt3xx_disable_fast_irq(dev, 0x50);
1238 hpt3xx_disable_fast_irq(dev, 0x54);
1239
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 return dev->irq;
1241}
1242
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001243static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001244{
1245 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001246 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001247 u8 chip_type = info->chip_type;
1248 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1249
1250 /*
1251 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1252 * address lines to access an external EEPROM. To read valid
1253 * cable detect state the pins must be enabled as inputs.
1254 */
1255 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1256 /*
1257 * HPT374 PCI function 1
1258 * - set bit 15 of reg 0x52 to enable TCBLID as input
1259 * - set bit 15 of reg 0x56 to enable FCBLID as input
1260 */
1261 u8 mcr_addr = hwif->select_data + 2;
1262 u16 mcr;
1263
1264 pci_read_config_word(dev, mcr_addr, &mcr);
1265 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1266 /* now read cable id register */
1267 pci_read_config_byte(dev, 0x5a, &scr1);
1268 pci_write_config_word(dev, mcr_addr, mcr);
1269 } else if (chip_type >= HPT370) {
1270 /*
1271 * HPT370/372 and 374 pcifn 0
1272 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1273 */
1274 u8 scr2 = 0;
1275
1276 pci_read_config_byte(dev, 0x5b, &scr2);
1277 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1278 /* now read cable id register */
1279 pci_read_config_byte(dev, 0x5a, &scr1);
1280 pci_write_config_byte(dev, 0x5b, scr2);
1281 } else
1282 pci_read_config_byte(dev, 0x5a, &scr1);
1283
1284 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1285}
1286
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1288{
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001289 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001290 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001291
1292 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001293 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001294
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001295 /*
1296 * HPT3xxN chips have some complications:
1297 *
1298 * - on 33 MHz PCI we must clock switch
1299 * - on 66 MHz PCI we must NOT use the PCI clock
1300 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001301 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001302 /*
1303 * Clock is shared between the channels,
1304 * so we'll have to serialize them... :-(
1305 */
Bartlomiej Zolnierkiewicz702c0262008-12-29 20:27:36 +01001306 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001307 hwif->rw_disk = &hpt3xxn_rw_disk;
1308 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309}
1310
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001311static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1312 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001314 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001315 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1316 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001318 if (base == 0)
1319 return -1;
1320
1321 hwif->dma_base = base;
1322
1323 if (ide_pci_check_simplex(hwif, d) < 0)
1324 return -1;
1325
1326 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001327 return -1;
1328
1329 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330
1331 local_irq_save(flags);
1332
1333 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001334 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1335 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336
1337 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001338 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001340 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341
1342 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001343
1344 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1345 hwif->name, base, base + 7);
1346
1347 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1348
1349 if (ide_allocate_dma_engine(hwif))
1350 return -1;
1351
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001352 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353}
1354
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001355static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001357 if (dev2->irq != dev->irq) {
1358 /* FIXME: we need a core pci_set_interrupt() */
1359 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001360 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001361 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363}
1364
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001365static void __devinit hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366{
Auke Kok44c10132007-06-08 15:46:36 -07001367 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001368
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001369 /*
1370 * HPT371 chips physically have only one channel, the secondary one,
1371 * but the primary channel registers do exist! Go figure...
1372 * So, we manually disable the non-existing channel here
1373 * (if the BIOS hasn't done this already).
1374 */
1375 pci_read_config_byte(dev, 0x50, &mcr1);
1376 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001377 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001378}
1379
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001380static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001381{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001382 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001383
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001384 /*
1385 * Now we'll have to force both channels enabled if
1386 * at least one of them has been enabled by BIOS...
1387 */
1388 pci_read_config_byte(dev, 0x50, &mcr1);
1389 if (mcr1 & 0x30)
1390 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001391
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001392 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1393 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001394
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001395 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001396 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001397 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001398 return 1;
1399 }
1400
1401 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001402}
1403
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001404#define IDE_HFLAGS_HPT3XX \
1405 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001406 IDE_HFLAG_OFF_BOARD)
1407
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001408static const struct ide_port_ops hpt3xx_port_ops = {
1409 .set_pio_mode = hpt3xx_set_pio_mode,
1410 .set_dma_mode = hpt3xx_set_mode,
1411 .quirkproc = hpt3xx_quirkproc,
1412 .maskproc = hpt3xx_maskproc,
1413 .mdma_filter = hpt3xx_mdma_filter,
1414 .udma_filter = hpt3xx_udma_filter,
1415 .cable_detect = hpt3xx_cable_detect,
1416};
1417
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001418static const struct ide_dma_ops hpt37x_dma_ops = {
1419 .dma_host_set = ide_dma_host_set,
1420 .dma_setup = ide_dma_setup,
1421 .dma_exec_cmd = ide_dma_exec_cmd,
1422 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001423 .dma_end = hpt374_dma_end,
1424 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001425 .dma_lost_irq = ide_dma_lost_irq,
1426 .dma_timeout = ide_dma_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001427 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001428};
1429
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001430static const struct ide_dma_ops hpt370_dma_ops = {
1431 .dma_host_set = ide_dma_host_set,
1432 .dma_setup = ide_dma_setup,
1433 .dma_exec_cmd = ide_dma_exec_cmd,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001434 .dma_start = hpt370_dma_start,
1435 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001436 .dma_test_irq = ide_dma_test_irq,
1437 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001438 .dma_timeout = hpt370_dma_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001439 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001440};
1441
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001442static const struct ide_dma_ops hpt36x_dma_ops = {
1443 .dma_host_set = ide_dma_host_set,
1444 .dma_setup = ide_dma_setup,
1445 .dma_exec_cmd = ide_dma_exec_cmd,
1446 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +02001447 .dma_end = ide_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001448 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001449 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001450 .dma_timeout = ide_dma_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001451 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001452};
1453
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +02001454static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001455 { /* 0: HPT36x */
1456 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001457 .init_chipset = init_chipset_hpt366,
1458 .init_hwif = init_hwif_hpt366,
1459 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001460 /*
1461 * HPT36x chips have one channel per function and have
1462 * both channel enable bits located differently and visible
1463 * to both functions -- really stupid design decision... :-(
1464 * Bit 4 is for the primary channel, bit 5 for the secondary.
1465 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001466 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001467 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001468 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001469 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001470 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001471 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001472 },
1473 { /* 1: HPT3xx */
1474 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 .init_hwif = init_hwif_hpt366,
1477 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001478 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001479 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001480 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001481 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001482 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001483 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484 }
1485};
1486
1487/**
1488 * hpt366_init_one - called when an HPT366 is found
1489 * @dev: the hpt366 device
1490 * @id: the matching pci id
1491 *
1492 * Called when the PCI registration layer (or the IDE initialization)
1493 * finds a device matching our IDE device tables.
1494 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1496{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001497 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001498 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001499 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001500 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001501 u8 idx = id->driver_data;
1502 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001503 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001504
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001505 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1506 return -ENODEV;
1507
1508 switch (idx) {
1509 case 0:
1510 if (rev < 3)
1511 info = &hpt36x;
1512 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001513 switch (min_t(u8, rev, 6)) {
1514 case 3: info = &hpt370; break;
1515 case 4: info = &hpt370a; break;
1516 case 5: info = &hpt372; break;
1517 case 6: info = &hpt372n; break;
1518 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001519 idx++;
1520 }
1521 break;
1522 case 1:
1523 info = (rev > 1) ? &hpt372n : &hpt372a;
1524 break;
1525 case 2:
1526 info = (rev > 1) ? &hpt302n : &hpt302;
1527 break;
1528 case 3:
1529 hpt371_init(dev);
1530 info = (rev > 1) ? &hpt371n : &hpt371;
1531 break;
1532 case 4:
1533 info = &hpt374;
1534 break;
1535 case 5:
1536 info = &hpt372n;
1537 break;
1538 }
1539
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001540 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001541
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001542 d = hpt366_chipsets[min_t(u8, idx, 1)];
1543
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001544 d.udma_mask = info->udma_mask;
1545
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001546 /* fixup ->dma_ops for HPT370/HPT370A */
1547 if (info == &hpt370 || info == &hpt370a)
1548 d.dma_ops = &hpt370_dma_ops;
1549
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001550 if (info == &hpt36x || info == &hpt374)
1551 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1552
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001553 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1554 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001555 printk(KERN_ERR "%s %s: out of memory!\n",
1556 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001557 pci_dev_put(dev2);
1558 return -ENOMEM;
1559 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001560
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001561 /*
1562 * Copy everything from a static "template" structure
1563 * to just allocated per-chip hpt_info structure.
1564 */
1565 memcpy(dyn_info, info, sizeof(*dyn_info));
1566
1567 if (dev2) {
1568 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001569
1570 if (info == &hpt374)
1571 hpt374_init(dev, dev2);
1572 else {
1573 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001574 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001575 }
1576
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001577 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1578 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001579 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001580 kfree(dyn_info);
1581 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001582 return ret;
1583 }
1584
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001585 ret = ide_pci_init_one(dev, &d, dyn_info);
1586 if (ret < 0)
1587 kfree(dyn_info);
1588
1589 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590}
1591
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001592static void __devexit hpt366_remove(struct pci_dev *dev)
1593{
1594 struct ide_host *host = pci_get_drvdata(dev);
1595 struct ide_info *info = host->host_priv;
1596 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1597
1598 ide_pci_remove(dev);
1599 pci_dev_put(dev2);
1600 kfree(info);
1601}
1602
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001603static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001604 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1605 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610 { 0, },
1611};
1612MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1613
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001614static struct pci_driver hpt366_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615 .name = "HPT366_IDE",
1616 .id_table = hpt366_pci_tbl,
1617 .probe = hpt366_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +02001618 .remove = __devexit_p(hpt366_remove),
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +02001619 .suspend = ide_pci_suspend,
1620 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621};
1622
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001623static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001625 return ide_pci_register_driver(&hpt366_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626}
1627
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001628static void __exit hpt366_ide_exit(void)
1629{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001630 pci_unregister_driver(&hpt366_pci_driver);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001631}
1632
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001634module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001635
1636MODULE_AUTHOR("Andre Hedrick");
1637MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1638MODULE_LICENSE("GPL");