Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 2 of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * Ported to libata by: |
| 10 | * Albert Lee <albertcc@tw.ibm.com> IBM Corporation |
| 11 | * |
| 12 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> |
| 13 | * Portions Copyright (C) 1999 Promise Technology, Inc. |
| 14 | * |
| 15 | * Author: Frank Tiernan (frankt@promise.com) |
| 16 | * Released under terms of General Public License |
| 17 | * |
| 18 | * |
| 19 | * libata documentation is available via 'make {ps|pdf}docs', |
| 20 | * as Documentation/DocBook/libata.* |
| 21 | * |
| 22 | * Hardware information only available under NDA. |
| 23 | * |
| 24 | */ |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/blkdev.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/device.h> |
| 32 | #include <scsi/scsi.h> |
| 33 | #include <scsi/scsi_host.h> |
| 34 | #include <scsi/scsi_cmnd.h> |
| 35 | #include <linux/libata.h> |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 36 | |
| 37 | #define DRV_NAME "pata_pdc2027x" |
Jeff Garzik | 2a3103c | 2007-08-31 04:54:06 -0400 | [diff] [blame] | 38 | #define DRV_VERSION "1.0" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 39 | #undef PDC_DEBUG |
| 40 | |
| 41 | #ifdef PDC_DEBUG |
| 42 | #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) |
| 43 | #else |
| 44 | #define PDPRINTK(fmt, args...) |
| 45 | #endif |
| 46 | |
| 47 | enum { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 48 | PDC_MMIO_BAR = 5, |
| 49 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 50 | PDC_UDMA_100 = 0, |
| 51 | PDC_UDMA_133 = 1, |
| 52 | |
| 53 | PDC_100_MHZ = 100000000, |
| 54 | PDC_133_MHZ = 133333333, |
| 55 | |
| 56 | PDC_SYS_CTL = 0x1100, |
| 57 | PDC_ATA_CTL = 0x1104, |
| 58 | PDC_GLOBAL_CTL = 0x1108, |
| 59 | PDC_CTCR0 = 0x110C, |
| 60 | PDC_CTCR1 = 0x1110, |
| 61 | PDC_BYTE_COUNT = 0x1120, |
| 62 | PDC_PLL_CTL = 0x1202, |
| 63 | }; |
| 64 | |
| 65 | static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 66 | static void pdc2027x_error_handler(struct ata_port *ap); |
| 67 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); |
| 68 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 69 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 70 | static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); |
| 71 | static int pdc2027x_cable_detect(struct ata_port *ap); |
| 72 | static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * ATA Timing Tables based on 133MHz controller clock. |
| 76 | * These tables are only used when the controller is in 133MHz clock. |
| 77 | * If the controller is in 100MHz clock, the ASIC hardware will |
| 78 | * set the timing registers automatically when "set feature" command |
| 79 | * is issued to the device. However, if the controller clock is 133MHz, |
| 80 | * the following tables must be used. |
| 81 | */ |
| 82 | static struct pdc2027x_pio_timing { |
| 83 | u8 value0, value1, value2; |
| 84 | } pdc2027x_pio_timing_tbl [] = { |
| 85 | { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ |
| 86 | { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ |
| 87 | { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ |
| 88 | { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ |
| 89 | { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ |
| 90 | }; |
| 91 | |
| 92 | static struct pdc2027x_mdma_timing { |
| 93 | u8 value0, value1; |
| 94 | } pdc2027x_mdma_timing_tbl [] = { |
| 95 | { 0xdf, 0x5f }, /* MDMA mode 0 */ |
| 96 | { 0x6b, 0x27 }, /* MDMA mode 1 */ |
| 97 | { 0x69, 0x25 }, /* MDMA mode 2 */ |
| 98 | }; |
| 99 | |
| 100 | static struct pdc2027x_udma_timing { |
| 101 | u8 value0, value1, value2; |
| 102 | } pdc2027x_udma_timing_tbl [] = { |
| 103 | { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ |
| 104 | { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ |
| 105 | { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ |
| 106 | { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ |
| 107 | { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ |
| 108 | { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ |
| 109 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ |
| 110 | }; |
| 111 | |
| 112 | static const struct pci_device_id pdc2027x_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 113 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, |
| 114 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, |
| 115 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, |
| 116 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, |
| 117 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, |
| 118 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, |
| 119 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, |
| 120 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 121 | { } /* terminate list */ |
| 122 | }; |
| 123 | |
| 124 | static struct pci_driver pdc2027x_pci_driver = { |
| 125 | .name = DRV_NAME, |
| 126 | .id_table = pdc2027x_pci_tbl, |
| 127 | .probe = pdc2027x_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 128 | .remove = ata_pci_remove_one, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static struct scsi_host_template pdc2027x_sht = { |
| 132 | .module = THIS_MODULE, |
| 133 | .name = DRV_NAME, |
| 134 | .ioctl = ata_scsi_ioctl, |
| 135 | .queuecommand = ata_scsi_queuecmd, |
| 136 | .can_queue = ATA_DEF_QUEUE, |
| 137 | .this_id = ATA_SHT_THIS_ID, |
| 138 | .sg_tablesize = LIBATA_MAX_PRD, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 139 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 140 | .emulated = ATA_SHT_EMULATED, |
| 141 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 142 | .proc_name = DRV_NAME, |
| 143 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 144 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | afdfe89 | 2006-11-29 11:26:47 +0900 | [diff] [blame] | 145 | .slave_destroy = ata_scsi_slave_destroy, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 146 | .bios_param = ata_std_bios_param, |
| 147 | }; |
| 148 | |
| 149 | static struct ata_port_operations pdc2027x_pata100_ops = { |
| 150 | .port_disable = ata_port_disable, |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 151 | .mode_filter = ata_pci_default_filter, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 152 | |
| 153 | .tf_load = ata_tf_load, |
| 154 | .tf_read = ata_tf_read, |
| 155 | .check_status = ata_check_status, |
| 156 | .exec_command = ata_exec_command, |
| 157 | .dev_select = ata_std_dev_select, |
| 158 | |
| 159 | .check_atapi_dma = pdc2027x_check_atapi_dma, |
| 160 | .bmdma_setup = ata_bmdma_setup, |
| 161 | .bmdma_start = ata_bmdma_start, |
| 162 | .bmdma_stop = ata_bmdma_stop, |
| 163 | .bmdma_status = ata_bmdma_status, |
| 164 | .qc_prep = ata_qc_prep, |
| 165 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 166 | .data_xfer = ata_data_xfer, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 167 | |
| 168 | .freeze = ata_bmdma_freeze, |
| 169 | .thaw = ata_bmdma_thaw, |
| 170 | .error_handler = pdc2027x_error_handler, |
| 171 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 172 | .cable_detect = pdc2027x_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 173 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 174 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 175 | .irq_on = ata_irq_on, |
| 176 | .irq_ack = ata_irq_ack, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 177 | |
| 178 | .port_start = ata_port_start, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | static struct ata_port_operations pdc2027x_pata133_ops = { |
| 182 | .port_disable = ata_port_disable, |
| 183 | .set_piomode = pdc2027x_set_piomode, |
| 184 | .set_dmamode = pdc2027x_set_dmamode, |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 185 | .set_mode = pdc2027x_set_mode, |
| 186 | .mode_filter = pdc2027x_mode_filter, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 187 | |
| 188 | .tf_load = ata_tf_load, |
| 189 | .tf_read = ata_tf_read, |
| 190 | .check_status = ata_check_status, |
| 191 | .exec_command = ata_exec_command, |
| 192 | .dev_select = ata_std_dev_select, |
| 193 | |
| 194 | .check_atapi_dma = pdc2027x_check_atapi_dma, |
| 195 | .bmdma_setup = ata_bmdma_setup, |
| 196 | .bmdma_start = ata_bmdma_start, |
| 197 | .bmdma_stop = ata_bmdma_stop, |
| 198 | .bmdma_status = ata_bmdma_status, |
| 199 | .qc_prep = ata_qc_prep, |
| 200 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 201 | .data_xfer = ata_data_xfer, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 202 | |
| 203 | .freeze = ata_bmdma_freeze, |
| 204 | .thaw = ata_bmdma_thaw, |
| 205 | .error_handler = pdc2027x_error_handler, |
| 206 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 207 | .cable_detect = pdc2027x_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 208 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 209 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 210 | .irq_on = ata_irq_on, |
| 211 | .irq_ack = ata_irq_ack, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 212 | |
| 213 | .port_start = ata_port_start, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | static struct ata_port_info pdc2027x_port_info[] = { |
| 217 | /* PDC_UDMA_100 */ |
| 218 | { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 219 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | |
| 220 | ATA_FLAG_MMIO, |
| 221 | .pio_mask = 0x1f, /* pio0-4 */ |
| 222 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 223 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
| 224 | .port_ops = &pdc2027x_pata100_ops, |
| 225 | }, |
| 226 | /* PDC_UDMA_133 */ |
| 227 | { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 228 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | |
| 229 | ATA_FLAG_MMIO, |
| 230 | .pio_mask = 0x1f, /* pio0-4 */ |
| 231 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 232 | .udma_mask = ATA_UDMA6, /* udma0-6 */ |
| 233 | .port_ops = &pdc2027x_pata133_ops, |
| 234 | }, |
| 235 | }; |
| 236 | |
| 237 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); |
| 238 | MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); |
| 239 | MODULE_LICENSE("GPL"); |
| 240 | MODULE_VERSION(DRV_VERSION); |
| 241 | MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); |
| 242 | |
| 243 | /** |
| 244 | * port_mmio - Get the MMIO address of PDC2027x extended registers |
| 245 | * @ap: Port |
| 246 | * @offset: offset from mmio base |
| 247 | */ |
Al Viro | 7c25041 | 2006-09-25 02:57:57 +0100 | [diff] [blame] | 248 | static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 249 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 250 | return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | /** |
| 254 | * dev_mmio - Get the MMIO address of PDC2027x extended registers |
| 255 | * @ap: Port |
| 256 | * @adev: device |
| 257 | * @offset: offset from mmio base |
| 258 | */ |
Al Viro | 7c25041 | 2006-09-25 02:57:57 +0100 | [diff] [blame] | 259 | static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 260 | { |
| 261 | u8 adj = (adev->devno) ? 0x08 : 0x00; |
| 262 | return port_mmio(ap, offset) + adj; |
| 263 | } |
| 264 | |
| 265 | /** |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 266 | * pdc2027x_pata_cable_detect - Probe host controller cable detect info |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 267 | * @ap: Port for which cable detect info is desired |
| 268 | * |
| 269 | * Read 80c cable indicator from Promise extended register. |
| 270 | * This register is latched when the system is reset. |
| 271 | * |
| 272 | * LOCKING: |
| 273 | * None (inherited from caller). |
| 274 | */ |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 275 | static int pdc2027x_cable_detect(struct ata_port *ap) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 276 | { |
| 277 | u32 cgcr; |
| 278 | |
| 279 | /* check cable detect results */ |
| 280 | cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL)); |
| 281 | if (cgcr & (1 << 26)) |
| 282 | goto cbl40; |
| 283 | |
| 284 | PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); |
| 285 | |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 286 | return ATA_CBL_PATA80; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 287 | cbl40: |
| 288 | printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 289 | return ATA_CBL_PATA40; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | /** |
| 293 | * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. |
| 294 | * @ap: Port to check |
| 295 | */ |
| 296 | static inline int pdc2027x_port_enabled(struct ata_port *ap) |
| 297 | { |
| 298 | return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02; |
| 299 | } |
| 300 | |
| 301 | /** |
| 302 | * pdc2027x_prereset - prereset for PATA host controller |
| 303 | * @ap: Target port |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 304 | * @deadline: deadline jiffies for the operation |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 305 | * |
| 306 | * Probeinit including cable detection. |
| 307 | * |
| 308 | * LOCKING: |
| 309 | * None (inherited from caller). |
| 310 | */ |
| 311 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 312 | static int pdc2027x_prereset(struct ata_port *ap, unsigned long deadline) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 313 | { |
| 314 | /* Check whether port enabled */ |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 315 | if (!pdc2027x_port_enabled(ap)) |
| 316 | return -ENOENT; |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 317 | return ata_std_prereset(ap, deadline); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | /** |
| 321 | * pdc2027x_error_handler - Perform reset on PATA port and classify |
| 322 | * @ap: Port to reset |
| 323 | * |
| 324 | * Reset PATA phy and classify attached devices. |
| 325 | * |
| 326 | * LOCKING: |
| 327 | * None (inherited from caller). |
| 328 | */ |
| 329 | |
| 330 | static void pdc2027x_error_handler(struct ata_port *ap) |
| 331 | { |
| 332 | ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset); |
| 333 | } |
| 334 | |
| 335 | /** |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 336 | * pdc2720x_mode_filter - mode selection filter |
| 337 | * @adev: ATA device |
| 338 | * @mask: list of modes proposed |
| 339 | * |
| 340 | * Block UDMA on devices that cause trouble with this controller. |
| 341 | */ |
| 342 | |
| 343 | static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) |
| 344 | { |
| 345 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
| 346 | struct ata_device *pair = ata_dev_pair(adev); |
| 347 | |
| 348 | if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) |
| 349 | return ata_pci_default_filter(adev, mask); |
| 350 | |
| 351 | /* Check for slave of a Maxtor at UDMA6 */ |
| 352 | ata_id_c_string(pair->id, model_num, ATA_ID_PROD, |
| 353 | ATA_ID_PROD_LEN + 1); |
| 354 | /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ |
| 355 | if(strstr(model_num, "Maxtor") == 0 && pair->dma_mode == XFER_UDMA_6) |
| 356 | mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); |
| 357 | |
| 358 | return ata_pci_default_filter(adev, mask); |
| 359 | } |
| 360 | |
| 361 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 362 | * pdc2027x_set_piomode - Initialize host controller PATA PIO timings |
| 363 | * @ap: Port to configure |
| 364 | * @adev: um |
| 365 | * @pio: PIO mode, 0 - 4 |
| 366 | * |
| 367 | * Set PIO mode for device. |
| 368 | * |
| 369 | * LOCKING: |
| 370 | * None (inherited from caller). |
| 371 | */ |
| 372 | |
| 373 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 374 | { |
| 375 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
| 376 | u32 ctcr0, ctcr1; |
| 377 | |
| 378 | PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); |
| 379 | |
| 380 | /* Sanity check */ |
| 381 | if (pio > 4) { |
| 382 | printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); |
| 383 | return; |
| 384 | |
| 385 | } |
| 386 | |
| 387 | /* Set the PIO timing registers using value table for 133MHz */ |
| 388 | PDPRINTK("Set pio regs... \n"); |
| 389 | |
| 390 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); |
| 391 | ctcr0 &= 0xffff0000; |
| 392 | ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | |
| 393 | (pdc2027x_pio_timing_tbl[pio].value1 << 8); |
| 394 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); |
| 395 | |
| 396 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); |
| 397 | ctcr1 &= 0x00ffffff; |
| 398 | ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); |
| 399 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); |
| 400 | |
| 401 | PDPRINTK("Set pio regs done\n"); |
| 402 | |
| 403 | PDPRINTK("Set to pio mode[%u] \n", pio); |
| 404 | } |
| 405 | |
| 406 | /** |
| 407 | * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings |
| 408 | * @ap: Port to configure |
| 409 | * @adev: um |
| 410 | * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6 |
| 411 | * |
| 412 | * Set UDMA mode for device. |
| 413 | * |
| 414 | * LOCKING: |
| 415 | * None (inherited from caller). |
| 416 | */ |
| 417 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
| 418 | { |
| 419 | unsigned int dma_mode = adev->dma_mode; |
| 420 | u32 ctcr0, ctcr1; |
| 421 | |
| 422 | if ((dma_mode >= XFER_UDMA_0) && |
| 423 | (dma_mode <= XFER_UDMA_6)) { |
| 424 | /* Set the UDMA timing registers with value table for 133MHz */ |
| 425 | unsigned int udma_mode = dma_mode & 0x07; |
| 426 | |
| 427 | if (dma_mode == XFER_UDMA_2) { |
| 428 | /* |
| 429 | * Turn off tHOLD. |
| 430 | * If tHOLD is '1', the hardware will add half clock for data hold time. |
| 431 | * This code segment seems to be no effect. tHOLD will be overwritten below. |
| 432 | */ |
| 433 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); |
| 434 | writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); |
| 435 | } |
| 436 | |
| 437 | PDPRINTK("Set udma regs... \n"); |
| 438 | |
| 439 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); |
| 440 | ctcr1 &= 0xff000000; |
| 441 | ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | |
| 442 | (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | |
| 443 | (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); |
| 444 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); |
| 445 | |
| 446 | PDPRINTK("Set udma regs done\n"); |
| 447 | |
| 448 | PDPRINTK("Set to udma mode[%u] \n", udma_mode); |
| 449 | |
| 450 | } else if ((dma_mode >= XFER_MW_DMA_0) && |
| 451 | (dma_mode <= XFER_MW_DMA_2)) { |
| 452 | /* Set the MDMA timing registers with value table for 133MHz */ |
| 453 | unsigned int mdma_mode = dma_mode & 0x07; |
| 454 | |
| 455 | PDPRINTK("Set mdma regs... \n"); |
| 456 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); |
| 457 | |
| 458 | ctcr0 &= 0x0000ffff; |
| 459 | ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | |
| 460 | (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); |
| 461 | |
| 462 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); |
| 463 | PDPRINTK("Set mdma regs done\n"); |
| 464 | |
| 465 | PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); |
| 466 | } else { |
| 467 | printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | /** |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 472 | * pdc2027x_set_mode - Set the timing registers back to correct values. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 473 | * @ap: Port to configure |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 474 | * @r_failed: Returned device for failure |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 475 | * |
| 476 | * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers |
| 477 | * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. |
| 478 | * This function overwrites the possibly incorrect values set by the hardware to be correct. |
| 479 | */ |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 480 | static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 481 | { |
| 482 | int i; |
| 483 | |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 484 | i = ata_do_set_mode(ap, r_failed); |
| 485 | if (i < 0) |
| 486 | return i; |
| 487 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 488 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| 489 | struct ata_device *dev = &ap->device[i]; |
| 490 | |
| 491 | if (ata_dev_enabled(dev)) { |
| 492 | |
| 493 | pdc2027x_set_piomode(ap, dev); |
| 494 | |
| 495 | /* |
| 496 | * Enable prefetch if the device support PIO only. |
| 497 | */ |
| 498 | if (dev->xfer_shift == ATA_SHIFT_PIO) { |
| 499 | u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1)); |
| 500 | ctcr1 |= (1 << 25); |
| 501 | writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); |
| 502 | |
| 503 | PDPRINTK("Turn on prefetch\n"); |
| 504 | } else { |
| 505 | pdc2027x_set_dmamode(ap, dev); |
| 506 | } |
| 507 | } |
| 508 | } |
Alan Cox | 9bedb79 | 2007-04-11 00:19:00 +0100 | [diff] [blame] | 509 | return 0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | /** |
| 513 | * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command |
| 514 | * @qc: Metadata associated with taskfile to check |
| 515 | * |
| 516 | * LOCKING: |
| 517 | * None (inherited from caller). |
| 518 | * |
| 519 | * RETURNS: 0 when ATAPI DMA can be used |
| 520 | * 1 otherwise |
| 521 | */ |
| 522 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) |
| 523 | { |
| 524 | struct scsi_cmnd *cmd = qc->scsicmd; |
| 525 | u8 *scsicmd = cmd->cmnd; |
| 526 | int rc = 1; /* atapi dma off by default */ |
| 527 | |
| 528 | /* |
| 529 | * This workaround is from Promise's GPL driver. |
| 530 | * If ATAPI DMA is used for commands not in the |
| 531 | * following white list, say MODE_SENSE and REQUEST_SENSE, |
| 532 | * pdc2027x might hit the irq lost problem. |
| 533 | */ |
| 534 | switch (scsicmd[0]) { |
| 535 | case READ_10: |
| 536 | case WRITE_10: |
| 537 | case READ_12: |
| 538 | case WRITE_12: |
| 539 | case READ_6: |
| 540 | case WRITE_6: |
| 541 | case 0xad: /* READ_DVD_STRUCTURE */ |
| 542 | case 0xbe: /* READ_CD */ |
| 543 | /* ATAPI DMA is ok */ |
| 544 | rc = 0; |
| 545 | break; |
| 546 | default: |
| 547 | ; |
| 548 | } |
| 549 | |
| 550 | return rc; |
| 551 | } |
| 552 | |
| 553 | /** |
| 554 | * pdc_read_counter - Read the ctr counter |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 555 | * @host: target ATA host |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 556 | */ |
| 557 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 558 | static long pdc_read_counter(struct ata_host *host) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 559 | { |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 560 | void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 561 | long counter; |
| 562 | int retry = 1; |
| 563 | u32 bccrl, bccrh, bccrlv, bccrhv; |
| 564 | |
| 565 | retry: |
Mikael Pettersson | 78c4af0 | 2007-08-18 22:58:53 +0200 | [diff] [blame] | 566 | bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff; |
| 567 | bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 568 | rmb(); |
| 569 | |
| 570 | /* Read the counter values again for verification */ |
Mikael Pettersson | 78c4af0 | 2007-08-18 22:58:53 +0200 | [diff] [blame] | 571 | bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff; |
| 572 | bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 573 | rmb(); |
| 574 | |
| 575 | counter = (bccrh << 15) | bccrl; |
| 576 | |
| 577 | PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); |
| 578 | PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); |
| 579 | |
| 580 | /* |
| 581 | * The 30-bit decreasing counter are read by 2 pieces. |
| 582 | * Incorrect value may be read when both bccrh and bccrl are changing. |
| 583 | * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. |
| 584 | */ |
| 585 | if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { |
| 586 | retry--; |
| 587 | PDPRINTK("rereading counter\n"); |
| 588 | goto retry; |
| 589 | } |
| 590 | |
| 591 | return counter; |
| 592 | } |
| 593 | |
| 594 | /** |
| 595 | * adjust_pll - Adjust the PLL input clock in Hz. |
| 596 | * |
| 597 | * @pdc_controller: controller specific information |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 598 | * @host: target ATA host |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 599 | * @pll_clock: The input of PLL in HZ |
| 600 | */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 601 | static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 602 | { |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 603 | void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 604 | u16 pll_ctl; |
| 605 | long pll_clock_khz = pll_clock / 1000; |
| 606 | long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; |
| 607 | long ratio = pout_required / pll_clock_khz; |
| 608 | int F, R; |
| 609 | |
| 610 | /* Sanity check */ |
| 611 | if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { |
| 612 | printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); |
| 613 | return; |
| 614 | } |
| 615 | |
| 616 | #ifdef PDC_DEBUG |
| 617 | PDPRINTK("pout_required is %ld\n", pout_required); |
| 618 | |
| 619 | /* Show the current clock value of PLL control register |
| 620 | * (maybe already configured by the firmware) |
| 621 | */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 622 | pll_ctl = readw(mmio_base + PDC_PLL_CTL); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 623 | |
| 624 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
| 625 | #endif |
| 626 | |
| 627 | /* |
| 628 | * Calculate the ratio of F, R and OD |
| 629 | * POUT = (F + 2) / (( R + 2) * NO) |
| 630 | */ |
| 631 | if (ratio < 8600L) { /* 8.6x */ |
| 632 | /* Using NO = 0x01, R = 0x0D */ |
| 633 | R = 0x0d; |
| 634 | } else if (ratio < 12900L) { /* 12.9x */ |
| 635 | /* Using NO = 0x01, R = 0x08 */ |
| 636 | R = 0x08; |
| 637 | } else if (ratio < 16100L) { /* 16.1x */ |
| 638 | /* Using NO = 0x01, R = 0x06 */ |
| 639 | R = 0x06; |
| 640 | } else if (ratio < 64000L) { /* 64x */ |
| 641 | R = 0x00; |
| 642 | } else { |
| 643 | /* Invalid ratio */ |
| 644 | printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); |
| 645 | return; |
| 646 | } |
| 647 | |
| 648 | F = (ratio * (R+2)) / 1000 - 2; |
| 649 | |
| 650 | if (unlikely(F < 0 || F > 127)) { |
| 651 | /* Invalid F */ |
| 652 | printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); |
| 653 | return; |
| 654 | } |
| 655 | |
| 656 | PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); |
| 657 | |
| 658 | pll_ctl = (R << 8) | F; |
| 659 | |
| 660 | PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); |
| 661 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 662 | writew(pll_ctl, mmio_base + PDC_PLL_CTL); |
| 663 | readw(mmio_base + PDC_PLL_CTL); /* flush */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 664 | |
| 665 | /* Wait the PLL circuit to be stable */ |
| 666 | mdelay(30); |
| 667 | |
| 668 | #ifdef PDC_DEBUG |
| 669 | /* |
| 670 | * Show the current clock value of PLL control register |
| 671 | * (maybe configured by the firmware) |
| 672 | */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 673 | pll_ctl = readw(mmio_base + PDC_PLL_CTL); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 674 | |
| 675 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
| 676 | #endif |
| 677 | |
| 678 | return; |
| 679 | } |
| 680 | |
| 681 | /** |
| 682 | * detect_pll_input_clock - Detect the PLL input clock in Hz. |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 683 | * @host: target ATA host |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 684 | * Ex. 16949000 on 33MHz PCI bus for pdc20275. |
| 685 | * Half of the PCI clock. |
| 686 | */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 687 | static long pdc_detect_pll_input_clock(struct ata_host *host) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 688 | { |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 689 | void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 690 | u32 scr; |
| 691 | long start_count, end_count; |
Albert Lee | 8c781bf | 2007-06-26 13:43:15 +0800 | [diff] [blame] | 692 | struct timeval start_time, end_time; |
| 693 | long pll_clock, usec_elapsed; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 694 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 695 | /* Start the test mode */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 696 | scr = readl(mmio_base + PDC_SYS_CTL); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 697 | PDPRINTK("scr[%X]\n", scr); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 698 | writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); |
| 699 | readl(mmio_base + PDC_SYS_CTL); /* flush */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 700 | |
Mikael Pettersson | 78c4af0 | 2007-08-18 22:58:53 +0200 | [diff] [blame] | 701 | /* Read current counter value */ |
| 702 | start_count = pdc_read_counter(host); |
| 703 | do_gettimeofday(&start_time); |
| 704 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 705 | /* Let the counter run for 100 ms. */ |
| 706 | mdelay(100); |
| 707 | |
| 708 | /* Read the counter values again */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 709 | end_count = pdc_read_counter(host); |
Albert Lee | 8c781bf | 2007-06-26 13:43:15 +0800 | [diff] [blame] | 710 | do_gettimeofday(&end_time); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 711 | |
| 712 | /* Stop the test mode */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 713 | scr = readl(mmio_base + PDC_SYS_CTL); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 714 | PDPRINTK("scr[%X]\n", scr); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 715 | writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); |
| 716 | readl(mmio_base + PDC_SYS_CTL); /* flush */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 717 | |
| 718 | /* calculate the input clock in Hz */ |
Albert Lee | 8c781bf | 2007-06-26 13:43:15 +0800 | [diff] [blame] | 719 | usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 + |
| 720 | (end_time.tv_usec - start_time.tv_usec); |
| 721 | |
Mikael Pettersson | 78c4af0 | 2007-08-18 22:58:53 +0200 | [diff] [blame] | 722 | pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * |
Albert Lee | 8c781bf | 2007-06-26 13:43:15 +0800 | [diff] [blame] | 723 | (100000000 / usec_elapsed); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 724 | |
| 725 | PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); |
| 726 | PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); |
| 727 | |
| 728 | return pll_clock; |
| 729 | } |
| 730 | |
| 731 | /** |
| 732 | * pdc_hardware_init - Initialize the hardware. |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 733 | * @host: target ATA host |
| 734 | * @board_idx: board identifier |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 735 | */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 736 | static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 737 | { |
| 738 | long pll_clock; |
| 739 | |
| 740 | /* |
| 741 | * Detect PLL input clock rate. |
| 742 | * On some system, where PCI bus is running at non-standard clock rate. |
| 743 | * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. |
| 744 | * The pdc20275 controller employs PLL circuit to help correct timing registers setting. |
| 745 | */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 746 | pll_clock = pdc_detect_pll_input_clock(host); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 747 | |
| 748 | if (pll_clock < 0) /* counter overflow? Try again. */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 749 | pll_clock = pdc_detect_pll_input_clock(host); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 750 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 751 | dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 752 | |
| 753 | /* Adjust PLL control register */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 754 | pdc_adjust_pll(host, pll_clock, board_idx); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 755 | |
| 756 | return 0; |
| 757 | } |
| 758 | |
| 759 | /** |
| 760 | * pdc_ata_setup_port - setup the mmio address |
| 761 | * @port: ata ioports to setup |
| 762 | * @base: base address |
| 763 | */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 764 | static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 765 | { |
| 766 | port->cmd_addr = |
| 767 | port->data_addr = base; |
| 768 | port->feature_addr = |
| 769 | port->error_addr = base + 0x05; |
| 770 | port->nsect_addr = base + 0x0a; |
| 771 | port->lbal_addr = base + 0x0f; |
| 772 | port->lbam_addr = base + 0x10; |
| 773 | port->lbah_addr = base + 0x15; |
| 774 | port->device_addr = base + 0x1a; |
| 775 | port->command_addr = |
| 776 | port->status_addr = base + 0x1f; |
| 777 | port->altstatus_addr = |
| 778 | port->ctl_addr = base + 0x81a; |
| 779 | } |
| 780 | |
| 781 | /** |
| 782 | * pdc2027x_init_one - PCI probe function |
| 783 | * Called when an instance of PCI adapter is inserted. |
| 784 | * This function checks whether the hardware is supported, |
| 785 | * initialize hardware and register an instance of ata_host to |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 786 | * libata. (implements struct pci_driver.probe() ) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 787 | * |
| 788 | * @pdev: instance of pci_dev found |
| 789 | * @ent: matching entry in the id_tbl[] |
| 790 | */ |
| 791 | static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 792 | { |
| 793 | static int printed_version; |
| 794 | unsigned int board_idx = (unsigned int) ent->driver_data; |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 795 | const struct ata_port_info *ppi[] = |
| 796 | { &pdc2027x_port_info[board_idx], NULL }; |
| 797 | struct ata_host *host; |
Al Viro | 7c25041 | 2006-09-25 02:57:57 +0100 | [diff] [blame] | 798 | void __iomem *mmio_base; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 799 | int rc; |
| 800 | |
| 801 | if (!printed_version++) |
| 802 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
| 803 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 804 | /* alloc host */ |
| 805 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); |
| 806 | if (!host) |
| 807 | return -ENOMEM; |
| 808 | |
| 809 | /* acquire resources and fill host */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 810 | rc = pcim_enable_device(pdev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 811 | if (rc) |
| 812 | return rc; |
| 813 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 814 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 815 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 816 | return rc; |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 817 | host->iomap = pcim_iomap_table(pdev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 818 | |
| 819 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
| 820 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 821 | return rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 822 | |
| 823 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
| 824 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 825 | return rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 826 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 827 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 828 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 829 | pdc_ata_setup_port(&host->ports[0]->ioaddr, mmio_base + 0x17c0); |
| 830 | host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x1000; |
| 831 | pdc_ata_setup_port(&host->ports[1]->ioaddr, mmio_base + 0x15c0); |
| 832 | host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x1008; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 833 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 834 | //pci_enable_intx(pdev); |
| 835 | |
| 836 | /* initialize adapter */ |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 837 | if (pdc_hardware_init(host, board_idx) != 0) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 838 | return -EIO; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 839 | |
Tejun Heo | 5d72882 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 840 | pci_set_master(pdev); |
| 841 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
| 842 | &pdc2027x_sht); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 843 | } |
| 844 | |
| 845 | /** |
| 846 | * pdc2027x_init - Called after this module is loaded into the kernel. |
| 847 | */ |
| 848 | static int __init pdc2027x_init(void) |
| 849 | { |
Henrik Kretzschmar | 72dc679 | 2006-10-10 14:29:24 -0700 | [diff] [blame] | 850 | return pci_register_driver(&pdc2027x_pci_driver); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 851 | } |
| 852 | |
| 853 | /** |
| 854 | * pdc2027x_exit - Called before this module unloaded from the kernel |
| 855 | */ |
| 856 | static void __exit pdc2027x_exit(void) |
| 857 | { |
| 858 | pci_unregister_driver(&pdc2027x_pci_driver); |
| 859 | } |
| 860 | |
| 861 | module_init(pdc2027x_init); |
| 862 | module_exit(pdc2027x_exit); |