Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Low-level exception handling code |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> |
| 6 | * Will Deacon <will.deacon@arm.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/linkage.h> |
| 23 | |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 24 | #include <asm/alternative.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 25 | #include <asm/assembler.h> |
| 26 | #include <asm/asm-offsets.h> |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 27 | #include <asm/cpufeature.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 28 | #include <asm/errno.h> |
Marc Zyngier | 5c1ce6f | 2013-04-08 17:17:03 +0100 | [diff] [blame] | 29 | #include <asm/esr.h> |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 30 | #include <asm/irq.h> |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 31 | #include <asm/memory.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 32 | #include <asm/ptrace.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 33 | #include <asm/thread_info.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 34 | #include <asm/uaccess.h> |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 35 | #include <asm/asm-uaccess.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 36 | #include <asm/unistd.h> |
| 37 | |
| 38 | /* |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 39 | * Context tracking subsystem. Used to instrument transitions |
| 40 | * between user and kernel mode. |
| 41 | */ |
| 42 | .macro ct_user_exit, syscall = 0 |
| 43 | #ifdef CONFIG_CONTEXT_TRACKING |
| 44 | bl context_tracking_user_exit |
| 45 | .if \syscall == 1 |
| 46 | /* |
| 47 | * Save/restore needed during syscalls. Restore syscall arguments from |
| 48 | * the values already saved on stack during kernel_entry. |
| 49 | */ |
| 50 | ldp x0, x1, [sp] |
| 51 | ldp x2, x3, [sp, #S_X2] |
| 52 | ldp x4, x5, [sp, #S_X4] |
| 53 | ldp x6, x7, [sp, #S_X6] |
| 54 | .endif |
| 55 | #endif |
| 56 | .endm |
| 57 | |
| 58 | .macro ct_user_enter |
| 59 | #ifdef CONFIG_CONTEXT_TRACKING |
| 60 | bl context_tracking_user_enter |
| 61 | #endif |
| 62 | .endm |
| 63 | |
| 64 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 65 | * Bad Abort numbers |
| 66 | *----------------- |
| 67 | */ |
| 68 | #define BAD_SYNC 0 |
| 69 | #define BAD_IRQ 1 |
| 70 | #define BAD_FIQ 2 |
| 71 | #define BAD_ERROR 3 |
| 72 | |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 73 | .macro kernel_ventry label |
| 74 | .align 7 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 75 | sub sp, sp, #S_FRAME_SIZE |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 76 | b \label |
| 77 | .endm |
| 78 | |
| 79 | .macro kernel_entry, el, regsize = 64 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 80 | .if \regsize == 32 |
| 81 | mov w0, w0 // zero upper 32 bits of x0 |
| 82 | .endif |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 83 | stp x0, x1, [sp, #16 * 0] |
| 84 | stp x2, x3, [sp, #16 * 1] |
| 85 | stp x4, x5, [sp, #16 * 2] |
| 86 | stp x6, x7, [sp, #16 * 3] |
| 87 | stp x8, x9, [sp, #16 * 4] |
| 88 | stp x10, x11, [sp, #16 * 5] |
| 89 | stp x12, x13, [sp, #16 * 6] |
| 90 | stp x14, x15, [sp, #16 * 7] |
| 91 | stp x16, x17, [sp, #16 * 8] |
| 92 | stp x18, x19, [sp, #16 * 9] |
| 93 | stp x20, x21, [sp, #16 * 10] |
| 94 | stp x22, x23, [sp, #16 * 11] |
| 95 | stp x24, x25, [sp, #16 * 12] |
| 96 | stp x26, x27, [sp, #16 * 13] |
| 97 | stp x28, x29, [sp, #16 * 14] |
| 98 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 99 | .if \el == 0 |
| 100 | mrs x21, sp_el0 |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 101 | mov tsk, sp |
| 102 | and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 103 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug |
| 104 | disable_step_tsk x19, x20 // exceptions when scheduling. |
James Morse | 49003a8 | 2015-12-10 10:22:41 +0000 | [diff] [blame] | 105 | |
| 106 | mov x29, xzr // fp pointed to user-space |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 107 | .else |
| 108 | add x21, sp, #S_FRAME_SIZE |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 109 | get_thread_info tsk |
| 110 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ |
| 111 | ldr x20, [tsk, #TI_ADDR_LIMIT] |
| 112 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
| 113 | mov x20, #TASK_SIZE_64 |
| 114 | str x20, [tsk, #TI_ADDR_LIMIT] |
Vladimir Murzin | 563cada | 2016-09-01 14:35:59 +0100 | [diff] [blame] | 115 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 116 | .endif /* \el == 0 */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 117 | mrs x22, elr_el1 |
| 118 | mrs x23, spsr_el1 |
| 119 | stp lr, x21, [sp, #S_LR] |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 120 | |
| 121 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 122 | /* |
| 123 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from |
| 124 | * EL0, there is no need to check the state of TTBR0_EL1 since |
| 125 | * accesses are always enabled. |
| 126 | * Note that the meaning of this bit differs from the ARMv8.1 PAN |
| 127 | * feature as all TTBR0_EL1 accesses are disabled, not just those to |
| 128 | * user mappings. |
| 129 | */ |
| 130 | alternative_if ARM64_HAS_PAN |
| 131 | b 1f // skip TTBR0 PAN |
| 132 | alternative_else_nop_endif |
| 133 | |
| 134 | .if \el != 0 |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame^] | 135 | mrs x21, ttbr1_el1 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 136 | tst x21, #0xffff << 48 // Check for the reserved ASID |
| 137 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR |
| 138 | b.eq 1f // TTBR0 access already disabled |
| 139 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR |
| 140 | .endif |
| 141 | |
| 142 | __uaccess_ttbr0_disable x21 |
| 143 | 1: |
| 144 | #endif |
| 145 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 146 | stp x22, x23, [sp, #S_PC] |
| 147 | |
| 148 | /* |
| 149 | * Set syscallno to -1 by default (overridden later if real syscall). |
| 150 | */ |
| 151 | .if \el == 0 |
| 152 | mvn x21, xzr |
| 153 | str x21, [sp, #S_SYSCALLNO] |
| 154 | .endif |
| 155 | |
| 156 | /* |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 157 | * Set sp_el0 to current thread_info. |
| 158 | */ |
| 159 | .if \el == 0 |
| 160 | msr sp_el0, tsk |
| 161 | .endif |
| 162 | |
| 163 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 164 | * Registers that may be useful after this macro is invoked: |
| 165 | * |
| 166 | * x21 - aborted SP |
| 167 | * x22 - aborted PC |
| 168 | * x23 - aborted PSTATE |
| 169 | */ |
| 170 | .endm |
| 171 | |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 172 | .macro kernel_exit, el |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 173 | .if \el != 0 |
| 174 | /* Restore the task's original addr_limit. */ |
| 175 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] |
| 176 | str x20, [tsk, #TI_ADDR_LIMIT] |
| 177 | |
| 178 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ |
| 179 | .endif |
| 180 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 181 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
| 182 | .if \el == 0 |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 183 | ct_user_enter |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 184 | .endif |
| 185 | |
| 186 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 187 | /* |
| 188 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR |
| 189 | * PAN bit checking. |
| 190 | */ |
| 191 | alternative_if ARM64_HAS_PAN |
| 192 | b 2f // skip TTBR0 PAN |
| 193 | alternative_else_nop_endif |
| 194 | |
| 195 | .if \el != 0 |
| 196 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set |
| 197 | .endif |
| 198 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame^] | 199 | __uaccess_ttbr0_enable x0, x1 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 200 | |
| 201 | .if \el == 0 |
| 202 | /* |
| 203 | * Enable errata workarounds only if returning to user. The only |
| 204 | * workaround currently required for TTBR0_EL1 changes are for the |
| 205 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache |
| 206 | * corruption). |
| 207 | */ |
Will Deacon | 071a49f | 2017-08-10 13:34:30 +0100 | [diff] [blame] | 208 | post_ttbr_update_workaround |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 209 | .endif |
| 210 | 1: |
| 211 | .if \el != 0 |
| 212 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit |
| 213 | .endif |
| 214 | 2: |
| 215 | #endif |
| 216 | |
| 217 | .if \el == 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 218 | ldr x23, [sp, #S_SP] // load return stack pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 219 | msr sp_el0, x23 |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 220 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 221 | alternative_if ARM64_WORKAROUND_845719 |
Daniel Thompson | e28cabf | 2015-07-22 12:21:03 +0100 | [diff] [blame] | 222 | tbz x22, #4, 1f |
| 223 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
| 224 | mrs x29, contextidr_el1 |
| 225 | msr contextidr_el1, x29 |
| 226 | #else |
| 227 | msr contextidr_el1, xzr |
| 228 | #endif |
| 229 | 1: |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 230 | alternative_else_nop_endif |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 231 | #endif |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 232 | .endif |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 233 | |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 234 | msr elr_el1, x21 // set up the return data |
| 235 | msr spsr_el1, x22 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 236 | ldp x0, x1, [sp, #16 * 0] |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 237 | ldp x2, x3, [sp, #16 * 1] |
| 238 | ldp x4, x5, [sp, #16 * 2] |
| 239 | ldp x6, x7, [sp, #16 * 3] |
| 240 | ldp x8, x9, [sp, #16 * 4] |
| 241 | ldp x10, x11, [sp, #16 * 5] |
| 242 | ldp x12, x13, [sp, #16 * 6] |
| 243 | ldp x14, x15, [sp, #16 * 7] |
| 244 | ldp x16, x17, [sp, #16 * 8] |
| 245 | ldp x18, x19, [sp, #16 * 9] |
| 246 | ldp x20, x21, [sp, #16 * 10] |
| 247 | ldp x22, x23, [sp, #16 * 11] |
| 248 | ldp x24, x25, [sp, #16 * 12] |
| 249 | ldp x26, x27, [sp, #16 * 13] |
| 250 | ldp x28, x29, [sp, #16 * 14] |
| 251 | ldr lr, [sp, #S_LR] |
| 252 | add sp, sp, #S_FRAME_SIZE // restore sp |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 253 | eret // return to kernel |
| 254 | .endm |
| 255 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 256 | .macro irq_stack_entry |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 257 | mov x19, sp // preserve the original sp |
| 258 | |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 259 | /* |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 260 | * Compare sp with the current thread_info, if the top |
| 261 | * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and |
| 262 | * should switch to the irq stack. |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 263 | */ |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 264 | and x25, x19, #~(THREAD_SIZE - 1) |
| 265 | cmp x25, tsk |
| 266 | b.ne 9998f |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 267 | |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 268 | this_cpu_ptr irq_stack, x25, x26 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 269 | mov x26, #IRQ_STACK_START_SP |
| 270 | add x26, x25, x26 |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 271 | |
| 272 | /* switch to the irq stack */ |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 273 | mov sp, x26 |
| 274 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 275 | /* |
| 276 | * Add a dummy stack frame, this non-standard format is fixed up |
| 277 | * by unwind_frame() |
| 278 | */ |
| 279 | stp x29, x19, [sp, #-16]! |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 280 | mov x29, sp |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 281 | |
| 282 | 9998: |
| 283 | .endm |
| 284 | |
| 285 | /* |
| 286 | * x19 should be preserved between irq_stack_entry and |
| 287 | * irq_stack_exit. |
| 288 | */ |
| 289 | .macro irq_stack_exit |
| 290 | mov sp, x19 |
| 291 | .endm |
| 292 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 293 | /* |
| 294 | * These are the registers used in the syscall handler, and allow us to |
| 295 | * have in theory up to 7 arguments to a function - x0 to x6. |
| 296 | * |
| 297 | * x7 is reserved for the system call number in 32-bit mode. |
| 298 | */ |
| 299 | sc_nr .req x25 // number of system calls |
| 300 | scno .req x26 // syscall number |
| 301 | stbl .req x27 // syscall table pointer |
| 302 | tsk .req x28 // current thread_info |
| 303 | |
| 304 | /* |
| 305 | * Interrupt handling. |
| 306 | */ |
| 307 | .macro irq_handler |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 308 | ldr_l x1, handle_arch_irq |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 309 | mov x0, sp |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 310 | irq_stack_entry |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 311 | blr x1 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 312 | irq_stack_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 313 | .endm |
| 314 | |
| 315 | .text |
| 316 | |
| 317 | /* |
| 318 | * Exception vectors. |
| 319 | */ |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 320 | .pushsection ".entry.text", "ax" |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 321 | |
| 322 | .align 11 |
| 323 | ENTRY(vectors) |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 324 | kernel_ventry el1_sync_invalid // Synchronous EL1t |
| 325 | kernel_ventry el1_irq_invalid // IRQ EL1t |
| 326 | kernel_ventry el1_fiq_invalid // FIQ EL1t |
| 327 | kernel_ventry el1_error_invalid // Error EL1t |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 328 | |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 329 | kernel_ventry el1_sync // Synchronous EL1h |
| 330 | kernel_ventry el1_irq // IRQ EL1h |
| 331 | kernel_ventry el1_fiq_invalid // FIQ EL1h |
| 332 | kernel_ventry el1_error_invalid // Error EL1h |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 333 | |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 334 | kernel_ventry el0_sync // Synchronous 64-bit EL0 |
| 335 | kernel_ventry el0_irq // IRQ 64-bit EL0 |
| 336 | kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0 |
| 337 | kernel_ventry el0_error_invalid // Error 64-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 338 | |
| 339 | #ifdef CONFIG_COMPAT |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 340 | kernel_ventry el0_sync_compat // Synchronous 32-bit EL0 |
| 341 | kernel_ventry el0_irq_compat // IRQ 32-bit EL0 |
| 342 | kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 |
| 343 | kernel_ventry el0_error_invalid_compat // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 344 | #else |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 345 | kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0 |
| 346 | kernel_ventry el0_irq_invalid // IRQ 32-bit EL0 |
| 347 | kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0 |
| 348 | kernel_ventry el0_error_invalid // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 349 | #endif |
| 350 | END(vectors) |
| 351 | |
| 352 | /* |
| 353 | * Invalid mode handlers |
| 354 | */ |
| 355 | .macro inv_entry, el, reason, regsize = 64 |
Ard Biesheuvel | b660950 | 2016-03-18 10:58:09 +0100 | [diff] [blame] | 356 | kernel_entry \el, \regsize |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 357 | mov x0, sp |
| 358 | mov x1, #\reason |
| 359 | mrs x2, esr_el1 |
| 360 | b bad_mode |
| 361 | .endm |
| 362 | |
| 363 | el0_sync_invalid: |
| 364 | inv_entry 0, BAD_SYNC |
| 365 | ENDPROC(el0_sync_invalid) |
| 366 | |
| 367 | el0_irq_invalid: |
| 368 | inv_entry 0, BAD_IRQ |
| 369 | ENDPROC(el0_irq_invalid) |
| 370 | |
| 371 | el0_fiq_invalid: |
| 372 | inv_entry 0, BAD_FIQ |
| 373 | ENDPROC(el0_fiq_invalid) |
| 374 | |
| 375 | el0_error_invalid: |
| 376 | inv_entry 0, BAD_ERROR |
| 377 | ENDPROC(el0_error_invalid) |
| 378 | |
| 379 | #ifdef CONFIG_COMPAT |
| 380 | el0_fiq_invalid_compat: |
| 381 | inv_entry 0, BAD_FIQ, 32 |
| 382 | ENDPROC(el0_fiq_invalid_compat) |
| 383 | |
| 384 | el0_error_invalid_compat: |
| 385 | inv_entry 0, BAD_ERROR, 32 |
| 386 | ENDPROC(el0_error_invalid_compat) |
| 387 | #endif |
| 388 | |
| 389 | el1_sync_invalid: |
| 390 | inv_entry 1, BAD_SYNC |
| 391 | ENDPROC(el1_sync_invalid) |
| 392 | |
| 393 | el1_irq_invalid: |
| 394 | inv_entry 1, BAD_IRQ |
| 395 | ENDPROC(el1_irq_invalid) |
| 396 | |
| 397 | el1_fiq_invalid: |
| 398 | inv_entry 1, BAD_FIQ |
| 399 | ENDPROC(el1_fiq_invalid) |
| 400 | |
| 401 | el1_error_invalid: |
| 402 | inv_entry 1, BAD_ERROR |
| 403 | ENDPROC(el1_error_invalid) |
| 404 | |
| 405 | /* |
| 406 | * EL1 mode handlers. |
| 407 | */ |
| 408 | .align 6 |
| 409 | el1_sync: |
| 410 | kernel_entry 1 |
| 411 | mrs x1, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 412 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
| 413 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 414 | b.eq el1_da |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 415 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
| 416 | b.eq el1_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 417 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 418 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 419 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 420 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 421 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 422 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 423 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 424 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 425 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 426 | b.ge el1_dbg |
| 427 | b el1_inv |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 428 | |
| 429 | el1_ia: |
| 430 | /* |
| 431 | * Fall through to the Data abort case |
| 432 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 433 | el1_da: |
| 434 | /* |
| 435 | * Data abort handling |
| 436 | */ |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 437 | mrs x3, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 438 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 439 | // re-enable interrupts if they were enabled in the aborted context |
| 440 | tbnz x23, #7, 1f // PSR_I_BIT |
| 441 | enable_irq |
| 442 | 1: |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 443 | clear_address_tag x0, x3 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 444 | mov x2, sp // struct pt_regs |
| 445 | bl do_mem_abort |
| 446 | |
| 447 | // disable interrupts before pulling preserved data off the stack |
| 448 | disable_irq |
| 449 | kernel_exit 1 |
| 450 | el1_sp_pc: |
| 451 | /* |
| 452 | * Stack or PC alignment exception handling |
| 453 | */ |
| 454 | mrs x0, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 455 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 456 | mov x2, sp |
| 457 | b do_sp_pc_abort |
| 458 | el1_undef: |
| 459 | /* |
| 460 | * Undefined instruction |
| 461 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 462 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 463 | mov x0, sp |
| 464 | b do_undefinstr |
| 465 | el1_dbg: |
| 466 | /* |
| 467 | * Debug exception handling |
| 468 | */ |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 469 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
Sandeepa Prabhu | ee6214c | 2013-12-04 05:50:20 +0000 | [diff] [blame] | 470 | cinc x24, x24, eq // set bit '0' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 471 | tbz x24, #0, el1_inv // EL1 only |
| 472 | mrs x0, far_el1 |
| 473 | mov x2, sp // struct pt_regs |
| 474 | bl do_debug_exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 475 | kernel_exit 1 |
| 476 | el1_inv: |
| 477 | // TODO: add support for undefined instructions in kernel mode |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 478 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 479 | mov x0, sp |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 480 | mov x2, x1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 481 | mov x1, #BAD_SYNC |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 482 | b bad_mode |
| 483 | ENDPROC(el1_sync) |
| 484 | |
| 485 | .align 6 |
| 486 | el1_irq: |
| 487 | kernel_entry 1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 488 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 489 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 490 | bl trace_hardirqs_off |
| 491 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 492 | |
| 493 | irq_handler |
| 494 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 495 | #ifdef CONFIG_PREEMPT |
Neil Zhang | 883c057 | 2014-01-13 08:57:56 +0000 | [diff] [blame] | 496 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
Marc Zyngier | 717321f | 2013-11-04 20:14:58 +0000 | [diff] [blame] | 497 | cbnz w24, 1f // preempt count != 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 498 | ldr x0, [tsk, #TI_FLAGS] // get flags |
| 499 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
| 500 | bl el1_preempt |
| 501 | 1: |
| 502 | #endif |
| 503 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 504 | bl trace_hardirqs_on |
| 505 | #endif |
| 506 | kernel_exit 1 |
| 507 | ENDPROC(el1_irq) |
| 508 | |
| 509 | #ifdef CONFIG_PREEMPT |
| 510 | el1_preempt: |
| 511 | mov x24, lr |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 512 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 513 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
| 514 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
| 515 | ret x24 |
| 516 | #endif |
| 517 | |
| 518 | /* |
| 519 | * EL0 mode handlers. |
| 520 | */ |
| 521 | .align 6 |
| 522 | el0_sync: |
| 523 | kernel_entry 0 |
| 524 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 525 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 526 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 527 | b.eq el0_svc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 528 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 529 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 530 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 531 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 532 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 533 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 534 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 535 | b.eq el0_fpsimd_exc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 536 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 537 | b.eq el0_sys |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 538 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 539 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 540 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 541 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 542 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 543 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 544 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 545 | b.ge el0_dbg |
| 546 | b el0_inv |
| 547 | |
| 548 | #ifdef CONFIG_COMPAT |
| 549 | .align 6 |
| 550 | el0_sync_compat: |
| 551 | kernel_entry 0, 32 |
| 552 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 553 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 554 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 555 | b.eq el0_svc_compat |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 556 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 557 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 558 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 559 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 560 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 561 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 562 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 563 | b.eq el0_fpsimd_exc |
Mark Salyzyn | 77f3228f | 2015-10-13 14:30:51 -0700 | [diff] [blame] | 564 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 565 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 566 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 567 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 568 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 569 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 570 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 571 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 572 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 573 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 574 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 575 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 576 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 577 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 578 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 579 | b.ge el0_dbg |
| 580 | b el0_inv |
| 581 | el0_svc_compat: |
| 582 | /* |
| 583 | * AArch32 syscall handling |
| 584 | */ |
Catalin Marinas | 0156411 | 2015-01-06 16:42:32 +0000 | [diff] [blame] | 585 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 586 | uxtw scno, w7 // syscall number in w7 (r7) |
| 587 | mov sc_nr, #__NR_compat_syscalls |
| 588 | b el0_svc_naked |
| 589 | |
| 590 | .align 6 |
| 591 | el0_irq_compat: |
| 592 | kernel_entry 0, 32 |
| 593 | b el0_irq_naked |
| 594 | #endif |
| 595 | |
| 596 | el0_da: |
| 597 | /* |
| 598 | * Data abort handling |
| 599 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 600 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 601 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 602 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 603 | ct_user_exit |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 604 | clear_address_tag x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 605 | mov x1, x25 |
| 606 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 607 | bl do_mem_abort |
| 608 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 609 | el0_ia: |
| 610 | /* |
| 611 | * Instruction abort handling |
| 612 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 613 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 614 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 615 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 616 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 617 | mov x0, x26 |
Mark Rutland | 541ec87 | 2016-05-31 12:33:03 +0100 | [diff] [blame] | 618 | mov x1, x25 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 619 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 620 | bl do_mem_abort |
| 621 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 622 | el0_fpsimd_acc: |
| 623 | /* |
| 624 | * Floating Point or Advanced SIMD access |
| 625 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 626 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 627 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 628 | mov x0, x25 |
| 629 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 630 | bl do_fpsimd_acc |
| 631 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 632 | el0_fpsimd_exc: |
| 633 | /* |
| 634 | * Floating Point or Advanced SIMD exception |
| 635 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 636 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 637 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 638 | mov x0, x25 |
| 639 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 640 | bl do_fpsimd_exc |
| 641 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 642 | el0_sp_pc: |
| 643 | /* |
| 644 | * Stack or PC alignment exception handling |
| 645 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 646 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 647 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 648 | enable_dbg_and_irq |
Mark Rutland | 46b0567 | 2015-06-15 16:40:27 +0100 | [diff] [blame] | 649 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 650 | mov x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 651 | mov x1, x25 |
| 652 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 653 | bl do_sp_pc_abort |
| 654 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 655 | el0_undef: |
| 656 | /* |
| 657 | * Undefined instruction |
| 658 | */ |
Catalin Marinas | 2600e13 | 2013-08-22 11:47:37 +0100 | [diff] [blame] | 659 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 660 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 661 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 662 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 663 | bl do_undefinstr |
| 664 | b ret_to_user |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 665 | el0_sys: |
| 666 | /* |
| 667 | * System instructions, for trapped cache maintenance instructions |
| 668 | */ |
| 669 | enable_dbg_and_irq |
| 670 | ct_user_exit |
| 671 | mov x0, x25 |
| 672 | mov x1, sp |
| 673 | bl do_sysinstr |
| 674 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 675 | el0_dbg: |
| 676 | /* |
| 677 | * Debug exception handling |
| 678 | */ |
| 679 | tbnz x24, #0, el0_inv // EL0 only |
| 680 | mrs x0, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 681 | mov x1, x25 |
| 682 | mov x2, sp |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 683 | bl do_debug_exception |
| 684 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 685 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 686 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 687 | el0_inv: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 688 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 689 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 690 | mov x0, sp |
| 691 | mov x1, #BAD_SYNC |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 692 | mov x2, x25 |
Mark Rutland | de32794 | 2017-01-18 17:23:41 +0000 | [diff] [blame] | 693 | bl bad_el0_sync |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 694 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 695 | ENDPROC(el0_sync) |
| 696 | |
| 697 | .align 6 |
| 698 | el0_irq: |
| 699 | kernel_entry 0 |
| 700 | el0_irq_naked: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 701 | enable_dbg |
| 702 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 703 | bl trace_hardirqs_off |
| 704 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 705 | |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 706 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 707 | irq_handler |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 708 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 709 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 710 | bl trace_hardirqs_on |
| 711 | #endif |
| 712 | b ret_to_user |
| 713 | ENDPROC(el0_irq) |
| 714 | |
| 715 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 716 | * Register switch for AArch64. The callee-saved registers need to be saved |
| 717 | * and restored. On entry: |
| 718 | * x0 = previous task_struct (must be preserved across the switch) |
| 719 | * x1 = next task_struct |
| 720 | * Previous and next are guaranteed not to be the same. |
| 721 | * |
| 722 | */ |
| 723 | ENTRY(cpu_switch_to) |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 724 | mov x10, #THREAD_CPU_CONTEXT |
| 725 | add x8, x0, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 726 | mov x9, sp |
| 727 | stp x19, x20, [x8], #16 // store callee-saved registers |
| 728 | stp x21, x22, [x8], #16 |
| 729 | stp x23, x24, [x8], #16 |
| 730 | stp x25, x26, [x8], #16 |
| 731 | stp x27, x28, [x8], #16 |
| 732 | stp x29, x9, [x8], #16 |
| 733 | str lr, [x8] |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 734 | add x8, x1, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 735 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
| 736 | ldp x21, x22, [x8], #16 |
| 737 | ldp x23, x24, [x8], #16 |
| 738 | ldp x25, x26, [x8], #16 |
| 739 | ldp x27, x28, [x8], #16 |
| 740 | ldp x29, x9, [x8], #16 |
| 741 | ldr lr, [x8] |
| 742 | mov sp, x9 |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 743 | and x9, x9, #~(THREAD_SIZE - 1) |
| 744 | msr sp_el0, x9 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 745 | ret |
| 746 | ENDPROC(cpu_switch_to) |
| 747 | |
| 748 | /* |
| 749 | * This is the fast syscall return path. We do as little as possible here, |
| 750 | * and this includes saving x0 back into the kernel stack. |
| 751 | */ |
| 752 | ret_fast_syscall: |
| 753 | disable_irq // disable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 754 | str x0, [sp, #S_X0] // returned x0 |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 755 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
| 756 | and x2, x1, #_TIF_SYSCALL_WORK |
| 757 | cbnz x2, ret_fast_syscall_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 758 | and x2, x1, #_TIF_WORK_MASK |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 759 | cbnz x2, work_pending |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 760 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 761 | kernel_exit 0 |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 762 | ret_fast_syscall_trace: |
| 763 | enable_irq // enable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 764 | b __sys_trace_return_skipped // we already saved x0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 765 | |
| 766 | /* |
| 767 | * Ok, we need to do extra processing, enter the slow path. |
| 768 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 769 | work_pending: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 770 | mov x0, sp // 'regs' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 771 | bl do_notify_resume |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 772 | #ifdef CONFIG_TRACE_IRQFLAGS |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 773 | bl trace_hardirqs_on // enabled while in userspace |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 774 | #endif |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 775 | ldr x1, [tsk, #TI_FLAGS] // re-check for single-step |
| 776 | b finish_ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 777 | /* |
| 778 | * "slow" syscall return path. |
| 779 | */ |
Catalin Marinas | 59dc67b | 2012-09-10 16:11:46 +0100 | [diff] [blame] | 780 | ret_to_user: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 781 | disable_irq // disable interrupts |
| 782 | ldr x1, [tsk, #TI_FLAGS] |
| 783 | and x2, x1, #_TIF_WORK_MASK |
| 784 | cbnz x2, work_pending |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 785 | finish_ret_to_user: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 786 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 787 | kernel_exit 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 788 | ENDPROC(ret_to_user) |
| 789 | |
| 790 | /* |
| 791 | * This is how we return from a fork. |
| 792 | */ |
| 793 | ENTRY(ret_from_fork) |
| 794 | bl schedule_tail |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 795 | cbz x19, 1f // not a kernel thread |
| 796 | mov x0, x20 |
| 797 | blr x19 |
| 798 | 1: get_thread_info tsk |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 799 | b ret_to_user |
| 800 | ENDPROC(ret_from_fork) |
| 801 | |
| 802 | /* |
| 803 | * SVC handler. |
| 804 | */ |
| 805 | .align 6 |
| 806 | el0_svc: |
| 807 | adrp stbl, sys_call_table // load syscall table pointer |
| 808 | uxtw scno, w8 // syscall number in w8 |
| 809 | mov sc_nr, #__NR_syscalls |
| 810 | el0_svc_naked: // compat entry point |
| 811 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 812 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 813 | ct_user_exit 1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 814 | |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 815 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
| 816 | tst x16, #_TIF_SYSCALL_WORK |
| 817 | b.ne __sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 818 | cmp scno, sc_nr // check upper syscall limit |
| 819 | b.hs ni_sys |
| 820 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 821 | blr x16 // call sys_* routine |
| 822 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 823 | ni_sys: |
| 824 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 825 | bl do_ni_syscall |
| 826 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 827 | ENDPROC(el0_svc) |
| 828 | |
| 829 | /* |
| 830 | * This is the really slow path. We're going to be doing context |
| 831 | * switches, and waiting for our parent to respond. |
| 832 | */ |
| 833 | __sys_trace: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 834 | mov w0, #-1 // set default errno for |
| 835 | cmp scno, x0 // user-issued syscall(-1) |
| 836 | b.ne 1f |
| 837 | mov x0, #-ENOSYS |
| 838 | str x0, [sp, #S_X0] |
| 839 | 1: mov x0, sp |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 840 | bl syscall_trace_enter |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 841 | cmp w0, #-1 // skip the syscall? |
| 842 | b.eq __sys_trace_return_skipped |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 843 | uxtw scno, w0 // syscall number (possibly new) |
| 844 | mov x1, sp // pointer to regs |
| 845 | cmp scno, sc_nr // check upper syscall limit |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 846 | b.hs __ni_sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 847 | ldp x0, x1, [sp] // restore the syscall args |
| 848 | ldp x2, x3, [sp, #S_X2] |
| 849 | ldp x4, x5, [sp, #S_X4] |
| 850 | ldp x6, x7, [sp, #S_X6] |
| 851 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 852 | blr x16 // call sys_* routine |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 853 | |
| 854 | __sys_trace_return: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 855 | str x0, [sp, #S_X0] // save returned x0 |
| 856 | __sys_trace_return_skipped: |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 857 | mov x0, sp |
| 858 | bl syscall_trace_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 859 | b ret_to_user |
| 860 | |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 861 | __ni_sys_trace: |
| 862 | mov x0, sp |
| 863 | bl do_ni_syscall |
| 864 | b __sys_trace_return |
| 865 | |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 866 | .popsection // .entry.text |
| 867 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 868 | /* |
| 869 | * Special system call wrappers. |
| 870 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 871 | ENTRY(sys_rt_sigreturn_wrapper) |
| 872 | mov x0, sp |
| 873 | b sys_rt_sigreturn |
| 874 | ENDPROC(sys_rt_sigreturn_wrapper) |