Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, |
| 3 | * GT64260, MV64340, MV64360, GT96100, ... ). |
| 4 | * |
| 5 | * Author: Mark A. Greer <mgreer@mvista.com> |
| 6 | * |
| 7 | * Based on an old MPSC driver that was in the linuxppc tree. It appears to |
| 8 | * have been created by Chris Zankel (formerly of MontaVista) but there |
| 9 | * is no proper Copyright so I'm not sure. Apparently, parts were also |
| 10 | * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c |
| 11 | * by Russell King. |
| 12 | * |
| 13 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under |
| 14 | * the terms of the GNU General Public License version 2. This program |
| 15 | * is licensed "as is" without any warranty of any kind, whether express |
| 16 | * or implied. |
| 17 | */ |
| 18 | /* |
| 19 | * The MPSC interface is much like a typical network controller's interface. |
| 20 | * That is, you set up separate rings of descriptors for transmitting and |
| 21 | * receiving data. There is also a pool of buffers with (one buffer per |
| 22 | * descriptor) that incoming data are dma'd into or outgoing data are dma'd |
| 23 | * out of. |
| 24 | * |
| 25 | * The MPSC requires two other controllers to be able to work. The Baud Rate |
| 26 | * Generator (BRG) provides a clock at programmable frequencies which determines |
| 27 | * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the |
| 28 | * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the |
| 29 | * MPSC. It is actually the SDMA interrupt that the driver uses to keep the |
| 30 | * transmit and receive "engines" going (i.e., indicate data has been |
| 31 | * transmitted or received). |
| 32 | * |
| 33 | * NOTES: |
| 34 | * |
| 35 | * 1) Some chips have an erratum where several regs cannot be |
| 36 | * read. To work around that, we keep a local copy of those regs in |
| 37 | * 'mpsc_port_info'. |
| 38 | * |
| 39 | * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr |
| 40 | * accesses system mem with coherency enabled. For that reason, the driver |
| 41 | * assumes that coherency for that ctlr has been disabled. This means |
| 42 | * that when in a cache coherent system, the driver has to manually manage |
| 43 | * the data cache on the areas that it touches because the dma_* macro are |
| 44 | * basically no-ops. |
| 45 | * |
| 46 | * 3) There is an erratum (on PPC) where you can't use the instruction to do |
| 47 | * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places |
| 48 | * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed. |
| 49 | * |
| 50 | * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. |
| 51 | */ |
| 52 | |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 53 | |
| 54 | #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 55 | #define SUPPORT_SYSRQ |
| 56 | #endif |
| 57 | |
| 58 | #include <linux/module.h> |
| 59 | #include <linux/moduleparam.h> |
| 60 | #include <linux/tty.h> |
| 61 | #include <linux/tty_flip.h> |
| 62 | #include <linux/ioport.h> |
| 63 | #include <linux/init.h> |
| 64 | #include <linux/console.h> |
| 65 | #include <linux/sysrq.h> |
| 66 | #include <linux/serial.h> |
| 67 | #include <linux/serial_core.h> |
| 68 | #include <linux/delay.h> |
| 69 | #include <linux/device.h> |
| 70 | #include <linux/dma-mapping.h> |
| 71 | #include <linux/mv643xx.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 72 | #include <linux/platform_device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame^] | 73 | #include <linux/gfp.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 74 | |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 75 | #include <asm/io.h> |
| 76 | #include <asm/irq.h> |
| 77 | |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 78 | #define MPSC_NUM_CTLRS 2 |
| 79 | |
| 80 | /* |
| 81 | * Descriptors and buffers must be cache line aligned. |
| 82 | * Buffers lengths must be multiple of cache line size. |
| 83 | * Number of Tx & Rx descriptors must be powers of 2. |
| 84 | */ |
| 85 | #define MPSC_RXR_ENTRIES 32 |
| 86 | #define MPSC_RXRE_SIZE dma_get_cache_alignment() |
| 87 | #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE) |
| 88 | #define MPSC_RXBE_SIZE dma_get_cache_alignment() |
| 89 | #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE) |
| 90 | |
| 91 | #define MPSC_TXR_ENTRIES 32 |
| 92 | #define MPSC_TXRE_SIZE dma_get_cache_alignment() |
| 93 | #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE) |
| 94 | #define MPSC_TXBE_SIZE dma_get_cache_alignment() |
| 95 | #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) |
| 96 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 97 | #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \ |
| 98 | + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */) |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 99 | |
| 100 | /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ |
| 101 | struct mpsc_rx_desc { |
| 102 | u16 bufsize; |
| 103 | u16 bytecnt; |
| 104 | u32 cmdstat; |
| 105 | u32 link; |
| 106 | u32 buf_ptr; |
| 107 | } __attribute((packed)); |
| 108 | |
| 109 | struct mpsc_tx_desc { |
| 110 | u16 bytecnt; |
| 111 | u16 shadow; |
| 112 | u32 cmdstat; |
| 113 | u32 link; |
| 114 | u32 buf_ptr; |
| 115 | } __attribute((packed)); |
| 116 | |
| 117 | /* |
| 118 | * Some regs that have the erratum that you can't read them are are shared |
| 119 | * between the two MPSC controllers. This struct contains those shared regs. |
| 120 | */ |
| 121 | struct mpsc_shared_regs { |
| 122 | phys_addr_t mpsc_routing_base_p; |
| 123 | phys_addr_t sdma_intr_base_p; |
| 124 | |
| 125 | void __iomem *mpsc_routing_base; |
| 126 | void __iomem *sdma_intr_base; |
| 127 | |
| 128 | u32 MPSC_MRR_m; |
| 129 | u32 MPSC_RCRR_m; |
| 130 | u32 MPSC_TCRR_m; |
| 131 | u32 SDMA_INTR_CAUSE_m; |
| 132 | u32 SDMA_INTR_MASK_m; |
| 133 | }; |
| 134 | |
| 135 | /* The main driver data structure */ |
| 136 | struct mpsc_port_info { |
| 137 | struct uart_port port; /* Overlay uart_port structure */ |
| 138 | |
| 139 | /* Internal driver state for this ctlr */ |
| 140 | u8 ready; |
| 141 | u8 rcv_data; |
| 142 | tcflag_t c_iflag; /* save termios->c_iflag */ |
| 143 | tcflag_t c_cflag; /* save termios->c_cflag */ |
| 144 | |
| 145 | /* Info passed in from platform */ |
| 146 | u8 mirror_regs; /* Need to mirror regs? */ |
| 147 | u8 cache_mgmt; /* Need manual cache mgmt? */ |
| 148 | u8 brg_can_tune; /* BRG has baud tuning? */ |
| 149 | u32 brg_clk_src; |
| 150 | u16 mpsc_max_idle; |
| 151 | int default_baud; |
| 152 | int default_bits; |
| 153 | int default_parity; |
| 154 | int default_flow; |
| 155 | |
| 156 | /* Physical addresses of various blocks of registers (from platform) */ |
| 157 | phys_addr_t mpsc_base_p; |
| 158 | phys_addr_t sdma_base_p; |
| 159 | phys_addr_t brg_base_p; |
| 160 | |
| 161 | /* Virtual addresses of various blocks of registers (from platform) */ |
| 162 | void __iomem *mpsc_base; |
| 163 | void __iomem *sdma_base; |
| 164 | void __iomem *brg_base; |
| 165 | |
| 166 | /* Descriptor ring and buffer allocations */ |
| 167 | void *dma_region; |
| 168 | dma_addr_t dma_region_p; |
| 169 | |
| 170 | dma_addr_t rxr; /* Rx descriptor ring */ |
| 171 | dma_addr_t rxr_p; /* Phys addr of rxr */ |
| 172 | u8 *rxb; /* Rx Ring I/O buf */ |
| 173 | u8 *rxb_p; /* Phys addr of rxb */ |
| 174 | u32 rxr_posn; /* First desc w/ Rx data */ |
| 175 | |
| 176 | dma_addr_t txr; /* Tx descriptor ring */ |
| 177 | dma_addr_t txr_p; /* Phys addr of txr */ |
| 178 | u8 *txb; /* Tx Ring I/O buf */ |
| 179 | u8 *txb_p; /* Phys addr of txb */ |
| 180 | int txr_head; /* Where new data goes */ |
| 181 | int txr_tail; /* Where sent data comes off */ |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 182 | spinlock_t tx_lock; /* transmit lock */ |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 183 | |
| 184 | /* Mirrored values of regs we can't read (if 'mirror_regs' set) */ |
| 185 | u32 MPSC_MPCR_m; |
| 186 | u32 MPSC_CHR_1_m; |
| 187 | u32 MPSC_CHR_2_m; |
| 188 | u32 MPSC_CHR_10_m; |
| 189 | u32 BRG_BCR_m; |
| 190 | struct mpsc_shared_regs *shared_regs; |
| 191 | }; |
| 192 | |
| 193 | /* Hooks to platform-specific code */ |
| 194 | int mpsc_platform_register_driver(void); |
| 195 | void mpsc_platform_unregister_driver(void); |
| 196 | |
| 197 | /* Hooks back in to mpsc common to be called by platform-specific code */ |
| 198 | struct mpsc_port_info *mpsc_device_probe(int index); |
| 199 | struct mpsc_port_info *mpsc_device_remove(int index); |
| 200 | |
| 201 | /* Main MPSC Configuration Register Offsets */ |
| 202 | #define MPSC_MMCRL 0x0000 |
| 203 | #define MPSC_MMCRH 0x0004 |
| 204 | #define MPSC_MPCR 0x0008 |
| 205 | #define MPSC_CHR_1 0x000c |
| 206 | #define MPSC_CHR_2 0x0010 |
| 207 | #define MPSC_CHR_3 0x0014 |
| 208 | #define MPSC_CHR_4 0x0018 |
| 209 | #define MPSC_CHR_5 0x001c |
| 210 | #define MPSC_CHR_6 0x0020 |
| 211 | #define MPSC_CHR_7 0x0024 |
| 212 | #define MPSC_CHR_8 0x0028 |
| 213 | #define MPSC_CHR_9 0x002c |
| 214 | #define MPSC_CHR_10 0x0030 |
| 215 | #define MPSC_CHR_11 0x0034 |
| 216 | |
| 217 | #define MPSC_MPCR_FRZ (1 << 9) |
| 218 | #define MPSC_MPCR_CL_5 0 |
| 219 | #define MPSC_MPCR_CL_6 1 |
| 220 | #define MPSC_MPCR_CL_7 2 |
| 221 | #define MPSC_MPCR_CL_8 3 |
| 222 | #define MPSC_MPCR_SBL_1 0 |
| 223 | #define MPSC_MPCR_SBL_2 1 |
| 224 | |
| 225 | #define MPSC_CHR_2_TEV (1<<1) |
| 226 | #define MPSC_CHR_2_TA (1<<7) |
| 227 | #define MPSC_CHR_2_TTCS (1<<9) |
| 228 | #define MPSC_CHR_2_REV (1<<17) |
| 229 | #define MPSC_CHR_2_RA (1<<23) |
| 230 | #define MPSC_CHR_2_CRD (1<<25) |
| 231 | #define MPSC_CHR_2_EH (1<<31) |
| 232 | #define MPSC_CHR_2_PAR_ODD 0 |
| 233 | #define MPSC_CHR_2_PAR_SPACE 1 |
| 234 | #define MPSC_CHR_2_PAR_EVEN 2 |
| 235 | #define MPSC_CHR_2_PAR_MARK 3 |
| 236 | |
| 237 | /* MPSC Signal Routing */ |
| 238 | #define MPSC_MRR 0x0000 |
| 239 | #define MPSC_RCRR 0x0004 |
| 240 | #define MPSC_TCRR 0x0008 |
| 241 | |
| 242 | /* Serial DMA Controller Interface Registers */ |
| 243 | #define SDMA_SDC 0x0000 |
| 244 | #define SDMA_SDCM 0x0008 |
| 245 | #define SDMA_RX_DESC 0x0800 |
| 246 | #define SDMA_RX_BUF_PTR 0x0808 |
| 247 | #define SDMA_SCRDP 0x0810 |
| 248 | #define SDMA_TX_DESC 0x0c00 |
| 249 | #define SDMA_SCTDP 0x0c10 |
| 250 | #define SDMA_SFTDP 0x0c14 |
| 251 | |
| 252 | #define SDMA_DESC_CMDSTAT_PE (1<<0) |
| 253 | #define SDMA_DESC_CMDSTAT_CDL (1<<1) |
| 254 | #define SDMA_DESC_CMDSTAT_FR (1<<3) |
| 255 | #define SDMA_DESC_CMDSTAT_OR (1<<6) |
| 256 | #define SDMA_DESC_CMDSTAT_BR (1<<9) |
| 257 | #define SDMA_DESC_CMDSTAT_MI (1<<10) |
| 258 | #define SDMA_DESC_CMDSTAT_A (1<<11) |
| 259 | #define SDMA_DESC_CMDSTAT_AM (1<<12) |
| 260 | #define SDMA_DESC_CMDSTAT_CT (1<<13) |
| 261 | #define SDMA_DESC_CMDSTAT_C (1<<14) |
| 262 | #define SDMA_DESC_CMDSTAT_ES (1<<15) |
| 263 | #define SDMA_DESC_CMDSTAT_L (1<<16) |
| 264 | #define SDMA_DESC_CMDSTAT_F (1<<17) |
| 265 | #define SDMA_DESC_CMDSTAT_P (1<<18) |
| 266 | #define SDMA_DESC_CMDSTAT_EI (1<<23) |
| 267 | #define SDMA_DESC_CMDSTAT_O (1<<31) |
| 268 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 269 | #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \ |
| 270 | | SDMA_DESC_CMDSTAT_EI) |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 271 | |
| 272 | #define SDMA_SDC_RFT (1<<0) |
| 273 | #define SDMA_SDC_SFM (1<<1) |
| 274 | #define SDMA_SDC_BLMR (1<<6) |
| 275 | #define SDMA_SDC_BLMT (1<<7) |
| 276 | #define SDMA_SDC_POVR (1<<8) |
| 277 | #define SDMA_SDC_RIFB (1<<9) |
| 278 | |
| 279 | #define SDMA_SDCM_ERD (1<<7) |
| 280 | #define SDMA_SDCM_AR (1<<15) |
| 281 | #define SDMA_SDCM_STD (1<<16) |
| 282 | #define SDMA_SDCM_TXD (1<<23) |
| 283 | #define SDMA_SDCM_AT (1<<31) |
| 284 | |
| 285 | #define SDMA_0_CAUSE_RXBUF (1<<0) |
| 286 | #define SDMA_0_CAUSE_RXERR (1<<1) |
| 287 | #define SDMA_0_CAUSE_TXBUF (1<<2) |
| 288 | #define SDMA_0_CAUSE_TXEND (1<<3) |
| 289 | #define SDMA_1_CAUSE_RXBUF (1<<8) |
| 290 | #define SDMA_1_CAUSE_RXERR (1<<9) |
| 291 | #define SDMA_1_CAUSE_TXBUF (1<<10) |
| 292 | #define SDMA_1_CAUSE_TXEND (1<<11) |
| 293 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 294 | #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \ |
| 295 | | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) |
| 296 | #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \ |
| 297 | | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) |
Mark A. Greer | e4294b3 | 2006-03-25 03:08:28 -0800 | [diff] [blame] | 298 | |
| 299 | /* SDMA Interrupt registers */ |
| 300 | #define SDMA_INTR_CAUSE 0x0000 |
| 301 | #define SDMA_INTR_MASK 0x0080 |
| 302 | |
| 303 | /* Baud Rate Generator Interface Registers */ |
| 304 | #define BRG_BCR 0x0000 |
| 305 | #define BRG_BTR 0x0004 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * Define how this driver is known to the outside (we've been assigned a |
| 309 | * range on the "Low-density serial ports" major). |
| 310 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 311 | #define MPSC_MAJOR 204 |
| 312 | #define MPSC_MINOR_START 44 |
| 313 | #define MPSC_DRIVER_NAME "MPSC" |
| 314 | #define MPSC_DEV_NAME "ttyMM" |
| 315 | #define MPSC_VERSION "1.00" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | |
| 317 | static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS]; |
| 318 | static struct mpsc_shared_regs mpsc_shared_regs; |
Lee Nicks | 4d0145a | 2005-06-25 14:55:36 -0700 | [diff] [blame] | 319 | static struct uart_driver mpsc_reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | |
Lee Nicks | 4d0145a | 2005-06-25 14:55:36 -0700 | [diff] [blame] | 321 | static void mpsc_start_rx(struct mpsc_port_info *pi); |
| 322 | static void mpsc_free_ring_mem(struct mpsc_port_info *pi); |
| 323 | static void mpsc_release_port(struct uart_port *port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | /* |
| 325 | ****************************************************************************** |
| 326 | * |
| 327 | * Baud Rate Generator Routines (BRG) |
| 328 | * |
| 329 | ****************************************************************************** |
| 330 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 331 | static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | { |
| 333 | u32 v; |
| 334 | |
| 335 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); |
| 336 | v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18); |
| 337 | |
| 338 | if (pi->brg_can_tune) |
| 339 | v &= ~(1 << 25); |
| 340 | |
| 341 | if (pi->mirror_regs) |
| 342 | pi->BRG_BCR_m = v; |
| 343 | writel(v, pi->brg_base + BRG_BCR); |
| 344 | |
| 345 | writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, |
| 346 | pi->brg_base + BRG_BTR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | } |
| 348 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 349 | static void mpsc_brg_enable(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | { |
| 351 | u32 v; |
| 352 | |
| 353 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); |
| 354 | v |= (1 << 16); |
| 355 | |
| 356 | if (pi->mirror_regs) |
| 357 | pi->BRG_BCR_m = v; |
| 358 | writel(v, pi->brg_base + BRG_BCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | } |
| 360 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 361 | static void mpsc_brg_disable(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | { |
| 363 | u32 v; |
| 364 | |
| 365 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); |
| 366 | v &= ~(1 << 16); |
| 367 | |
| 368 | if (pi->mirror_regs) |
| 369 | pi->BRG_BCR_m = v; |
| 370 | writel(v, pi->brg_base + BRG_BCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | } |
| 372 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 373 | /* |
| 374 | * To set the baud, we adjust the CDV field in the BRG_BCR reg. |
| 375 | * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1. |
| 376 | * However, the input clock is divided by 16 in the MPSC b/c of how |
| 377 | * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our |
| 378 | * calculation by 16 to account for that. So the real calculation |
| 379 | * that accounts for the way the mpsc is set up is: |
| 380 | * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1. |
| 381 | */ |
| 382 | static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; |
| 385 | u32 v; |
| 386 | |
| 387 | mpsc_brg_disable(pi); |
| 388 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); |
| 389 | v = (v & 0xffff0000) | (cdv & 0xffff); |
| 390 | |
| 391 | if (pi->mirror_regs) |
| 392 | pi->BRG_BCR_m = v; |
| 393 | writel(v, pi->brg_base + BRG_BCR); |
| 394 | mpsc_brg_enable(pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | /* |
| 398 | ****************************************************************************** |
| 399 | * |
| 400 | * Serial DMA Routines (SDMA) |
| 401 | * |
| 402 | ****************************************************************************** |
| 403 | */ |
| 404 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 405 | static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | { |
| 407 | u32 v; |
| 408 | |
| 409 | pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n", |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 410 | pi->port.line, burst_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | |
| 412 | burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */ |
| 413 | |
| 414 | if (burst_size < 2) |
| 415 | v = 0x0; /* 1 64-bit word */ |
| 416 | else if (burst_size < 4) |
| 417 | v = 0x1; /* 2 64-bit words */ |
| 418 | else if (burst_size < 8) |
| 419 | v = 0x2; /* 4 64-bit words */ |
| 420 | else |
| 421 | v = 0x3; /* 8 64-bit words */ |
| 422 | |
| 423 | writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), |
| 424 | pi->sdma_base + SDMA_SDC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | } |
| 426 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 427 | static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | { |
| 429 | pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, |
| 430 | burst_size); |
| 431 | |
| 432 | writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, |
| 433 | pi->sdma_base + SDMA_SDC); |
| 434 | mpsc_sdma_burstsize(pi, burst_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | } |
| 436 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 437 | static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | { |
| 439 | u32 old, v; |
| 440 | |
| 441 | pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); |
| 442 | |
| 443 | old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : |
| 444 | readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); |
| 445 | |
| 446 | mask &= 0xf; |
| 447 | if (pi->port.line) |
| 448 | mask <<= 8; |
| 449 | v &= ~mask; |
| 450 | |
| 451 | if (pi->mirror_regs) |
| 452 | pi->shared_regs->SDMA_INTR_MASK_m = v; |
| 453 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); |
| 454 | |
| 455 | if (pi->port.line) |
| 456 | old >>= 8; |
| 457 | return old & 0xf; |
| 458 | } |
| 459 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 460 | static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | { |
| 462 | u32 v; |
| 463 | |
| 464 | pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); |
| 465 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 466 | v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m |
| 467 | : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | |
| 469 | mask &= 0xf; |
| 470 | if (pi->port.line) |
| 471 | mask <<= 8; |
| 472 | v |= mask; |
| 473 | |
| 474 | if (pi->mirror_regs) |
| 475 | pi->shared_regs->SDMA_INTR_MASK_m = v; |
| 476 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | } |
| 478 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 479 | static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | { |
| 481 | pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); |
| 482 | |
| 483 | if (pi->mirror_regs) |
| 484 | pi->shared_regs->SDMA_INTR_CAUSE_m = 0; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 485 | writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE |
| 486 | + pi->port.line); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | } |
| 488 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 489 | static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, |
| 490 | struct mpsc_rx_desc *rxre_p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | { |
| 492 | pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 493 | pi->port.line, (u32)rxre_p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | |
| 495 | writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | } |
| 497 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 498 | static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, |
| 499 | struct mpsc_tx_desc *txre_p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | { |
| 501 | writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); |
| 502 | writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | } |
| 504 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 505 | static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | { |
| 507 | u32 v; |
| 508 | |
| 509 | v = readl(pi->sdma_base + SDMA_SDCM); |
| 510 | if (val) |
| 511 | v |= val; |
| 512 | else |
| 513 | v = 0; |
| 514 | wmb(); |
| 515 | writel(v, pi->sdma_base + SDMA_SDCM); |
| 516 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | } |
| 518 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 519 | static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | { |
| 521 | return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; |
| 522 | } |
| 523 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 524 | static void mpsc_sdma_start_tx(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | { |
| 526 | struct mpsc_tx_desc *txre, *txre_p; |
| 527 | |
| 528 | /* If tx isn't running & there's a desc ready to go, start it */ |
| 529 | if (!mpsc_sdma_tx_active(pi)) { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 530 | txre = (struct mpsc_tx_desc *)(pi->txr |
| 531 | + (pi->txr_tail * MPSC_TXRE_SIZE)); |
| 532 | dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, |
| 533 | DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 535 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 536 | invalidate_dcache_range((ulong)txre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 537 | (ulong)txre + MPSC_TXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | #endif |
| 539 | |
| 540 | if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 541 | txre_p = (struct mpsc_tx_desc *) |
| 542 | (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | |
| 544 | mpsc_sdma_set_tx_ring(pi, txre_p); |
| 545 | mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); |
| 546 | } |
| 547 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | } |
| 549 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 550 | static void mpsc_sdma_stop(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | { |
| 552 | pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); |
| 553 | |
| 554 | /* Abort any SDMA transfers */ |
| 555 | mpsc_sdma_cmd(pi, 0); |
| 556 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); |
| 557 | |
| 558 | /* Clear the SDMA current and first TX and RX pointers */ |
Al Viro | 2c6e759 | 2005-04-25 18:32:12 -0700 | [diff] [blame] | 559 | mpsc_sdma_set_tx_ring(pi, NULL); |
| 560 | mpsc_sdma_set_rx_ring(pi, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 561 | |
| 562 | /* Disable interrupts */ |
| 563 | mpsc_sdma_intr_mask(pi, 0xf); |
| 564 | mpsc_sdma_intr_ack(pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | } |
| 566 | |
| 567 | /* |
| 568 | ****************************************************************************** |
| 569 | * |
| 570 | * Multi-Protocol Serial Controller Routines (MPSC) |
| 571 | * |
| 572 | ****************************************************************************** |
| 573 | */ |
| 574 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 575 | static void mpsc_hw_init(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 576 | { |
| 577 | u32 v; |
| 578 | |
| 579 | pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); |
| 580 | |
| 581 | /* Set up clock routing */ |
| 582 | if (pi->mirror_regs) { |
| 583 | v = pi->shared_regs->MPSC_MRR_m; |
| 584 | v &= ~0x1c7; |
| 585 | pi->shared_regs->MPSC_MRR_m = v; |
| 586 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); |
| 587 | |
| 588 | v = pi->shared_regs->MPSC_RCRR_m; |
| 589 | v = (v & ~0xf0f) | 0x100; |
| 590 | pi->shared_regs->MPSC_RCRR_m = v; |
| 591 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); |
| 592 | |
| 593 | v = pi->shared_regs->MPSC_TCRR_m; |
| 594 | v = (v & ~0xf0f) | 0x100; |
| 595 | pi->shared_regs->MPSC_TCRR_m = v; |
| 596 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 597 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); |
| 599 | v &= ~0x1c7; |
| 600 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); |
| 601 | |
| 602 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); |
| 603 | v = (v & ~0xf0f) | 0x100; |
| 604 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); |
| 605 | |
| 606 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); |
| 607 | v = (v & ~0xf0f) | 0x100; |
| 608 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); |
| 609 | } |
| 610 | |
| 611 | /* Put MPSC in UART mode & enabel Tx/Rx egines */ |
| 612 | writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); |
| 613 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 614 | /* No preamble, 16x divider, low-latency, */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); |
Mark A. Greer | 7bbdc3d | 2008-02-04 22:27:54 -0800 | [diff] [blame] | 616 | mpsc_set_baudrate(pi, pi->default_baud); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | |
| 618 | if (pi->mirror_regs) { |
| 619 | pi->MPSC_CHR_1_m = 0; |
| 620 | pi->MPSC_CHR_2_m = 0; |
| 621 | } |
| 622 | writel(0, pi->mpsc_base + MPSC_CHR_1); |
| 623 | writel(0, pi->mpsc_base + MPSC_CHR_2); |
| 624 | writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); |
| 625 | writel(0, pi->mpsc_base + MPSC_CHR_4); |
| 626 | writel(0, pi->mpsc_base + MPSC_CHR_5); |
| 627 | writel(0, pi->mpsc_base + MPSC_CHR_6); |
| 628 | writel(0, pi->mpsc_base + MPSC_CHR_7); |
| 629 | writel(0, pi->mpsc_base + MPSC_CHR_8); |
| 630 | writel(0, pi->mpsc_base + MPSC_CHR_9); |
| 631 | writel(0, pi->mpsc_base + MPSC_CHR_10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | } |
| 633 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 634 | static void mpsc_enter_hunt(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | { |
| 636 | pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); |
| 637 | |
| 638 | if (pi->mirror_regs) { |
| 639 | writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, |
| 640 | pi->mpsc_base + MPSC_CHR_2); |
| 641 | /* Erratum prevents reading CHR_2 so just delay for a while */ |
| 642 | udelay(100); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 643 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 645 | pi->mpsc_base + MPSC_CHR_2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | |
| 647 | while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) |
| 648 | udelay(10); |
| 649 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | } |
| 651 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 652 | static void mpsc_freeze(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | { |
| 654 | u32 v; |
| 655 | |
| 656 | pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); |
| 657 | |
| 658 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : |
| 659 | readl(pi->mpsc_base + MPSC_MPCR); |
| 660 | v |= MPSC_MPCR_FRZ; |
| 661 | |
| 662 | if (pi->mirror_regs) |
| 663 | pi->MPSC_MPCR_m = v; |
| 664 | writel(v, pi->mpsc_base + MPSC_MPCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | } |
| 666 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 667 | static void mpsc_unfreeze(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | { |
| 669 | u32 v; |
| 670 | |
| 671 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : |
| 672 | readl(pi->mpsc_base + MPSC_MPCR); |
| 673 | v &= ~MPSC_MPCR_FRZ; |
| 674 | |
| 675 | if (pi->mirror_regs) |
| 676 | pi->MPSC_MPCR_m = v; |
| 677 | writel(v, pi->mpsc_base + MPSC_MPCR); |
| 678 | |
| 679 | pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | } |
| 681 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 682 | static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 683 | { |
| 684 | u32 v; |
| 685 | |
| 686 | pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); |
| 687 | |
| 688 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : |
| 689 | readl(pi->mpsc_base + MPSC_MPCR); |
| 690 | v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12); |
| 691 | |
| 692 | if (pi->mirror_regs) |
| 693 | pi->MPSC_MPCR_m = v; |
| 694 | writel(v, pi->mpsc_base + MPSC_MPCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 695 | } |
| 696 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 697 | static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | { |
| 699 | u32 v; |
| 700 | |
| 701 | pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n", |
| 702 | pi->port.line, len); |
| 703 | |
| 704 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : |
| 705 | readl(pi->mpsc_base + MPSC_MPCR); |
| 706 | |
| 707 | v = (v & ~(1 << 14)) | ((len & 0x1) << 14); |
| 708 | |
| 709 | if (pi->mirror_regs) |
| 710 | pi->MPSC_MPCR_m = v; |
| 711 | writel(v, pi->mpsc_base + MPSC_MPCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 712 | } |
| 713 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 714 | static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | { |
| 716 | u32 v; |
| 717 | |
| 718 | pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); |
| 719 | |
| 720 | v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : |
| 721 | readl(pi->mpsc_base + MPSC_CHR_2); |
| 722 | |
| 723 | p &= 0x3; |
| 724 | v = (v & ~0xc000c) | (p << 18) | (p << 2); |
| 725 | |
| 726 | if (pi->mirror_regs) |
| 727 | pi->MPSC_CHR_2_m = v; |
| 728 | writel(v, pi->mpsc_base + MPSC_CHR_2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | /* |
| 732 | ****************************************************************************** |
| 733 | * |
| 734 | * Driver Init Routines |
| 735 | * |
| 736 | ****************************************************************************** |
| 737 | */ |
| 738 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 739 | static void mpsc_init_hw(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | { |
| 741 | pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); |
| 742 | |
| 743 | mpsc_brg_init(pi, pi->brg_clk_src); |
| 744 | mpsc_brg_enable(pi); |
| 745 | mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ |
| 746 | mpsc_sdma_stop(pi); |
| 747 | mpsc_hw_init(pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 748 | } |
| 749 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 750 | static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | { |
| 752 | int rc = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | |
| 754 | pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n", |
| 755 | pi->port.line); |
| 756 | |
| 757 | if (!pi->dma_region) { |
| 758 | if (!dma_supported(pi->port.dev, 0xffffffff)) { |
| 759 | printk(KERN_ERR "MPSC: Inadequate DMA support\n"); |
| 760 | rc = -ENXIO; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 761 | } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, |
| 762 | MPSC_DMA_ALLOC_SIZE, |
| 763 | &pi->dma_region_p, GFP_KERNEL)) |
| 764 | == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); |
| 766 | rc = -ENOMEM; |
| 767 | } |
| 768 | } |
| 769 | |
| 770 | return rc; |
| 771 | } |
| 772 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 773 | static void mpsc_free_ring_mem(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 774 | { |
| 775 | pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); |
| 776 | |
| 777 | if (pi->dma_region) { |
| 778 | dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 779 | pi->dma_region, pi->dma_region_p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | pi->dma_region = NULL; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 781 | pi->dma_region_p = (dma_addr_t)NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | } |
| 784 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 785 | static void mpsc_init_rings(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | { |
| 787 | struct mpsc_rx_desc *rxre; |
| 788 | struct mpsc_tx_desc *txre; |
| 789 | dma_addr_t dp, dp_p; |
| 790 | u8 *bp, *bp_p; |
| 791 | int i; |
| 792 | |
| 793 | pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); |
| 794 | |
| 795 | BUG_ON(pi->dma_region == NULL); |
| 796 | |
| 797 | memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); |
| 798 | |
| 799 | /* |
| 800 | * Descriptors & buffers are multiples of cacheline size and must be |
| 801 | * cacheline aligned. |
| 802 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 803 | dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment()); |
| 804 | dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | |
| 806 | /* |
| 807 | * Partition dma region into rx ring descriptor, rx buffers, |
| 808 | * tx ring descriptors, and tx buffers. |
| 809 | */ |
| 810 | pi->rxr = dp; |
| 811 | pi->rxr_p = dp_p; |
| 812 | dp += MPSC_RXR_SIZE; |
| 813 | dp_p += MPSC_RXR_SIZE; |
| 814 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 815 | pi->rxb = (u8 *)dp; |
| 816 | pi->rxb_p = (u8 *)dp_p; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | dp += MPSC_RXB_SIZE; |
| 818 | dp_p += MPSC_RXB_SIZE; |
| 819 | |
| 820 | pi->rxr_posn = 0; |
| 821 | |
| 822 | pi->txr = dp; |
| 823 | pi->txr_p = dp_p; |
| 824 | dp += MPSC_TXR_SIZE; |
| 825 | dp_p += MPSC_TXR_SIZE; |
| 826 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 827 | pi->txb = (u8 *)dp; |
| 828 | pi->txb_p = (u8 *)dp_p; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 829 | |
| 830 | pi->txr_head = 0; |
| 831 | pi->txr_tail = 0; |
| 832 | |
| 833 | /* Init rx ring descriptors */ |
| 834 | dp = pi->rxr; |
| 835 | dp_p = pi->rxr_p; |
| 836 | bp = pi->rxb; |
| 837 | bp_p = pi->rxb_p; |
| 838 | |
| 839 | for (i = 0; i < MPSC_RXR_ENTRIES; i++) { |
| 840 | rxre = (struct mpsc_rx_desc *)dp; |
| 841 | |
| 842 | rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); |
| 843 | rxre->bytecnt = cpu_to_be16(0); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 844 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
| 845 | | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F |
| 846 | | SDMA_DESC_CMDSTAT_L); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); |
| 848 | rxre->buf_ptr = cpu_to_be32(bp_p); |
| 849 | |
| 850 | dp += MPSC_RXRE_SIZE; |
| 851 | dp_p += MPSC_RXRE_SIZE; |
| 852 | bp += MPSC_RXBE_SIZE; |
| 853 | bp_p += MPSC_RXBE_SIZE; |
| 854 | } |
| 855 | rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ |
| 856 | |
| 857 | /* Init tx ring descriptors */ |
| 858 | dp = pi->txr; |
| 859 | dp_p = pi->txr_p; |
| 860 | bp = pi->txb; |
| 861 | bp_p = pi->txb_p; |
| 862 | |
| 863 | for (i = 0; i < MPSC_TXR_ENTRIES; i++) { |
| 864 | txre = (struct mpsc_tx_desc *)dp; |
| 865 | |
| 866 | txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE); |
| 867 | txre->buf_ptr = cpu_to_be32(bp_p); |
| 868 | |
| 869 | dp += MPSC_TXRE_SIZE; |
| 870 | dp_p += MPSC_TXRE_SIZE; |
| 871 | bp += MPSC_TXBE_SIZE; |
| 872 | bp_p += MPSC_TXBE_SIZE; |
| 873 | } |
| 874 | txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ |
| 875 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 876 | dma_cache_sync(pi->port.dev, (void *)pi->dma_region, |
| 877 | MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 879 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 880 | flush_dcache_range((ulong)pi->dma_region, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 881 | (ulong)pi->dma_region |
| 882 | + MPSC_DMA_ALLOC_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | #endif |
| 884 | |
| 885 | return; |
| 886 | } |
| 887 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 888 | static void mpsc_uninit_rings(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | { |
| 890 | pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); |
| 891 | |
| 892 | BUG_ON(pi->dma_region == NULL); |
| 893 | |
| 894 | pi->rxr = 0; |
| 895 | pi->rxr_p = 0; |
| 896 | pi->rxb = NULL; |
| 897 | pi->rxb_p = NULL; |
| 898 | pi->rxr_posn = 0; |
| 899 | |
| 900 | pi->txr = 0; |
| 901 | pi->txr_p = 0; |
| 902 | pi->txb = NULL; |
| 903 | pi->txb_p = NULL; |
| 904 | pi->txr_head = 0; |
| 905 | pi->txr_tail = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | } |
| 907 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 908 | static int mpsc_make_ready(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 909 | { |
| 910 | int rc; |
| 911 | |
| 912 | pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); |
| 913 | |
| 914 | if (!pi->ready) { |
| 915 | mpsc_init_hw(pi); |
| 916 | if ((rc = mpsc_alloc_ring_mem(pi))) |
| 917 | return rc; |
| 918 | mpsc_init_rings(pi); |
| 919 | pi->ready = 1; |
| 920 | } |
| 921 | |
| 922 | return 0; |
| 923 | } |
| 924 | |
Jason Wessel | 3b216c9 | 2008-07-23 11:30:16 -0500 | [diff] [blame] | 925 | #ifdef CONFIG_CONSOLE_POLL |
| 926 | static int serial_polled; |
| 927 | #endif |
| 928 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 929 | /* |
| 930 | ****************************************************************************** |
| 931 | * |
| 932 | * Interrupt Handling Routines |
| 933 | * |
| 934 | ****************************************************************************** |
| 935 | */ |
| 936 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 937 | static int mpsc_rx_intr(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | { |
| 939 | struct mpsc_rx_desc *rxre; |
Alan Cox | ebd2c8f | 2009-09-19 13:13:28 -0700 | [diff] [blame] | 940 | struct tty_struct *tty = pi->port.state->port.tty; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 941 | u32 cmdstat, bytes_in, i; |
| 942 | int rc = 0; |
| 943 | u8 *bp; |
| 944 | char flag = TTY_NORMAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 945 | |
| 946 | pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); |
| 947 | |
| 948 | rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); |
| 949 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 950 | dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, |
| 951 | DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 952 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 953 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 954 | invalidate_dcache_range((ulong)rxre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 955 | (ulong)rxre + MPSC_RXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | #endif |
| 957 | |
| 958 | /* |
| 959 | * Loop through Rx descriptors handling ones that have been completed. |
| 960 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 961 | while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) |
| 962 | & SDMA_DESC_CMDSTAT_O)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 963 | bytes_in = be16_to_cpu(rxre->bytecnt); |
Jason Wessel | 3b216c9 | 2008-07-23 11:30:16 -0500 | [diff] [blame] | 964 | #ifdef CONFIG_CONSOLE_POLL |
| 965 | if (unlikely(serial_polled)) { |
| 966 | serial_polled = 0; |
| 967 | return 0; |
| 968 | } |
| 969 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 970 | /* Following use of tty struct directly is deprecated */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 971 | if (unlikely(tty_buffer_request_room(tty, bytes_in) |
| 972 | < bytes_in)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 973 | if (tty->low_latency) |
| 974 | tty_flip_buffer_push(tty); |
| 975 | /* |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 976 | * If this failed then we will throw away the bytes |
| 977 | * but must do so to clear interrupts. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 978 | */ |
| 979 | } |
| 980 | |
| 981 | bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 982 | dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE, |
| 983 | DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 985 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 986 | invalidate_dcache_range((ulong)bp, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 987 | (ulong)bp + MPSC_RXBE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 988 | #endif |
| 989 | |
| 990 | /* |
| 991 | * Other than for parity error, the manual provides little |
| 992 | * info on what data will be in a frame flagged by any of |
| 993 | * these errors. For parity error, it is the last byte in |
| 994 | * the buffer that had the error. As for the rest, I guess |
| 995 | * we'll assume there is no data in the buffer. |
| 996 | * If there is...it gets lost. |
| 997 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 998 | if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
| 999 | | SDMA_DESC_CMDSTAT_FR |
| 1000 | | SDMA_DESC_CMDSTAT_OR))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | |
| 1002 | pi->port.icount.rx++; |
| 1003 | |
| 1004 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */ |
| 1005 | pi->port.icount.brk++; |
| 1006 | |
| 1007 | if (uart_handle_break(&pi->port)) |
| 1008 | goto next_frame; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1009 | } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | pi->port.icount.frame++; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1011 | } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | pi->port.icount.overrun++; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1013 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | |
| 1015 | cmdstat &= pi->port.read_status_mask; |
| 1016 | |
| 1017 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) |
| 1018 | flag = TTY_BREAK; |
| 1019 | else if (cmdstat & SDMA_DESC_CMDSTAT_FR) |
| 1020 | flag = TTY_FRAME; |
| 1021 | else if (cmdstat & SDMA_DESC_CMDSTAT_OR) |
| 1022 | flag = TTY_OVERRUN; |
| 1023 | else if (cmdstat & SDMA_DESC_CMDSTAT_PE) |
| 1024 | flag = TTY_PARITY; |
| 1025 | } |
| 1026 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1027 | if (uart_handle_sysrq_char(&pi->port, *bp)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | bp++; |
| 1029 | bytes_in--; |
Jason Wessel | 3b216c9 | 2008-07-23 11:30:16 -0500 | [diff] [blame] | 1030 | #ifdef CONFIG_CONSOLE_POLL |
| 1031 | if (unlikely(serial_polled)) { |
| 1032 | serial_polled = 0; |
| 1033 | return 0; |
| 1034 | } |
| 1035 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | goto next_frame; |
| 1037 | } |
| 1038 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1039 | if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
| 1040 | | SDMA_DESC_CMDSTAT_FR |
| 1041 | | SDMA_DESC_CMDSTAT_OR))) |
| 1042 | && !(cmdstat & pi->port.ignore_status_mask)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | tty_insert_flip_char(tty, *bp, flag); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1044 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1045 | for (i=0; i<bytes_in; i++) |
| 1046 | tty_insert_flip_char(tty, *bp++, TTY_NORMAL); |
| 1047 | |
| 1048 | pi->port.icount.rx += bytes_in; |
| 1049 | } |
| 1050 | |
| 1051 | next_frame: |
| 1052 | rxre->bytecnt = cpu_to_be16(0); |
| 1053 | wmb(); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1054 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
| 1055 | | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F |
| 1056 | | SDMA_DESC_CMDSTAT_L); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | wmb(); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1058 | dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, |
| 1059 | DMA_BIDIRECTIONAL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1061 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1062 | flush_dcache_range((ulong)rxre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1063 | (ulong)rxre + MPSC_RXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | #endif |
| 1065 | |
| 1066 | /* Advance to next descriptor */ |
| 1067 | pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1068 | rxre = (struct mpsc_rx_desc *) |
| 1069 | (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE)); |
| 1070 | dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, |
| 1071 | DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1072 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1073 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1074 | invalidate_dcache_range((ulong)rxre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1075 | (ulong)rxre + MPSC_RXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | rc = 1; |
| 1078 | } |
| 1079 | |
| 1080 | /* Restart rx engine, if its stopped */ |
| 1081 | if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) |
| 1082 | mpsc_start_rx(pi); |
| 1083 | |
| 1084 | tty_flip_buffer_push(tty); |
| 1085 | return rc; |
| 1086 | } |
| 1087 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1088 | static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | { |
| 1090 | struct mpsc_tx_desc *txre; |
| 1091 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1092 | txre = (struct mpsc_tx_desc *)(pi->txr |
| 1093 | + (pi->txr_head * MPSC_TXRE_SIZE)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1094 | |
| 1095 | txre->bytecnt = cpu_to_be16(count); |
| 1096 | txre->shadow = txre->bytecnt; |
| 1097 | wmb(); /* ensure cmdstat is last field updated */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1098 | txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
| 1099 | | SDMA_DESC_CMDSTAT_L |
| 1100 | | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1101 | wmb(); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1102 | dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, |
| 1103 | DMA_BIDIRECTIONAL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1104 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1105 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1106 | flush_dcache_range((ulong)txre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1107 | (ulong)txre + MPSC_TXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1109 | } |
| 1110 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1111 | static void mpsc_copy_tx_data(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1112 | { |
Alan Cox | ebd2c8f | 2009-09-19 13:13:28 -0700 | [diff] [blame] | 1113 | struct circ_buf *xmit = &pi->port.state->xmit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1114 | u8 *bp; |
| 1115 | u32 i; |
| 1116 | |
| 1117 | /* Make sure the desc ring isn't full */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1118 | while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) |
| 1119 | < (MPSC_TXR_ENTRIES - 1)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1120 | if (pi->port.x_char) { |
| 1121 | /* |
| 1122 | * Ideally, we should use the TCS field in |
| 1123 | * CHR_1 to put the x_char out immediately but |
| 1124 | * errata prevents us from being able to read |
| 1125 | * CHR_2 to know that its safe to write to |
| 1126 | * CHR_1. Instead, just put it in-band with |
| 1127 | * all the other Tx data. |
| 1128 | */ |
| 1129 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); |
| 1130 | *bp = pi->port.x_char; |
| 1131 | pi->port.x_char = 0; |
| 1132 | i = 1; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1133 | } else if (!uart_circ_empty(xmit) |
| 1134 | && !uart_tx_stopped(&pi->port)) { |
| 1135 | i = min((u32)MPSC_TXBE_SIZE, |
| 1136 | (u32)uart_circ_chars_pending(xmit)); |
| 1137 | i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1138 | UART_XMIT_SIZE)); |
| 1139 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); |
| 1140 | memcpy(bp, &xmit->buf[xmit->tail], i); |
| 1141 | xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1); |
| 1142 | |
| 1143 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 1144 | uart_write_wakeup(&pi->port); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1145 | } else { /* All tx data copied into ring bufs */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | return; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1147 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1148 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1149 | dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, |
| 1150 | DMA_BIDIRECTIONAL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1152 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1153 | flush_dcache_range((ulong)bp, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1154 | (ulong)bp + MPSC_TXBE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1155 | #endif |
| 1156 | mpsc_setup_tx_desc(pi, i, 1); |
| 1157 | |
| 1158 | /* Advance to next descriptor */ |
| 1159 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); |
| 1160 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1161 | } |
| 1162 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1163 | static int mpsc_tx_intr(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | { |
| 1165 | struct mpsc_tx_desc *txre; |
| 1166 | int rc = 0; |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1167 | unsigned long iflags; |
| 1168 | |
| 1169 | spin_lock_irqsave(&pi->tx_lock, iflags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1170 | |
| 1171 | if (!mpsc_sdma_tx_active(pi)) { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1172 | txre = (struct mpsc_tx_desc *)(pi->txr |
| 1173 | + (pi->txr_tail * MPSC_TXRE_SIZE)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1175 | dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, |
| 1176 | DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1178 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1179 | invalidate_dcache_range((ulong)txre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1180 | (ulong)txre + MPSC_TXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | #endif |
| 1182 | |
| 1183 | while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) { |
| 1184 | rc = 1; |
| 1185 | pi->port.icount.tx += be16_to_cpu(txre->bytecnt); |
| 1186 | pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); |
| 1187 | |
| 1188 | /* If no more data to tx, fall out of loop */ |
| 1189 | if (pi->txr_head == pi->txr_tail) |
| 1190 | break; |
| 1191 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1192 | txre = (struct mpsc_tx_desc *)(pi->txr |
| 1193 | + (pi->txr_tail * MPSC_TXRE_SIZE)); |
| 1194 | dma_cache_sync(pi->port.dev, (void *)txre, |
| 1195 | MPSC_TXRE_SIZE, DMA_FROM_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1196 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1197 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1198 | invalidate_dcache_range((ulong)txre, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1199 | (ulong)txre + MPSC_TXRE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | #endif |
| 1201 | } |
| 1202 | |
| 1203 | mpsc_copy_tx_data(pi); |
| 1204 | mpsc_sdma_start_tx(pi); /* start next desc if ready */ |
| 1205 | } |
| 1206 | |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1207 | spin_unlock_irqrestore(&pi->tx_lock, iflags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | return rc; |
| 1209 | } |
| 1210 | |
| 1211 | /* |
| 1212 | * This is the driver's interrupt handler. To avoid a race, we first clear |
| 1213 | * the interrupt, then handle any completed Rx/Tx descriptors. When done |
| 1214 | * handling those descriptors, we restart the Rx/Tx engines if they're stopped. |
| 1215 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1216 | static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | { |
| 1218 | struct mpsc_port_info *pi = dev_id; |
| 1219 | ulong iflags; |
| 1220 | int rc = IRQ_NONE; |
| 1221 | |
| 1222 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); |
| 1223 | |
| 1224 | spin_lock_irqsave(&pi->port.lock, iflags); |
| 1225 | mpsc_sdma_intr_ack(pi); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1226 | if (mpsc_rx_intr(pi)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1227 | rc = IRQ_HANDLED; |
| 1228 | if (mpsc_tx_intr(pi)) |
| 1229 | rc = IRQ_HANDLED; |
| 1230 | spin_unlock_irqrestore(&pi->port.lock, iflags); |
| 1231 | |
| 1232 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); |
| 1233 | return rc; |
| 1234 | } |
| 1235 | |
| 1236 | /* |
| 1237 | ****************************************************************************** |
| 1238 | * |
| 1239 | * serial_core.c Interface routines |
| 1240 | * |
| 1241 | ****************************************************************************** |
| 1242 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1243 | static uint mpsc_tx_empty(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1244 | { |
| 1245 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1246 | ulong iflags; |
| 1247 | uint rc; |
| 1248 | |
| 1249 | spin_lock_irqsave(&pi->port.lock, iflags); |
| 1250 | rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; |
| 1251 | spin_unlock_irqrestore(&pi->port.lock, iflags); |
| 1252 | |
| 1253 | return rc; |
| 1254 | } |
| 1255 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1256 | static void mpsc_set_mctrl(struct uart_port *port, uint mctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | { |
| 1258 | /* Have no way to set modem control lines AFAICT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1259 | } |
| 1260 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1261 | static uint mpsc_get_mctrl(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | { |
| 1263 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1264 | u32 mflags, status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1266 | status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m |
| 1267 | : readl(pi->mpsc_base + MPSC_CHR_10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | |
| 1269 | mflags = 0; |
| 1270 | if (status & 0x1) |
| 1271 | mflags |= TIOCM_CTS; |
| 1272 | if (status & 0x2) |
| 1273 | mflags |= TIOCM_CAR; |
| 1274 | |
| 1275 | return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ |
| 1276 | } |
| 1277 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1278 | static void mpsc_stop_tx(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1279 | { |
| 1280 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1281 | |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1282 | pr_debug("mpsc_stop_tx[%d]\n", port->line); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1283 | |
| 1284 | mpsc_freeze(pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1285 | } |
| 1286 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1287 | static void mpsc_start_tx(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1288 | { |
| 1289 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1290 | unsigned long iflags; |
| 1291 | |
| 1292 | spin_lock_irqsave(&pi->tx_lock, iflags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1293 | |
| 1294 | mpsc_unfreeze(pi); |
| 1295 | mpsc_copy_tx_data(pi); |
| 1296 | mpsc_sdma_start_tx(pi); |
| 1297 | |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1298 | spin_unlock_irqrestore(&pi->tx_lock, iflags); |
| 1299 | |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1300 | pr_debug("mpsc_start_tx[%d]\n", port->line); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1301 | } |
| 1302 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1303 | static void mpsc_start_rx(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | { |
| 1305 | pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); |
| 1306 | |
| 1307 | if (pi->rcv_data) { |
| 1308 | mpsc_enter_hunt(pi); |
| 1309 | mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); |
| 1310 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1311 | } |
| 1312 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1313 | static void mpsc_stop_rx(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1314 | { |
| 1315 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1316 | |
| 1317 | pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line); |
| 1318 | |
Carlos Sanchez | 6c1ead5 | 2007-07-31 00:38:59 -0700 | [diff] [blame] | 1319 | if (pi->mirror_regs) { |
| 1320 | writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA, |
| 1321 | pi->mpsc_base + MPSC_CHR_2); |
| 1322 | /* Erratum prevents reading CHR_2 so just delay for a while */ |
| 1323 | udelay(100); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1324 | } else { |
Carlos Sanchez | 6c1ead5 | 2007-07-31 00:38:59 -0700 | [diff] [blame] | 1325 | writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1326 | pi->mpsc_base + MPSC_CHR_2); |
Carlos Sanchez | 6c1ead5 | 2007-07-31 00:38:59 -0700 | [diff] [blame] | 1327 | |
| 1328 | while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA) |
| 1329 | udelay(10); |
| 1330 | } |
| 1331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | } |
| 1334 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1335 | static void mpsc_enable_ms(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1337 | } |
| 1338 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1339 | static void mpsc_break_ctl(struct uart_port *port, int ctl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1340 | { |
| 1341 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1342 | ulong flags; |
| 1343 | u32 v; |
| 1344 | |
| 1345 | v = ctl ? 0x00ff0000 : 0; |
| 1346 | |
| 1347 | spin_lock_irqsave(&pi->port.lock, flags); |
| 1348 | if (pi->mirror_regs) |
| 1349 | pi->MPSC_CHR_1_m = v; |
| 1350 | writel(v, pi->mpsc_base + MPSC_CHR_1); |
| 1351 | spin_unlock_irqrestore(&pi->port.lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | } |
| 1353 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1354 | static int mpsc_startup(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1355 | { |
| 1356 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1357 | u32 flag = 0; |
| 1358 | int rc; |
| 1359 | |
| 1360 | pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n", |
| 1361 | port->line, pi->port.irq); |
| 1362 | |
| 1363 | if ((rc = mpsc_make_ready(pi)) == 0) { |
| 1364 | /* Setup IRQ handler */ |
| 1365 | mpsc_sdma_intr_ack(pi); |
| 1366 | |
| 1367 | /* If irq's are shared, need to set flag */ |
| 1368 | if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq) |
Thomas Gleixner | 40663cc | 2006-07-01 19:29:43 -0700 | [diff] [blame] | 1369 | flag = IRQF_SHARED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1370 | |
| 1371 | if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1372 | "mpsc-sdma", pi)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1374 | pi->port.irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | |
| 1376 | mpsc_sdma_intr_unmask(pi, 0xf); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1377 | mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p |
| 1378 | + (pi->rxr_posn * MPSC_RXRE_SIZE))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1379 | } |
| 1380 | |
| 1381 | return rc; |
| 1382 | } |
| 1383 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1384 | static void mpsc_shutdown(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1385 | { |
| 1386 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | |
| 1388 | pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line); |
| 1389 | |
| 1390 | mpsc_sdma_stop(pi); |
| 1391 | free_irq(pi->port.irq, pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1392 | } |
| 1393 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1394 | static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios, |
Alan Cox | 606d099 | 2006-12-08 02:38:45 -0800 | [diff] [blame] | 1395 | struct ktermios *old) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1396 | { |
| 1397 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1398 | u32 baud; |
| 1399 | ulong flags; |
| 1400 | u32 chr_bits, stop_bits, par; |
| 1401 | |
| 1402 | pi->c_iflag = termios->c_iflag; |
| 1403 | pi->c_cflag = termios->c_cflag; |
| 1404 | |
| 1405 | switch (termios->c_cflag & CSIZE) { |
| 1406 | case CS5: |
| 1407 | chr_bits = MPSC_MPCR_CL_5; |
| 1408 | break; |
| 1409 | case CS6: |
| 1410 | chr_bits = MPSC_MPCR_CL_6; |
| 1411 | break; |
| 1412 | case CS7: |
| 1413 | chr_bits = MPSC_MPCR_CL_7; |
| 1414 | break; |
| 1415 | case CS8: |
| 1416 | default: |
| 1417 | chr_bits = MPSC_MPCR_CL_8; |
| 1418 | break; |
| 1419 | } |
| 1420 | |
| 1421 | if (termios->c_cflag & CSTOPB) |
| 1422 | stop_bits = MPSC_MPCR_SBL_2; |
| 1423 | else |
| 1424 | stop_bits = MPSC_MPCR_SBL_1; |
| 1425 | |
| 1426 | par = MPSC_CHR_2_PAR_EVEN; |
| 1427 | if (termios->c_cflag & PARENB) |
| 1428 | if (termios->c_cflag & PARODD) |
| 1429 | par = MPSC_CHR_2_PAR_ODD; |
| 1430 | #ifdef CMSPAR |
| 1431 | if (termios->c_cflag & CMSPAR) { |
| 1432 | if (termios->c_cflag & PARODD) |
| 1433 | par = MPSC_CHR_2_PAR_MARK; |
| 1434 | else |
| 1435 | par = MPSC_CHR_2_PAR_SPACE; |
| 1436 | } |
| 1437 | #endif |
| 1438 | |
| 1439 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); |
| 1440 | |
| 1441 | spin_lock_irqsave(&pi->port.lock, flags); |
| 1442 | |
| 1443 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1444 | |
| 1445 | mpsc_set_char_length(pi, chr_bits); |
| 1446 | mpsc_set_stop_bit_length(pi, stop_bits); |
| 1447 | mpsc_set_parity(pi, par); |
| 1448 | mpsc_set_baudrate(pi, baud); |
| 1449 | |
| 1450 | /* Characters/events to read */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; |
| 1452 | |
| 1453 | if (termios->c_iflag & INPCK) |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1454 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
| 1455 | | SDMA_DESC_CMDSTAT_FR; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1456 | |
| 1457 | if (termios->c_iflag & (BRKINT | PARMRK)) |
| 1458 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; |
| 1459 | |
| 1460 | /* Characters/events to ignore */ |
| 1461 | pi->port.ignore_status_mask = 0; |
| 1462 | |
| 1463 | if (termios->c_iflag & IGNPAR) |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1464 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
| 1465 | | SDMA_DESC_CMDSTAT_FR; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1466 | |
| 1467 | if (termios->c_iflag & IGNBRK) { |
| 1468 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; |
| 1469 | |
| 1470 | if (termios->c_iflag & IGNPAR) |
| 1471 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; |
| 1472 | } |
| 1473 | |
Stephane Chazelas | 5797ae3 | 2007-07-31 00:38:59 -0700 | [diff] [blame] | 1474 | if ((termios->c_cflag & CREAD)) { |
| 1475 | if (!pi->rcv_data) { |
| 1476 | pi->rcv_data = 1; |
| 1477 | mpsc_start_rx(pi); |
| 1478 | } |
| 1479 | } else if (pi->rcv_data) { |
| 1480 | mpsc_stop_rx(port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1481 | pi->rcv_data = 0; |
Stephane Chazelas | 5797ae3 | 2007-07-31 00:38:59 -0700 | [diff] [blame] | 1482 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | |
| 1484 | spin_unlock_irqrestore(&pi->port.lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1485 | } |
| 1486 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1487 | static const char *mpsc_type(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1488 | { |
| 1489 | pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); |
| 1490 | return MPSC_DRIVER_NAME; |
| 1491 | } |
| 1492 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1493 | static int mpsc_request_port(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1494 | { |
| 1495 | /* Should make chip/platform specific call */ |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1499 | static void mpsc_release_port(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1500 | { |
| 1501 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1502 | |
| 1503 | if (pi->ready) { |
| 1504 | mpsc_uninit_rings(pi); |
| 1505 | mpsc_free_ring_mem(pi); |
| 1506 | pi->ready = 0; |
| 1507 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1508 | } |
| 1509 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1510 | static void mpsc_config_port(struct uart_port *port, int flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1511 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1512 | } |
| 1513 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1514 | static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1515 | { |
| 1516 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1517 | int rc = 0; |
| 1518 | |
| 1519 | pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); |
| 1520 | |
| 1521 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC) |
| 1522 | rc = -EINVAL; |
| 1523 | else if (pi->port.irq != ser->irq) |
| 1524 | rc = -EINVAL; |
| 1525 | else if (ser->io_type != SERIAL_IO_MEM) |
| 1526 | rc = -EINVAL; |
| 1527 | else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ |
| 1528 | rc = -EINVAL; |
| 1529 | else if ((void *)pi->port.mapbase != ser->iomem_base) |
| 1530 | rc = -EINVAL; |
| 1531 | else if (pi->port.iobase != ser->port) |
| 1532 | rc = -EINVAL; |
| 1533 | else if (ser->hub6 != 0) |
| 1534 | rc = -EINVAL; |
| 1535 | |
| 1536 | return rc; |
| 1537 | } |
Jason Wessel | 3b216c9 | 2008-07-23 11:30:16 -0500 | [diff] [blame] | 1538 | #ifdef CONFIG_CONSOLE_POLL |
| 1539 | /* Serial polling routines for writing and reading from the uart while |
| 1540 | * in an interrupt or debug context. |
| 1541 | */ |
| 1542 | |
| 1543 | static char poll_buf[2048]; |
| 1544 | static int poll_ptr; |
| 1545 | static int poll_cnt; |
| 1546 | static void mpsc_put_poll_char(struct uart_port *port, |
| 1547 | unsigned char c); |
| 1548 | |
| 1549 | static int mpsc_get_poll_char(struct uart_port *port) |
| 1550 | { |
| 1551 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1552 | struct mpsc_rx_desc *rxre; |
| 1553 | u32 cmdstat, bytes_in, i; |
| 1554 | u8 *bp; |
| 1555 | |
| 1556 | if (!serial_polled) |
| 1557 | serial_polled = 1; |
| 1558 | |
| 1559 | pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); |
| 1560 | |
| 1561 | if (poll_cnt) { |
| 1562 | poll_cnt--; |
| 1563 | return poll_buf[poll_ptr++]; |
| 1564 | } |
| 1565 | poll_ptr = 0; |
| 1566 | poll_cnt = 0; |
| 1567 | |
| 1568 | while (poll_cnt == 0) { |
| 1569 | rxre = (struct mpsc_rx_desc *)(pi->rxr + |
| 1570 | (pi->rxr_posn*MPSC_RXRE_SIZE)); |
| 1571 | dma_cache_sync(pi->port.dev, (void *)rxre, |
| 1572 | MPSC_RXRE_SIZE, DMA_FROM_DEVICE); |
| 1573 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1574 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1575 | invalidate_dcache_range((ulong)rxre, |
| 1576 | (ulong)rxre + MPSC_RXRE_SIZE); |
| 1577 | #endif |
| 1578 | /* |
| 1579 | * Loop through Rx descriptors handling ones that have |
| 1580 | * been completed. |
| 1581 | */ |
| 1582 | while (poll_cnt == 0 && |
| 1583 | !((cmdstat = be32_to_cpu(rxre->cmdstat)) & |
| 1584 | SDMA_DESC_CMDSTAT_O)){ |
| 1585 | bytes_in = be16_to_cpu(rxre->bytecnt); |
| 1586 | bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); |
| 1587 | dma_cache_sync(pi->port.dev, (void *) bp, |
| 1588 | MPSC_RXBE_SIZE, DMA_FROM_DEVICE); |
| 1589 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1590 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1591 | invalidate_dcache_range((ulong)bp, |
| 1592 | (ulong)bp + MPSC_RXBE_SIZE); |
| 1593 | #endif |
| 1594 | if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | |
| 1595 | SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && |
| 1596 | !(cmdstat & pi->port.ignore_status_mask)) { |
| 1597 | poll_buf[poll_cnt] = *bp; |
| 1598 | poll_cnt++; |
| 1599 | } else { |
| 1600 | for (i = 0; i < bytes_in; i++) { |
| 1601 | poll_buf[poll_cnt] = *bp++; |
| 1602 | poll_cnt++; |
| 1603 | } |
| 1604 | pi->port.icount.rx += bytes_in; |
| 1605 | } |
| 1606 | rxre->bytecnt = cpu_to_be16(0); |
| 1607 | wmb(); |
| 1608 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | |
| 1609 | SDMA_DESC_CMDSTAT_EI | |
| 1610 | SDMA_DESC_CMDSTAT_F | |
| 1611 | SDMA_DESC_CMDSTAT_L); |
| 1612 | wmb(); |
| 1613 | dma_cache_sync(pi->port.dev, (void *)rxre, |
| 1614 | MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); |
| 1615 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1616 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1617 | flush_dcache_range((ulong)rxre, |
| 1618 | (ulong)rxre + MPSC_RXRE_SIZE); |
| 1619 | #endif |
| 1620 | |
| 1621 | /* Advance to next descriptor */ |
| 1622 | pi->rxr_posn = (pi->rxr_posn + 1) & |
| 1623 | (MPSC_RXR_ENTRIES - 1); |
| 1624 | rxre = (struct mpsc_rx_desc *)(pi->rxr + |
| 1625 | (pi->rxr_posn * MPSC_RXRE_SIZE)); |
| 1626 | dma_cache_sync(pi->port.dev, (void *)rxre, |
| 1627 | MPSC_RXRE_SIZE, DMA_FROM_DEVICE); |
| 1628 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1629 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1630 | invalidate_dcache_range((ulong)rxre, |
| 1631 | (ulong)rxre + MPSC_RXRE_SIZE); |
| 1632 | #endif |
| 1633 | } |
| 1634 | |
| 1635 | /* Restart rx engine, if its stopped */ |
| 1636 | if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) |
| 1637 | mpsc_start_rx(pi); |
| 1638 | } |
| 1639 | if (poll_cnt) { |
| 1640 | poll_cnt--; |
| 1641 | return poll_buf[poll_ptr++]; |
| 1642 | } |
| 1643 | |
| 1644 | return 0; |
| 1645 | } |
| 1646 | |
| 1647 | |
| 1648 | static void mpsc_put_poll_char(struct uart_port *port, |
| 1649 | unsigned char c) |
| 1650 | { |
| 1651 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; |
| 1652 | u32 data; |
| 1653 | |
| 1654 | data = readl(pi->mpsc_base + MPSC_MPCR); |
| 1655 | writeb(c, pi->mpsc_base + MPSC_CHR_1); |
| 1656 | mb(); |
| 1657 | data = readl(pi->mpsc_base + MPSC_CHR_2); |
| 1658 | data |= MPSC_CHR_2_TTCS; |
| 1659 | writel(data, pi->mpsc_base + MPSC_CHR_2); |
| 1660 | mb(); |
| 1661 | |
| 1662 | while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS); |
| 1663 | } |
| 1664 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1665 | |
| 1666 | static struct uart_ops mpsc_pops = { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1667 | .tx_empty = mpsc_tx_empty, |
| 1668 | .set_mctrl = mpsc_set_mctrl, |
| 1669 | .get_mctrl = mpsc_get_mctrl, |
| 1670 | .stop_tx = mpsc_stop_tx, |
| 1671 | .start_tx = mpsc_start_tx, |
| 1672 | .stop_rx = mpsc_stop_rx, |
| 1673 | .enable_ms = mpsc_enable_ms, |
| 1674 | .break_ctl = mpsc_break_ctl, |
| 1675 | .startup = mpsc_startup, |
| 1676 | .shutdown = mpsc_shutdown, |
| 1677 | .set_termios = mpsc_set_termios, |
| 1678 | .type = mpsc_type, |
| 1679 | .release_port = mpsc_release_port, |
| 1680 | .request_port = mpsc_request_port, |
| 1681 | .config_port = mpsc_config_port, |
| 1682 | .verify_port = mpsc_verify_port, |
Jason Wessel | 3b216c9 | 2008-07-23 11:30:16 -0500 | [diff] [blame] | 1683 | #ifdef CONFIG_CONSOLE_POLL |
| 1684 | .poll_get_char = mpsc_get_poll_char, |
| 1685 | .poll_put_char = mpsc_put_poll_char, |
| 1686 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1687 | }; |
| 1688 | |
| 1689 | /* |
| 1690 | ****************************************************************************** |
| 1691 | * |
| 1692 | * Console Interface Routines |
| 1693 | * |
| 1694 | ****************************************************************************** |
| 1695 | */ |
| 1696 | |
| 1697 | #ifdef CONFIG_SERIAL_MPSC_CONSOLE |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1698 | static void mpsc_console_write(struct console *co, const char *s, uint count) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | { |
| 1700 | struct mpsc_port_info *pi = &mpsc_ports[co->index]; |
| 1701 | u8 *bp, *dp, add_cr = 0; |
| 1702 | int i; |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1703 | unsigned long iflags; |
| 1704 | |
| 1705 | spin_lock_irqsave(&pi->tx_lock, iflags); |
| 1706 | |
| 1707 | while (pi->txr_head != pi->txr_tail) { |
| 1708 | while (mpsc_sdma_tx_active(pi)) |
| 1709 | udelay(100); |
| 1710 | mpsc_sdma_intr_ack(pi); |
| 1711 | mpsc_tx_intr(pi); |
| 1712 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | |
| 1714 | while (mpsc_sdma_tx_active(pi)) |
| 1715 | udelay(100); |
| 1716 | |
| 1717 | while (count > 0) { |
| 1718 | bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); |
| 1719 | |
| 1720 | for (i = 0; i < MPSC_TXBE_SIZE; i++) { |
| 1721 | if (count == 0) |
| 1722 | break; |
| 1723 | |
| 1724 | if (add_cr) { |
| 1725 | *(dp++) = '\r'; |
| 1726 | add_cr = 0; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1727 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | *(dp++) = *s; |
| 1729 | |
| 1730 | if (*(s++) == '\n') { /* add '\r' after '\n' */ |
| 1731 | add_cr = 1; |
| 1732 | count++; |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | count--; |
| 1737 | } |
| 1738 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1739 | dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, |
| 1740 | DMA_BIDIRECTIONAL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1741 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) |
| 1742 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ |
| 1743 | flush_dcache_range((ulong)bp, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1744 | (ulong)bp + MPSC_TXBE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1745 | #endif |
| 1746 | mpsc_setup_tx_desc(pi, i, 0); |
| 1747 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); |
| 1748 | mpsc_sdma_start_tx(pi); |
| 1749 | |
| 1750 | while (mpsc_sdma_tx_active(pi)) |
| 1751 | udelay(100); |
| 1752 | |
| 1753 | pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); |
| 1754 | } |
| 1755 | |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 1756 | spin_unlock_irqrestore(&pi->tx_lock, iflags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1757 | } |
| 1758 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1759 | static int __init mpsc_console_setup(struct console *co, char *options) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1760 | { |
| 1761 | struct mpsc_port_info *pi; |
| 1762 | int baud, bits, parity, flow; |
| 1763 | |
| 1764 | pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options); |
| 1765 | |
| 1766 | if (co->index >= MPSC_NUM_CTLRS) |
| 1767 | co->index = 0; |
| 1768 | |
| 1769 | pi = &mpsc_ports[co->index]; |
| 1770 | |
| 1771 | baud = pi->default_baud; |
| 1772 | bits = pi->default_bits; |
| 1773 | parity = pi->default_parity; |
| 1774 | flow = pi->default_flow; |
| 1775 | |
| 1776 | if (!pi->port.ops) |
| 1777 | return -ENODEV; |
| 1778 | |
| 1779 | spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ |
| 1780 | |
| 1781 | if (options) |
| 1782 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 1783 | |
| 1784 | return uart_set_options(&pi->port, co, baud, parity, bits, flow); |
| 1785 | } |
| 1786 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1787 | static struct console mpsc_console = { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1788 | .name = MPSC_DEV_NAME, |
| 1789 | .write = mpsc_console_write, |
| 1790 | .device = uart_console_device, |
| 1791 | .setup = mpsc_console_setup, |
| 1792 | .flags = CON_PRINTBUFFER, |
| 1793 | .index = -1, |
| 1794 | .data = &mpsc_reg, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1795 | }; |
| 1796 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1797 | static int __init mpsc_late_console_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1798 | { |
| 1799 | pr_debug("mpsc_late_console_init: Enter\n"); |
| 1800 | |
| 1801 | if (!(mpsc_console.flags & CON_ENABLED)) |
| 1802 | register_console(&mpsc_console); |
| 1803 | return 0; |
| 1804 | } |
| 1805 | |
| 1806 | late_initcall(mpsc_late_console_init); |
| 1807 | |
| 1808 | #define MPSC_CONSOLE &mpsc_console |
| 1809 | #else |
| 1810 | #define MPSC_CONSOLE NULL |
| 1811 | #endif |
| 1812 | /* |
| 1813 | ****************************************************************************** |
| 1814 | * |
| 1815 | * Dummy Platform Driver to extract & map shared register regions |
| 1816 | * |
| 1817 | ****************************************************************************** |
| 1818 | */ |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1819 | static void mpsc_resource_err(char *s) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1820 | { |
| 1821 | printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1822 | } |
| 1823 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1824 | static int mpsc_shared_map_regs(struct platform_device *pd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1825 | { |
| 1826 | struct resource *r; |
| 1827 | |
| 1828 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1829 | MPSC_ROUTING_BASE_ORDER)) |
| 1830 | && request_mem_region(r->start, |
| 1831 | MPSC_ROUTING_REG_BLOCK_SIZE, |
| 1832 | "mpsc_routing_regs")) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1833 | mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1834 | MPSC_ROUTING_REG_BLOCK_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1835 | mpsc_shared_regs.mpsc_routing_base_p = r->start; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1836 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1837 | mpsc_resource_err("MPSC routing base"); |
| 1838 | return -ENOMEM; |
| 1839 | } |
| 1840 | |
| 1841 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1842 | MPSC_SDMA_INTR_BASE_ORDER)) |
| 1843 | && request_mem_region(r->start, |
| 1844 | MPSC_SDMA_INTR_REG_BLOCK_SIZE, |
| 1845 | "sdma_intr_regs")) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1846 | mpsc_shared_regs.sdma_intr_base = ioremap(r->start, |
| 1847 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); |
| 1848 | mpsc_shared_regs.sdma_intr_base_p = r->start; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1849 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1850 | iounmap(mpsc_shared_regs.mpsc_routing_base); |
| 1851 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1852 | MPSC_ROUTING_REG_BLOCK_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1853 | mpsc_resource_err("SDMA intr base"); |
| 1854 | return -ENOMEM; |
| 1855 | } |
| 1856 | |
| 1857 | return 0; |
| 1858 | } |
| 1859 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1860 | static void mpsc_shared_unmap_regs(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1861 | { |
| 1862 | if (!mpsc_shared_regs.mpsc_routing_base) { |
| 1863 | iounmap(mpsc_shared_regs.mpsc_routing_base); |
| 1864 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1865 | MPSC_ROUTING_REG_BLOCK_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1866 | } |
| 1867 | if (!mpsc_shared_regs.sdma_intr_base) { |
| 1868 | iounmap(mpsc_shared_regs.sdma_intr_base); |
| 1869 | release_mem_region(mpsc_shared_regs.sdma_intr_base_p, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1870 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1871 | } |
| 1872 | |
Al Viro | 2c6e759 | 2005-04-25 18:32:12 -0700 | [diff] [blame] | 1873 | mpsc_shared_regs.mpsc_routing_base = NULL; |
| 1874 | mpsc_shared_regs.sdma_intr_base = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1875 | |
| 1876 | mpsc_shared_regs.mpsc_routing_base_p = 0; |
| 1877 | mpsc_shared_regs.sdma_intr_base_p = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1878 | } |
| 1879 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1880 | static int mpsc_shared_drv_probe(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1881 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1882 | struct mpsc_shared_pdata *pdata; |
| 1883 | int rc = -ENODEV; |
| 1884 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1885 | if (dev->id == 0) { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1886 | if (!(rc = mpsc_shared_map_regs(dev))) { |
| 1887 | pdata = (struct mpsc_shared_pdata *) |
| 1888 | dev->dev.platform_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1889 | |
| 1890 | mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; |
| 1891 | mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; |
| 1892 | mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val; |
| 1893 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = |
| 1894 | pdata->intr_cause_val; |
| 1895 | mpsc_shared_regs.SDMA_INTR_MASK_m = |
| 1896 | pdata->intr_mask_val; |
| 1897 | |
| 1898 | rc = 0; |
| 1899 | } |
| 1900 | } |
| 1901 | |
| 1902 | return rc; |
| 1903 | } |
| 1904 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1905 | static int mpsc_shared_drv_remove(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1906 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | int rc = -ENODEV; |
| 1908 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1909 | if (dev->id == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1910 | mpsc_shared_unmap_regs(); |
| 1911 | mpsc_shared_regs.MPSC_MRR_m = 0; |
| 1912 | mpsc_shared_regs.MPSC_RCRR_m = 0; |
| 1913 | mpsc_shared_regs.MPSC_TCRR_m = 0; |
| 1914 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0; |
| 1915 | mpsc_shared_regs.SDMA_INTR_MASK_m = 0; |
| 1916 | rc = 0; |
| 1917 | } |
| 1918 | |
| 1919 | return rc; |
| 1920 | } |
| 1921 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1922 | static struct platform_driver mpsc_shared_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1923 | .probe = mpsc_shared_drv_probe, |
| 1924 | .remove = mpsc_shared_drv_remove, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1925 | .driver = { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1926 | .name = MPSC_SHARED_NAME, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1927 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1928 | }; |
| 1929 | |
| 1930 | /* |
| 1931 | ****************************************************************************** |
| 1932 | * |
| 1933 | * Driver Interface Routines |
| 1934 | * |
| 1935 | ****************************************************************************** |
| 1936 | */ |
| 1937 | static struct uart_driver mpsc_reg = { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1938 | .owner = THIS_MODULE, |
| 1939 | .driver_name = MPSC_DRIVER_NAME, |
| 1940 | .dev_name = MPSC_DEV_NAME, |
| 1941 | .major = MPSC_MAJOR, |
| 1942 | .minor = MPSC_MINOR_START, |
| 1943 | .nr = MPSC_NUM_CTLRS, |
| 1944 | .cons = MPSC_CONSOLE, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1945 | }; |
| 1946 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1947 | static int mpsc_drv_map_regs(struct mpsc_port_info *pi, |
| 1948 | struct platform_device *pd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1949 | { |
| 1950 | struct resource *r; |
| 1951 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1952 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) |
| 1953 | && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, |
| 1954 | "mpsc_regs")) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1955 | pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); |
| 1956 | pi->mpsc_base_p = r->start; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1957 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1958 | mpsc_resource_err("MPSC base"); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1959 | goto err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1960 | } |
| 1961 | |
| 1962 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1963 | MPSC_SDMA_BASE_ORDER)) |
| 1964 | && request_mem_region(r->start, |
| 1965 | MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1966 | pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); |
| 1967 | pi->sdma_base_p = r->start; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1968 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1969 | mpsc_resource_err("SDMA base"); |
Amol Lad | a141a04 | 2006-09-30 23:29:24 -0700 | [diff] [blame] | 1970 | if (pi->mpsc_base) { |
| 1971 | iounmap(pi->mpsc_base); |
| 1972 | pi->mpsc_base = NULL; |
| 1973 | } |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1974 | goto err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1975 | } |
| 1976 | |
| 1977 | if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1978 | && request_mem_region(r->start, |
| 1979 | MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1980 | pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); |
| 1981 | pi->brg_base_p = r->start; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1982 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1983 | mpsc_resource_err("BRG base"); |
Amol Lad | a141a04 | 2006-09-30 23:29:24 -0700 | [diff] [blame] | 1984 | if (pi->mpsc_base) { |
| 1985 | iounmap(pi->mpsc_base); |
| 1986 | pi->mpsc_base = NULL; |
| 1987 | } |
| 1988 | if (pi->sdma_base) { |
| 1989 | iounmap(pi->sdma_base); |
| 1990 | pi->sdma_base = NULL; |
| 1991 | } |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1992 | goto err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1993 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1994 | return 0; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 1995 | |
| 1996 | err: |
| 1997 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1998 | } |
| 1999 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2000 | static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2001 | { |
| 2002 | if (!pi->mpsc_base) { |
| 2003 | iounmap(pi->mpsc_base); |
| 2004 | release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); |
| 2005 | } |
| 2006 | if (!pi->sdma_base) { |
| 2007 | iounmap(pi->sdma_base); |
| 2008 | release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); |
| 2009 | } |
| 2010 | if (!pi->brg_base) { |
| 2011 | iounmap(pi->brg_base); |
| 2012 | release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); |
| 2013 | } |
| 2014 | |
Al Viro | 2c6e759 | 2005-04-25 18:32:12 -0700 | [diff] [blame] | 2015 | pi->mpsc_base = NULL; |
| 2016 | pi->sdma_base = NULL; |
| 2017 | pi->brg_base = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2018 | |
| 2019 | pi->mpsc_base_p = 0; |
| 2020 | pi->sdma_base_p = 0; |
| 2021 | pi->brg_base_p = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2022 | } |
| 2023 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2024 | static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi, |
| 2025 | struct platform_device *pd, int num) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2026 | { |
| 2027 | struct mpsc_pdata *pdata; |
| 2028 | |
| 2029 | pdata = (struct mpsc_pdata *)pd->dev.platform_data; |
| 2030 | |
| 2031 | pi->port.uartclk = pdata->brg_clk_freq; |
| 2032 | pi->port.iotype = UPIO_MEM; |
| 2033 | pi->port.line = num; |
| 2034 | pi->port.type = PORT_MPSC; |
| 2035 | pi->port.fifosize = MPSC_TXBE_SIZE; |
| 2036 | pi->port.membase = pi->mpsc_base; |
| 2037 | pi->port.mapbase = (ulong)pi->mpsc_base; |
| 2038 | pi->port.ops = &mpsc_pops; |
| 2039 | |
| 2040 | pi->mirror_regs = pdata->mirror_regs; |
| 2041 | pi->cache_mgmt = pdata->cache_mgmt; |
| 2042 | pi->brg_can_tune = pdata->brg_can_tune; |
| 2043 | pi->brg_clk_src = pdata->brg_clk_src; |
| 2044 | pi->mpsc_max_idle = pdata->max_idle; |
| 2045 | pi->default_baud = pdata->default_baud; |
| 2046 | pi->default_bits = pdata->default_bits; |
| 2047 | pi->default_parity = pdata->default_parity; |
| 2048 | pi->default_flow = pdata->default_flow; |
| 2049 | |
| 2050 | /* Initial values of mirrored regs */ |
| 2051 | pi->MPSC_CHR_1_m = pdata->chr_1_val; |
| 2052 | pi->MPSC_CHR_2_m = pdata->chr_2_val; |
| 2053 | pi->MPSC_CHR_10_m = pdata->chr_10_val; |
| 2054 | pi->MPSC_MPCR_m = pdata->mpcr_val; |
| 2055 | pi->BRG_BCR_m = pdata->bcr_val; |
| 2056 | |
| 2057 | pi->shared_regs = &mpsc_shared_regs; |
| 2058 | |
| 2059 | pi->port.irq = platform_get_irq(pd, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2060 | } |
| 2061 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2062 | static int mpsc_drv_probe(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2063 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2064 | struct mpsc_port_info *pi; |
| 2065 | int rc = -ENODEV; |
| 2066 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2067 | pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2068 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2069 | if (dev->id < MPSC_NUM_CTLRS) { |
| 2070 | pi = &mpsc_ports[dev->id]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2071 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2072 | if (!(rc = mpsc_drv_map_regs(pi, dev))) { |
| 2073 | mpsc_drv_get_platform_data(pi, dev, dev->id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2074 | |
Dave Jiang | 1733310 | 2007-05-06 14:48:50 -0700 | [diff] [blame] | 2075 | if (!(rc = mpsc_make_ready(pi))) { |
| 2076 | spin_lock_init(&pi->tx_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2077 | if (!(rc = uart_add_one_port(&mpsc_reg, |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2078 | &pi->port))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2079 | rc = 0; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2080 | } else { |
| 2081 | mpsc_release_port((struct uart_port *) |
| 2082 | pi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2083 | mpsc_drv_unmap_regs(pi); |
| 2084 | } |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2085 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2086 | mpsc_drv_unmap_regs(pi); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2087 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2088 | } |
| 2089 | } |
| 2090 | |
| 2091 | return rc; |
| 2092 | } |
| 2093 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2094 | static int mpsc_drv_remove(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2095 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2096 | pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2097 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2098 | if (dev->id < MPSC_NUM_CTLRS) { |
| 2099 | uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2100 | mpsc_release_port((struct uart_port *) |
| 2101 | &mpsc_ports[dev->id].port); |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2102 | mpsc_drv_unmap_regs(&mpsc_ports[dev->id]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2103 | return 0; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2104 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2105 | return -ENODEV; |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2106 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2107 | } |
| 2108 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2109 | static struct platform_driver mpsc_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2110 | .probe = mpsc_drv_probe, |
| 2111 | .remove = mpsc_drv_remove, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2112 | .driver = { |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2113 | .name = MPSC_CTLR_NAME, |
Kay Sievers | e169c13 | 2008-04-15 14:34:35 -0700 | [diff] [blame] | 2114 | .owner = THIS_MODULE, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2115 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2116 | }; |
| 2117 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2118 | static int __init mpsc_drv_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2119 | { |
| 2120 | int rc; |
| 2121 | |
Adrian Bunk | d87a6d9 | 2008-07-16 21:53:31 +0100 | [diff] [blame] | 2122 | printk(KERN_INFO "Serial: MPSC driver\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2123 | |
| 2124 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); |
| 2125 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); |
| 2126 | |
| 2127 | if (!(rc = uart_register_driver(&mpsc_reg))) { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2128 | if (!(rc = platform_driver_register(&mpsc_shared_driver))) { |
| 2129 | if ((rc = platform_driver_register(&mpsc_driver))) { |
| 2130 | platform_driver_unregister(&mpsc_shared_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2131 | uart_unregister_driver(&mpsc_reg); |
| 2132 | } |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2133 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2134 | uart_unregister_driver(&mpsc_reg); |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2135 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2136 | } |
| 2137 | |
| 2138 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2139 | } |
| 2140 | |
Mark A. Greer | 2e89db7 | 2007-07-31 00:39:01 -0700 | [diff] [blame] | 2141 | static void __exit mpsc_drv_exit(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2142 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 2143 | platform_driver_unregister(&mpsc_driver); |
| 2144 | platform_driver_unregister(&mpsc_shared_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2145 | uart_unregister_driver(&mpsc_reg); |
| 2146 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); |
| 2147 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2148 | } |
| 2149 | |
| 2150 | module_init(mpsc_drv_init); |
| 2151 | module_exit(mpsc_drv_exit); |
| 2152 | |
| 2153 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); |
Adrian Bunk | d87a6d9 | 2008-07-16 21:53:31 +0100 | [diff] [blame] | 2154 | MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2155 | MODULE_VERSION(MPSC_VERSION); |
| 2156 | MODULE_LICENSE("GPL"); |
| 2157 | MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR); |
Kay Sievers | e169c13 | 2008-04-15 14:34:35 -0700 | [diff] [blame] | 2158 | MODULE_ALIAS("platform:" MPSC_CTLR_NAME); |