blob: 152b34da927c1d8117c42d06d90a3adc0d214109 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/*
Dave Airliebc54fd12005-06-23 22:46:46 +10002 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110025 */
Dave Airliebc54fd12005-06-23 22:46:46 +100026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
32 */
33
34#include "drm.h"
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
Dave Airliec60ce622007-07-11 15:27:12 +100067 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
Dave Airliede227f52006-01-25 15:31:43 +110077 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
=?utf-8?q?Michel_D=C3=A4nzer?=376642c2006-10-25 00:09:35 +1000107
Dave Airlieaf6061a2008-05-07 12:15:39 +1000108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116} drm_i915_sarea_t;
117
118/* Flags for perf_boxes
119 */
120#define I915_BOX_RING_EMPTY 0x1
121#define I915_BOX_FLIP 0x2
122#define I915_BOX_WAIT 0x4
123#define I915_BOX_TEXTURE_LOAD 0x8
124#define I915_BOX_LOST_CONTEXT 0x10
125
126/* I915 specific ioctls
127 * The device specific ioctl range is 0x40 to 0x79.
128 */
129#define DRM_I915_INIT 0x00
130#define DRM_I915_FLUSH 0x01
131#define DRM_I915_FLIP 0x02
132#define DRM_I915_BATCHBUFFER 0x03
133#define DRM_I915_IRQ_EMIT 0x04
134#define DRM_I915_IRQ_WAIT 0x05
135#define DRM_I915_GETPARAM 0x06
136#define DRM_I915_SETPARAM 0x07
137#define DRM_I915_ALLOC 0x08
138#define DRM_I915_FREE 0x09
139#define DRM_I915_INIT_HEAP 0x0a
140#define DRM_I915_CMDBUFFER 0x0b
Dave Airliede227f52006-01-25 15:31:43 +1100141#define DRM_I915_DESTROY_HEAP 0x0c
Dave Airlie702880f2006-06-24 17:07:34 +1000142#define DRM_I915_SET_VBLANK_PIPE 0x0d
143#define DRM_I915_GET_VBLANK_PIPE 0x0e
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000144#define DRM_I915_VBLANK_SWAP 0x0f
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000145#define DRM_I915_HWS_ADDR 0x11
Eric Anholt673a3942008-07-30 12:06:12 -0700146#define DRM_I915_GEM_INIT 0x13
147#define DRM_I915_GEM_EXECBUFFER 0x14
148#define DRM_I915_GEM_PIN 0x15
149#define DRM_I915_GEM_UNPIN 0x16
150#define DRM_I915_GEM_BUSY 0x17
151#define DRM_I915_GEM_THROTTLE 0x18
152#define DRM_I915_GEM_ENTERVT 0x19
153#define DRM_I915_GEM_LEAVEVT 0x1a
154#define DRM_I915_GEM_CREATE 0x1b
155#define DRM_I915_GEM_PREAD 0x1c
156#define DRM_I915_GEM_PWRITE 0x1d
157#define DRM_I915_GEM_MMAP 0x1e
158#define DRM_I915_GEM_SET_DOMAIN 0x1f
159#define DRM_I915_GEM_SW_FINISH 0x20
160#define DRM_I915_GEM_SET_TILING 0x21
161#define DRM_I915_GEM_GET_TILING 0x22
Eric Anholt5a125c32008-10-22 21:40:13 -0700162#define DRM_I915_GEM_GET_APERTURE 0x23
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
165#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
Dave Airlieaf6061a2008-05-07 12:15:39 +1000166#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
168#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
169#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
170#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
171#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
172#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
173#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
174#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
175#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
Dave Airliede227f52006-01-25 15:31:43 +1100176#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
Dave Airlie702880f2006-06-24 17:07:34 +1000177#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
178#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
=?utf-8?q?Michel_D=C3=A4nzer?=541f29a2006-10-24 23:38:54 +1000179#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
Eric Anholt673a3942008-07-30 12:06:12 -0700180#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
181#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
182#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
183#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
184#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
185#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
186#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
187#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
188#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
189#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
190#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
191#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
192#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
193#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
Eric Anholt5a125c32008-10-22 21:40:13 -0700194#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195
196/* Allow drivers to submit batchbuffers directly to hardware, relying
197 * on the security mechanisms provided by hardware.
198 */
199typedef struct _drm_i915_batchbuffer {
200 int start; /* agp offset */
201 int used; /* nr bytes in use */
202 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
203 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
204 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000205 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206} drm_i915_batchbuffer_t;
207
208/* As above, but pass a pointer to userspace buffer which can be
209 * validated by the kernel prior to sending to hardware.
210 */
211typedef struct _drm_i915_cmdbuffer {
212 char __user *buf; /* pointer to userspace command buffer */
213 int sz; /* nr bytes in buf */
214 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
215 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
216 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000217 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218} drm_i915_cmdbuffer_t;
219
220/* Userspace can request & wait on irq's:
221 */
222typedef struct drm_i915_irq_emit {
223 int __user *irq_seq;
224} drm_i915_irq_emit_t;
225
226typedef struct drm_i915_irq_wait {
227 int irq_seq;
228} drm_i915_irq_wait_t;
229
230/* Ioctl to query kernel params:
231 */
232#define I915_PARAM_IRQ_ACTIVE 1
233#define I915_PARAM_ALLOW_BATCHBUFFER 2
Dave Airlie0d6aa602006-01-02 20:14:23 +1100234#define I915_PARAM_LAST_DISPATCH 3
Kristian Høgsberged4c9c42008-08-20 11:08:52 -0400235#define I915_PARAM_CHIPSET_ID 4
Eric Anholt673a3942008-07-30 12:06:12 -0700236#define I915_PARAM_HAS_GEM 5
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
238typedef struct drm_i915_getparam {
239 int param;
240 int __user *value;
241} drm_i915_getparam_t;
242
243/* Ioctl to set kernel params:
244 */
245#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
246#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
247#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
248
249typedef struct drm_i915_setparam {
250 int param;
251 int value;
252} drm_i915_setparam_t;
253
254/* A memory manager for regions of shared memory:
255 */
256#define I915_MEM_REGION_AGP 1
257
258typedef struct drm_i915_mem_alloc {
259 int region;
260 int alignment;
261 int size;
262 int __user *region_offset; /* offset from start of fb or agp */
263} drm_i915_mem_alloc_t;
264
265typedef struct drm_i915_mem_free {
266 int region;
267 int region_offset;
268} drm_i915_mem_free_t;
269
270typedef struct drm_i915_mem_init_heap {
271 int region;
272 int size;
273 int start;
274} drm_i915_mem_init_heap_t;
275
Dave Airliede227f52006-01-25 15:31:43 +1100276/* Allow memory manager to be torn down and re-initialized (eg on
277 * rotate):
278 */
279typedef struct drm_i915_mem_destroy_heap {
280 int region;
281} drm_i915_mem_destroy_heap_t;
282
Dave Airlie702880f2006-06-24 17:07:34 +1000283/* Allow X server to configure which pipes to monitor for vblank signals
284 */
285#define DRM_I915_VBLANK_PIPE_A 1
286#define DRM_I915_VBLANK_PIPE_B 2
287
288typedef struct drm_i915_vblank_pipe {
289 int pipe;
290} drm_i915_vblank_pipe_t;
291
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000292/* Schedule buffer swap at given vertical blank:
293 */
294typedef struct drm_i915_vblank_swap {
295 drm_drawable_t drawable;
Dave Airliec60ce622007-07-11 15:27:12 +1000296 enum drm_vblank_seq_type seqtype;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000297 unsigned int sequence;
298} drm_i915_vblank_swap_t;
299
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000300typedef struct drm_i915_hws_addr {
301 uint64_t addr;
302} drm_i915_hws_addr_t;
303
Eric Anholt673a3942008-07-30 12:06:12 -0700304struct drm_i915_gem_init {
305 /**
306 * Beginning offset in the GTT to be managed by the DRM memory
307 * manager.
308 */
309 uint64_t gtt_start;
310 /**
311 * Ending offset in the GTT to be managed by the DRM memory
312 * manager.
313 */
314 uint64_t gtt_end;
315};
316
317struct drm_i915_gem_create {
318 /**
319 * Requested size for the object.
320 *
321 * The (page-aligned) allocated size for the object will be returned.
322 */
323 uint64_t size;
324 /**
325 * Returned handle for the object.
326 *
327 * Object handles are nonzero.
328 */
329 uint32_t handle;
330 uint32_t pad;
331};
332
333struct drm_i915_gem_pread {
334 /** Handle for the object being read. */
335 uint32_t handle;
336 uint32_t pad;
337 /** Offset into the object to read from */
338 uint64_t offset;
339 /** Length of data to read */
340 uint64_t size;
341 /**
342 * Pointer to write the data into.
343 *
344 * This is a fixed-size type for 32/64 compatibility.
345 */
346 uint64_t data_ptr;
347};
348
349struct drm_i915_gem_pwrite {
350 /** Handle for the object being written to. */
351 uint32_t handle;
352 uint32_t pad;
353 /** Offset into the object to write to */
354 uint64_t offset;
355 /** Length of data to write */
356 uint64_t size;
357 /**
358 * Pointer to read the data from.
359 *
360 * This is a fixed-size type for 32/64 compatibility.
361 */
362 uint64_t data_ptr;
363};
364
365struct drm_i915_gem_mmap {
366 /** Handle for the object being mapped. */
367 uint32_t handle;
368 uint32_t pad;
369 /** Offset in the object to map. */
370 uint64_t offset;
371 /**
372 * Length of data to map.
373 *
374 * The value will be page-aligned.
375 */
376 uint64_t size;
377 /**
378 * Returned pointer the data was mapped at.
379 *
380 * This is a fixed-size type for 32/64 compatibility.
381 */
382 uint64_t addr_ptr;
383};
384
385struct drm_i915_gem_set_domain {
386 /** Handle for the object */
387 uint32_t handle;
388
389 /** New read domains */
390 uint32_t read_domains;
391
392 /** New write domain */
393 uint32_t write_domain;
394};
395
396struct drm_i915_gem_sw_finish {
397 /** Handle for the object */
398 uint32_t handle;
399};
400
401struct drm_i915_gem_relocation_entry {
402 /**
403 * Handle of the buffer being pointed to by this relocation entry.
404 *
405 * It's appealing to make this be an index into the mm_validate_entry
406 * list to refer to the buffer, but this allows the driver to create
407 * a relocation list for state buffers and not re-write it per
408 * exec using the buffer.
409 */
410 uint32_t target_handle;
411
412 /**
413 * Value to be added to the offset of the target buffer to make up
414 * the relocation entry.
415 */
416 uint32_t delta;
417
418 /** Offset in the buffer the relocation entry will be written into */
419 uint64_t offset;
420
421 /**
422 * Offset value of the target buffer that the relocation entry was last
423 * written as.
424 *
425 * If the buffer has the same offset as last time, we can skip syncing
426 * and writing the relocation. This value is written back out by
427 * the execbuffer ioctl when the relocation is written.
428 */
429 uint64_t presumed_offset;
430
431 /**
432 * Target memory domains read by this operation.
433 */
434 uint32_t read_domains;
435
436 /**
437 * Target memory domains written by this operation.
438 *
439 * Note that only one domain may be written by the whole
440 * execbuffer operation, so that where there are conflicts,
441 * the application will get -EINVAL back.
442 */
443 uint32_t write_domain;
444};
445
446/** @{
447 * Intel memory domains
448 *
449 * Most of these just align with the various caches in
450 * the system and are used to flush and invalidate as
451 * objects end up cached in different domains.
452 */
453/** CPU cache */
454#define I915_GEM_DOMAIN_CPU 0x00000001
455/** Render cache, used by 2D and 3D drawing */
456#define I915_GEM_DOMAIN_RENDER 0x00000002
457/** Sampler cache, used by texture engine */
458#define I915_GEM_DOMAIN_SAMPLER 0x00000004
459/** Command queue, used to load batch buffers */
460#define I915_GEM_DOMAIN_COMMAND 0x00000008
461/** Instruction cache, used by shader programs */
462#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
463/** Vertex address cache */
464#define I915_GEM_DOMAIN_VERTEX 0x00000020
465/** GTT domain - aperture and scanout */
466#define I915_GEM_DOMAIN_GTT 0x00000040
467/** @} */
468
469struct drm_i915_gem_exec_object {
470 /**
471 * User's handle for a buffer to be bound into the GTT for this
472 * operation.
473 */
474 uint32_t handle;
475
476 /** Number of relocations to be performed on this buffer */
477 uint32_t relocation_count;
478 /**
479 * Pointer to array of struct drm_i915_gem_relocation_entry containing
480 * the relocations to be performed in this buffer.
481 */
482 uint64_t relocs_ptr;
483
484 /** Required alignment in graphics aperture */
485 uint64_t alignment;
486
487 /**
488 * Returned value of the updated offset of the object, for future
489 * presumed_offset writes.
490 */
491 uint64_t offset;
492};
493
494struct drm_i915_gem_execbuffer {
495 /**
496 * List of buffers to be validated with their relocations to be
497 * performend on them.
498 *
499 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
500 *
501 * These buffers must be listed in an order such that all relocations
502 * a buffer is performing refer to buffers that have already appeared
503 * in the validate list.
504 */
505 uint64_t buffers_ptr;
506 uint32_t buffer_count;
507
508 /** Offset in the batchbuffer to start execution from. */
509 uint32_t batch_start_offset;
510 /** Bytes used in batchbuffer from batch_start_offset */
511 uint32_t batch_len;
512 uint32_t DR1;
513 uint32_t DR4;
514 uint32_t num_cliprects;
515 /** This is a struct drm_clip_rect *cliprects */
516 uint64_t cliprects_ptr;
517};
518
519struct drm_i915_gem_pin {
520 /** Handle of the buffer to be pinned. */
521 uint32_t handle;
522 uint32_t pad;
523
524 /** alignment required within the aperture */
525 uint64_t alignment;
526
527 /** Returned GTT offset of the buffer. */
528 uint64_t offset;
529};
530
531struct drm_i915_gem_unpin {
532 /** Handle of the buffer to be unpinned. */
533 uint32_t handle;
534 uint32_t pad;
535};
536
537struct drm_i915_gem_busy {
538 /** Handle of the buffer to check for busy */
539 uint32_t handle;
540
541 /** Return busy status (1 if busy, 0 if idle) */
542 uint32_t busy;
543};
544
545#define I915_TILING_NONE 0
546#define I915_TILING_X 1
547#define I915_TILING_Y 2
548
549#define I915_BIT_6_SWIZZLE_NONE 0
550#define I915_BIT_6_SWIZZLE_9 1
551#define I915_BIT_6_SWIZZLE_9_10 2
552#define I915_BIT_6_SWIZZLE_9_11 3
553#define I915_BIT_6_SWIZZLE_9_10_11 4
554/* Not seen by userland */
555#define I915_BIT_6_SWIZZLE_UNKNOWN 5
556
557struct drm_i915_gem_set_tiling {
558 /** Handle of the buffer to have its tiling state updated */
559 uint32_t handle;
560
561 /**
562 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
563 * I915_TILING_Y).
564 *
565 * This value is to be set on request, and will be updated by the
566 * kernel on successful return with the actual chosen tiling layout.
567 *
568 * The tiling mode may be demoted to I915_TILING_NONE when the system
569 * has bit 6 swizzling that can't be managed correctly by GEM.
570 *
571 * Buffer contents become undefined when changing tiling_mode.
572 */
573 uint32_t tiling_mode;
574
575 /**
576 * Stride in bytes for the object when in I915_TILING_X or
577 * I915_TILING_Y.
578 */
579 uint32_t stride;
580
581 /**
582 * Returned address bit 6 swizzling required for CPU access through
583 * mmap mapping.
584 */
585 uint32_t swizzle_mode;
586};
587
588struct drm_i915_gem_get_tiling {
589 /** Handle of the buffer to get tiling state for. */
590 uint32_t handle;
591
592 /**
593 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
594 * I915_TILING_Y).
595 */
596 uint32_t tiling_mode;
597
598 /**
599 * Returned address bit 6 swizzling required for CPU access through
600 * mmap mapping.
601 */
602 uint32_t swizzle_mode;
603};
604
Eric Anholt5a125c32008-10-22 21:40:13 -0700605struct drm_i915_gem_get_aperture {
606 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
607 uint64_t aper_size;
608
609 /**
610 * Available space in the aperture used by i915_gem_execbuffer, in
611 * bytes
612 */
613 uint64_t aper_available_size;
614};
615
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616#endif /* _I915_DRM_H_ */