blob: 08fb878ef063a7456131743d609789e1f1ead81f [file] [log] [blame]
Magnus Damm6d9598e2010-11-17 10:59:31 +00001/*
2 * sh73a0 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
Paul Mundt6ef9f6f2011-01-07 11:49:49 +090023#include <linux/clkdev.h>
Magnus Damm6d9598e2010-11-17 10:59:31 +000024#include <mach/common.h>
Magnus Damm6d9598e2010-11-17 10:59:31 +000025
Magnus Dammf6d84f42010-12-03 07:22:31 +000026#define FRQCRA 0xe6150000
27#define FRQCRB 0xe6150004
28#define FRQCRD 0xe61500e4
29#define VCLKCR1 0xe6150008
30#define VCLKCR2 0xe615000C
31#define VCLKCR3 0xe615001C
32#define ZBCKCR 0xe6150010
33#define FLCKCR 0xe6150014
34#define SD0CKCR 0xe6150074
35#define SD1CKCR 0xe6150078
36#define SD2CKCR 0xe615007C
37#define FSIACKCR 0xe6150018
38#define FSIBCKCR 0xe6150090
39#define SUBCKCR 0xe6150080
40#define SPUACKCR 0xe6150084
41#define SPUVCKCR 0xe6150094
42#define MSUCKCR 0xe6150088
43#define HSICKCR 0xe615008C
44#define MFCK1CR 0xe6150098
45#define MFCK2CR 0xe615009C
46#define DSITCKCR 0xe6150060
47#define DSI0PCKCR 0xe6150064
48#define DSI1PCKCR 0xe6150068
49#define DSI0PHYCR 0xe615006C
50#define DSI1PHYCR 0xe6150070
51#define PLLECR 0xe61500d0
52#define PLL0CR 0xe61500d8
53#define PLL1CR 0xe6150028
54#define PLL2CR 0xe615002c
55#define PLL3CR 0xe61500dc
Magnus Damm6d9598e2010-11-17 10:59:31 +000056#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61#define SMSTPCR5 0xe6150144
Magnus Dammf6d84f42010-12-03 07:22:31 +000062#define CKSCR 0xe61500c0
Magnus Damm6d9598e2010-11-17 10:59:31 +000063
64/* Fixed 32 KHz root clock from EXTALR pin */
65static struct clk r_clk = {
66 .rate = 32768,
67};
68
Magnus Dammf6d84f42010-12-03 07:22:31 +000069/*
70 * 26MHz default rate for the EXTAL1 root input clock.
71 * If needed, reset this with clk_set_rate() from the platform code.
72 */
73struct clk sh73a0_extal1_clk = {
74 .rate = 26000000,
Magnus Damm6d9598e2010-11-17 10:59:31 +000075};
76
Magnus Dammf6d84f42010-12-03 07:22:31 +000077/*
78 * 48MHz default rate for the EXTAL2 root input clock.
79 * If needed, reset this with clk_set_rate() from the platform code.
80 */
81struct clk sh73a0_extal2_clk = {
82 .rate = 48000000,
83};
84
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95/* Divide extal1 by two */
96static struct clk extal1_div2_clk = {
97 .ops = &div2_clk_ops,
98 .parent = &sh73a0_extal1_clk,
99};
100
101/* Divide extal2 by two */
102static struct clk extal2_div2_clk = {
103 .ops = &div2_clk_ops,
104 .parent = &sh73a0_extal2_clk,
105};
106
107static struct clk_ops main_clk_ops = {
108 .recalc = followparent_recalc,
109};
110
111/* Main clock */
112static struct clk main_clk = {
113 .ops = &main_clk_ops,
114};
115
116/* PLL0, PLL1, PLL2, PLL3 */
117static unsigned long pll_recalc(struct clk *clk)
118{
119 unsigned long mult = 1;
120
121 if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
122 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
123
124 return clk->parent->rate * mult;
125}
126
127static struct clk_ops pll_clk_ops = {
128 .recalc = pll_recalc,
129};
130
131static struct clk pll0_clk = {
132 .ops = &pll_clk_ops,
133 .flags = CLK_ENABLE_ON_INIT,
134 .parent = &main_clk,
135 .enable_reg = (void __iomem *)PLL0CR,
136 .enable_bit = 0,
137};
138
139static struct clk pll1_clk = {
140 .ops = &pll_clk_ops,
141 .flags = CLK_ENABLE_ON_INIT,
142 .parent = &main_clk,
143 .enable_reg = (void __iomem *)PLL1CR,
144 .enable_bit = 1,
145};
146
147static struct clk pll2_clk = {
148 .ops = &pll_clk_ops,
149 .flags = CLK_ENABLE_ON_INIT,
150 .parent = &main_clk,
151 .enable_reg = (void __iomem *)PLL2CR,
152 .enable_bit = 2,
153};
154
155static struct clk pll3_clk = {
156 .ops = &pll_clk_ops,
157 .flags = CLK_ENABLE_ON_INIT,
158 .parent = &main_clk,
159 .enable_reg = (void __iomem *)PLL3CR,
160 .enable_bit = 3,
161};
162
163/* Divide PLL1 by two */
164static struct clk pll1_div2_clk = {
165 .ops = &div2_clk_ops,
166 .parent = &pll1_clk,
Yoshii Takashib028f942010-11-19 13:20:45 +0000167};
168
Magnus Damm6d9598e2010-11-17 10:59:31 +0000169static struct clk *main_clks[] = {
170 &r_clk,
Magnus Dammf6d84f42010-12-03 07:22:31 +0000171 &sh73a0_extal1_clk,
172 &sh73a0_extal2_clk,
173 &extal1_div2_clk,
174 &extal2_div2_clk,
175 &main_clk,
176 &pll0_clk,
177 &pll1_clk,
178 &pll2_clk,
179 &pll3_clk,
180 &pll1_div2_clk,
Magnus Damm6d9598e2010-11-17 10:59:31 +0000181};
182
Magnus Dammf6d84f42010-12-03 07:22:31 +0000183static void div4_kick(struct clk *clk)
184{
185 unsigned long value;
186
187 /* set KICK bit in FRQCRB to update hardware setting */
188 value = __raw_readl(FRQCRB);
189 value |= (1 << 31);
190 __raw_writel(value, FRQCRB);
191}
192
193static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
Takashi YOSHIIc070c202010-12-22 14:15:08 +0000194 24, 0, 36, 48, 7 };
Magnus Dammf6d84f42010-12-03 07:22:31 +0000195
196static struct clk_div_mult_table div4_div_mult_table = {
197 .divisors = divisors,
198 .nr_divisors = ARRAY_SIZE(divisors),
199};
200
201static struct clk_div4_table div4_table = {
202 .div_mult_table = &div4_div_mult_table,
203 .kick = div4_kick,
204};
205
206enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
207 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
208
209#define DIV4(_reg, _bit, _mask, _flags) \
210 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
211
212static struct clk div4_clks[DIV4_NR] = {
213 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
214 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
Magnus Dammdcdb3182011-01-18 08:53:06 +0000215 [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
Magnus Dammf6d84f42010-12-03 07:22:31 +0000216 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
217 [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
218 [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
219 [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
220 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
221 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
222 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
223 [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
224};
225
226enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
227 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
228 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
229 DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
230 DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
231 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
232 DIV6_NR };
233
234static struct clk div6_clks[DIV6_NR] = {
235 [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
236 [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
237 [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
238 [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
239 [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
240 [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
241 [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
242 [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
243 [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
244 [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
245 [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
246 [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
247 [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
248 [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
249 [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
250 [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
251 [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
252 [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
253 [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
254 [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
255};
256
257enum { MSTP001,
Magnus Damm5010f3d2010-12-21 08:40:59 +0000258 MSTP125, MSTP116,
Magnus Dammf6d84f42010-12-03 07:22:31 +0000259 MSTP219,
260 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
Kuninori Morimotoa33bb8a2011-01-14 11:00:41 +0000261 MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
Kuninori Morimoto696d6e12010-11-24 07:41:14 +0000262 MSTP411, MSTP410, MSTP403,
Magnus Damm6d9598e2010-11-17 10:59:31 +0000263 MSTP_NR };
264
265#define MSTP(_parent, _reg, _bit, _flags) \
266 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
267
268static struct clk mstp_clks[MSTP_NR] = {
Magnus Dammf6d84f42010-12-03 07:22:31 +0000269 [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
Magnus Damm5010f3d2010-12-21 08:40:59 +0000270 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
Magnus Dammf6d84f42010-12-03 07:22:31 +0000271 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
272 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
273 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
274 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
275 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
276 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
277 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
278 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
279 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
280 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
Magnus Damm6d9598e2010-11-17 10:59:31 +0000281 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
Magnus Damm5a1b70a2011-01-18 08:48:17 +0000282 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
Magnus Dammf6d84f42010-12-03 07:22:31 +0000283 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
Takashi YOSHII6bf45a102010-12-22 06:35:30 +0000284 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
Magnus Dammf6d84f42010-12-03 07:22:31 +0000285 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
286 [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
Magnus Damm019c4ae2010-12-22 06:14:05 +0000287 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
Magnus Damm6d9598e2010-11-17 10:59:31 +0000288};
289
Magnus Dammf6d84f42010-12-03 07:22:31 +0000290#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
Magnus Damm6d9598e2010-11-17 10:59:31 +0000291#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
292
293static struct clk_lookup lookups[] = {
Magnus Dammf6d84f42010-12-03 07:22:31 +0000294 /* main clocks */
295 CLKDEV_CON_ID("r_clk", &r_clk),
296
Magnus Damm6d9598e2010-11-17 10:59:31 +0000297 /* MSTP32 clocks */
Kuninori Morimoto696d6e12010-11-24 07:41:14 +0000298 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
Magnus Damm5010f3d2010-12-21 08:40:59 +0000299 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
300 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
Kuninori Morimoto696d6e12010-11-24 07:41:14 +0000301 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
Magnus Damm6d9598e2010-11-17 10:59:31 +0000302 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
303 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
304 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
305 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
306 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
307 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
308 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
309 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
310 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
311 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
Kuninori Morimotoa33bb8a2011-01-14 11:00:41 +0000312 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
Yoshii Takashib028f942010-11-19 13:20:45 +0000313 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
Takashi YOSHII6bf45a102010-12-22 06:35:30 +0000314 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
Yoshii Takashib028f942010-11-19 13:20:45 +0000315 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
316 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
Magnus Damm019c4ae2010-12-22 06:14:05 +0000317 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
Magnus Damm6d9598e2010-11-17 10:59:31 +0000318};
319
320void __init sh73a0_clock_init(void)
321{
322 int k, ret = 0;
323
Magnus Dammf6d84f42010-12-03 07:22:31 +0000324 /* detect main clock parent */
325 switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
326 case 0:
327 main_clk.parent = &sh73a0_extal1_clk;
328 break;
329 case 1:
330 main_clk.parent = &extal1_div2_clk;
331 break;
332 case 2:
333 main_clk.parent = &sh73a0_extal2_clk;
334 break;
335 case 3:
336 main_clk.parent = &extal2_div2_clk;
337 break;
338 }
339
Magnus Damm6d9598e2010-11-17 10:59:31 +0000340 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
341 ret = clk_register(main_clks[k]);
342
343 if (!ret)
Magnus Dammf6d84f42010-12-03 07:22:31 +0000344 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
345
346 if (!ret)
347 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
348
349 if (!ret)
Magnus Damm6d9598e2010-11-17 10:59:31 +0000350 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
351
352 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
353
354 if (!ret)
355 clk_init();
356 else
357 panic("failed to setup sh73a0 clocks\n");
358}