Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame^] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include "hw.h" |
| 18 | #include "ar5008_initvals.h" |
| 19 | #include "ar9001_initvals.h" |
| 20 | #include "ar9002_initvals.h" |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 21 | #include "ar9002_phy.h" |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 22 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 23 | int modparam_force_new_ani; |
| 24 | module_param_named(force_new_ani, modparam_force_new_ani, int, 0444); |
John W. Linville | 33af881 | 2011-01-05 14:05:00 -0500 | [diff] [blame] | 25 | MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002"); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 26 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 27 | /* General hardware code for the A5008/AR9001/AR9002 hadware families */ |
| 28 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 29 | static void ar9002_hw_init_mode_regs(struct ath_hw *ah) |
| 30 | { |
| 31 | if (AR_SREV_9271(ah)) { |
| 32 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
| 33 | ARRAY_SIZE(ar9271Modes_9271), 6); |
| 34 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
| 35 | ARRAY_SIZE(ar9271Common_9271), 2); |
| 36 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
| 37 | ar9271Common_normal_cck_fir_coeff_9271, |
| 38 | ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); |
| 39 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, |
| 40 | ar9271Common_japan_2484_cck_fir_coeff_9271, |
| 41 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); |
| 42 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
| 43 | ar9271Modes_9271_1_0_only, |
| 44 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); |
| 45 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
| 46 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); |
| 47 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, |
| 48 | ar9271Modes_high_power_tx_gain_9271, |
| 49 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); |
| 50 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, |
| 51 | ar9271Modes_normal_power_tx_gain_9271, |
| 52 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); |
| 53 | return; |
| 54 | } |
| 55 | |
| 56 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 57 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
| 58 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); |
| 59 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
| 60 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
| 61 | if (ah->config.pcie_clock_req) |
| 62 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 63 | ar9287PciePhy_clkreq_off_L1_9287_1_1, |
| 64 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); |
| 65 | else |
| 66 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 67 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, |
| 68 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), |
| 69 | 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 70 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
| 71 | |
| 72 | |
| 73 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
| 74 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
| 75 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
| 76 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
| 77 | |
| 78 | if (ah->config.pcie_clock_req) { |
| 79 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 80 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
| 81 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); |
| 82 | } else { |
| 83 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 84 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
| 85 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), |
| 86 | 2); |
| 87 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 88 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 89 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
| 90 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
| 91 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
| 92 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
| 93 | |
| 94 | if (ah->config.pcie_clock_req) { |
| 95 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 96 | ar9280PciePhy_clkreq_off_L1_9280, |
| 97 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); |
| 98 | } else { |
| 99 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 100 | ar9280PciePhy_clkreq_always_on_L1_9280, |
| 101 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); |
| 102 | } |
| 103 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 104 | ar9280Modes_fast_clock_9280_2, |
| 105 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 106 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 107 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
| 108 | ARRAY_SIZE(ar5416Modes_9160), 6); |
| 109 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
| 110 | ARRAY_SIZE(ar5416Common_9160), 2); |
| 111 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
| 112 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
| 113 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
| 114 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
| 115 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
| 116 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
| 117 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
| 118 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
| 119 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
| 120 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
| 121 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
| 122 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
| 123 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
| 124 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
| 125 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
| 126 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
| 127 | if (AR_SREV_9160_11(ah)) { |
| 128 | INIT_INI_ARRAY(&ah->iniAddac, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 129 | ar5416Addac_9160_1_1, |
| 130 | ARRAY_SIZE(ar5416Addac_9160_1_1), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 131 | } else { |
| 132 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
| 133 | ARRAY_SIZE(ar5416Addac_9160), 2); |
| 134 | } |
| 135 | } else if (AR_SREV_9100_OR_LATER(ah)) { |
| 136 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
| 137 | ARRAY_SIZE(ar5416Modes_9100), 6); |
| 138 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
| 139 | ARRAY_SIZE(ar5416Common_9100), 2); |
| 140 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
| 141 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
| 142 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
| 143 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
| 144 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
| 145 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
| 146 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
| 147 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
| 148 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
| 149 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
| 150 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
| 151 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
| 152 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
| 153 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
| 154 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
| 155 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
| 156 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
| 157 | ARRAY_SIZE(ar5416Addac_9100), 2); |
| 158 | } else { |
| 159 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
| 160 | ARRAY_SIZE(ar5416Modes), 6); |
| 161 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
| 162 | ARRAY_SIZE(ar5416Common), 2); |
| 163 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
| 164 | ARRAY_SIZE(ar5416Bank0), 2); |
| 165 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
| 166 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
| 167 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
| 168 | ARRAY_SIZE(ar5416Bank1), 2); |
| 169 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
| 170 | ARRAY_SIZE(ar5416Bank2), 2); |
| 171 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
| 172 | ARRAY_SIZE(ar5416Bank3), 3); |
| 173 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
| 174 | ARRAY_SIZE(ar5416Bank6), 3); |
| 175 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
| 176 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
| 177 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
| 178 | ARRAY_SIZE(ar5416Bank7), 2); |
| 179 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
| 180 | ARRAY_SIZE(ar5416Addac), 2); |
| 181 | } |
| 182 | } |
| 183 | |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 184 | /* Support for Japan ch.14 (2484) spread */ |
| 185 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah) |
| 186 | { |
| 187 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 188 | INIT_INI_ARRAY(&ah->iniCckfirNormal, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 189 | ar9287Common_normal_cck_fir_coeff_9287_1_1, |
| 190 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1), |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 191 | 2); |
| 192 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 193 | ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, |
| 194 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1), |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 195 | 2); |
| 196 | } |
| 197 | } |
| 198 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 199 | static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) |
| 200 | { |
| 201 | u32 rxgain_type; |
| 202 | |
| 203 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= |
| 204 | AR5416_EEP_MINOR_VER_17) { |
| 205 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); |
| 206 | |
| 207 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
| 208 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 209 | ar9280Modes_backoff_13db_rxgain_9280_2, |
| 210 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); |
| 211 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
| 212 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 213 | ar9280Modes_backoff_23db_rxgain_9280_2, |
| 214 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); |
| 215 | else |
| 216 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 217 | ar9280Modes_original_rxgain_9280_2, |
| 218 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
| 219 | } else { |
| 220 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 221 | ar9280Modes_original_rxgain_9280_2, |
| 222 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah) |
| 227 | { |
| 228 | u32 txgain_type; |
| 229 | |
| 230 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= |
| 231 | AR5416_EEP_MINOR_VER_19) { |
| 232 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
| 233 | |
| 234 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
| 235 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 236 | ar9280Modes_high_power_tx_gain_9280_2, |
| 237 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); |
| 238 | else |
| 239 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 240 | ar9280Modes_original_tx_gain_9280_2, |
| 241 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
| 242 | } else { |
| 243 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 244 | ar9280Modes_original_tx_gain_9280_2, |
| 245 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 250 | { |
| 251 | if (AR_SREV_9287_11_OR_LATER(ah)) |
| 252 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 253 | ar9287Modes_rx_gain_9287_1_1, |
| 254 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 255 | else if (AR_SREV_9280_20(ah)) |
| 256 | ar9280_20_hw_init_rxgain_ini(ah); |
| 257 | |
| 258 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 259 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 260 | ar9287Modes_tx_gain_9287_1_1, |
| 261 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 262 | } else if (AR_SREV_9280_20(ah)) { |
| 263 | ar9280_20_hw_init_txgain_ini(ah); |
| 264 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
| 265 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
| 266 | |
| 267 | /* txgain table */ |
| 268 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { |
| 269 | if (AR_SREV_9285E_20(ah)) { |
| 270 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 271 | ar9285Modes_XE2_0_high_power, |
| 272 | ARRAY_SIZE( |
| 273 | ar9285Modes_XE2_0_high_power), 6); |
| 274 | } else { |
| 275 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 276 | ar9285Modes_high_power_tx_gain_9285_1_2, |
| 277 | ARRAY_SIZE( |
| 278 | ar9285Modes_high_power_tx_gain_9285_1_2), 6); |
| 279 | } |
| 280 | } else { |
| 281 | if (AR_SREV_9285E_20(ah)) { |
| 282 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 283 | ar9285Modes_XE2_0_normal_power, |
| 284 | ARRAY_SIZE( |
| 285 | ar9285Modes_XE2_0_normal_power), 6); |
| 286 | } else { |
| 287 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 288 | ar9285Modes_original_tx_gain_9285_1_2, |
| 289 | ARRAY_SIZE( |
| 290 | ar9285Modes_original_tx_gain_9285_1_2), 6); |
| 291 | } |
| 292 | } |
| 293 | } |
| 294 | } |
| 295 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 296 | /* |
| 297 | * Helper for ASPM support. |
| 298 | * |
| 299 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 300 | * This power saving option must be enabled through the SerDes. |
| 301 | * |
| 302 | * Programming the SerDes must go through the same 288 bit serial shift |
| 303 | * register as the other analog registers. Hence the 9 writes. |
| 304 | */ |
| 305 | static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
| 306 | int restore, |
| 307 | int power_off) |
| 308 | { |
| 309 | u8 i; |
| 310 | u32 val; |
| 311 | |
| 312 | if (ah->is_pciexpress != true) |
| 313 | return; |
| 314 | |
| 315 | /* Do not touch SerDes registers */ |
| 316 | if (ah->config.pcie_powersave_enable == 2) |
| 317 | return; |
| 318 | |
| 319 | /* Nothing to do on restore for 11N */ |
| 320 | if (!restore) { |
| 321 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 322 | /* |
| 323 | * AR9280 2.0 or later chips use SerDes values from the |
| 324 | * initvals.h initialized depending on chipset during |
| 325 | * __ath9k_hw_init() |
| 326 | */ |
| 327 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
| 328 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
| 329 | INI_RA(&ah->iniPcieSerdes, i, 1)); |
| 330 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 331 | } else { |
Sujith | d5e347b | 2010-04-23 10:28:11 +0530 | [diff] [blame] | 332 | ENABLE_REGWRITE_BUFFER(ah); |
| 333 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 334 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 335 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 336 | |
| 337 | /* RX shut off when elecidle is asserted */ |
| 338 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
| 339 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); |
| 340 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); |
| 341 | |
| 342 | /* |
| 343 | * Ignore ah->ah_config.pcie_clock_req setting for |
| 344 | * pre-AR9280 11n |
| 345 | */ |
| 346 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
| 347 | |
| 348 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 349 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 350 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
| 351 | |
| 352 | /* Load the new settings */ |
| 353 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
Sujith | d5e347b | 2010-04-23 10:28:11 +0530 | [diff] [blame] | 354 | |
| 355 | REGWRITE_BUFFER_FLUSH(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | udelay(1000); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 359 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 360 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 361 | if (power_off) { |
| 362 | /* clear bit 19 to disable L1 */ |
| 363 | REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 364 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 365 | val = REG_READ(ah, AR_WA); |
| 366 | |
| 367 | /* |
| 368 | * Set PCIe workaround bits |
| 369 | * In AR9280 and AR9285, bit 14 in WA register (disable L1) |
| 370 | * should only be set when device enters D3 and be |
| 371 | * cleared when device comes back to D0. |
| 372 | */ |
| 373 | if (ah->config.pcie_waen) { |
| 374 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
| 375 | val |= AR_WA_D3_L1_DISABLE; |
| 376 | } else { |
| 377 | if (((AR_SREV_9285(ah) || |
| 378 | AR_SREV_9271(ah) || |
| 379 | AR_SREV_9287(ah)) && |
| 380 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || |
| 381 | (AR_SREV_9280(ah) && |
| 382 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { |
| 383 | val |= AR_WA_D3_L1_DISABLE; |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { |
| 388 | /* |
| 389 | * Disable bit 6 and 7 before entering D3 to |
| 390 | * prevent system hang. |
| 391 | */ |
| 392 | val &= ~(AR_WA_BIT6 | AR_WA_BIT7); |
| 393 | } |
| 394 | |
Vasanthakumar Thiagarajan | f119da3 | 2010-11-04 17:41:25 -0700 | [diff] [blame] | 395 | if (AR_SREV_9280(ah)) |
| 396 | val |= AR_WA_BIT22; |
| 397 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 398 | if (AR_SREV_9285E_20(ah)) |
| 399 | val |= AR_WA_BIT23; |
| 400 | |
| 401 | REG_WRITE(ah, AR_WA, val); |
| 402 | } else { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 403 | if (ah->config.pcie_waen) { |
| 404 | val = ah->config.pcie_waen; |
| 405 | if (!power_off) |
| 406 | val &= (~AR_WA_D3_L1_DISABLE); |
| 407 | } else { |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 408 | if (AR_SREV_9285(ah) || |
| 409 | AR_SREV_9271(ah) || |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 410 | AR_SREV_9287(ah)) { |
| 411 | val = AR9285_WA_DEFAULT; |
| 412 | if (!power_off) |
| 413 | val &= (~AR_WA_D3_L1_DISABLE); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 414 | } |
| 415 | else if (AR_SREV_9280(ah)) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 416 | /* |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 417 | * For AR9280 chips, bit 22 of 0x4004 |
| 418 | * needs to be set. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 419 | */ |
| 420 | val = AR9280_WA_DEFAULT; |
| 421 | if (!power_off) |
| 422 | val &= (~AR_WA_D3_L1_DISABLE); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 423 | } else { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 424 | val = AR_WA_DEFAULT; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 425 | } |
| 426 | } |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 427 | |
| 428 | /* WAR for ASPM system hang */ |
Rajkumar Manoharan | 5b64aa7 | 2011-01-27 18:39:37 +0530 | [diff] [blame] | 429 | if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 430 | val |= (AR_WA_BIT6 | AR_WA_BIT7); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 431 | |
| 432 | if (AR_SREV_9285E_20(ah)) |
| 433 | val |= AR_WA_BIT23; |
| 434 | |
| 435 | REG_WRITE(ah, AR_WA, val); |
| 436 | |
| 437 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 438 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 439 | } |
| 440 | } |
| 441 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 442 | static int ar9002_hw_get_radiorev(struct ath_hw *ah) |
| 443 | { |
| 444 | u32 val; |
| 445 | int i; |
| 446 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 447 | ENABLE_REGWRITE_BUFFER(ah); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 448 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 449 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 450 | for (i = 0; i < 8; i++) |
| 451 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 452 | |
| 453 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 454 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 455 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; |
| 456 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); |
| 457 | |
| 458 | return ath9k_hw_reverse_bits(val, 8); |
| 459 | } |
| 460 | |
| 461 | int ar9002_hw_rf_claim(struct ath_hw *ah) |
| 462 | { |
| 463 | u32 val; |
| 464 | |
| 465 | REG_WRITE(ah, AR_PHY(0), 0x00000007); |
| 466 | |
| 467 | val = ar9002_hw_get_radiorev(ah); |
| 468 | switch (val & AR_RADIO_SREV_MAJOR) { |
| 469 | case 0: |
| 470 | val = AR_RAD5133_SREV_MAJOR; |
| 471 | break; |
| 472 | case AR_RAD5133_SREV_MAJOR: |
| 473 | case AR_RAD5122_SREV_MAJOR: |
| 474 | case AR_RAD2133_SREV_MAJOR: |
| 475 | case AR_RAD2122_SREV_MAJOR: |
| 476 | break; |
| 477 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 478 | ath_err(ath9k_hw_common(ah), |
| 479 | "Radio Chip Rev 0x%02X not supported\n", |
| 480 | val & AR_RADIO_SREV_MAJOR); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 481 | return -EOPNOTSUPP; |
| 482 | } |
| 483 | |
| 484 | ah->hw_version.analog5GhzRev = val; |
| 485 | |
| 486 | return 0; |
| 487 | } |
| 488 | |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 489 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah) |
| 490 | { |
| 491 | if (AR_SREV_9287_13_OR_LATER(ah)) { |
| 492 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 493 | AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); |
| 494 | REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); |
| 495 | REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 496 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 497 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 498 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 499 | } |
| 500 | } |
| 501 | |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 502 | /* |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 503 | * If Async FIFO is enabled, the following counters change as MAC now runs |
| 504 | * at 117 Mhz instead of 88/44MHz when async FIFO is disabled. |
| 505 | * |
| 506 | * The values below tested for ht40 2 chain. |
| 507 | * Overwrite the delay/timeouts initialized in process ini. |
| 508 | */ |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 509 | void ar9002_hw_update_async_fifo(struct ath_hw *ah) |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 510 | { |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 511 | if (AR_SREV_9287_13_OR_LATER(ah)) { |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 512 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
| 513 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); |
| 514 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, |
| 515 | AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); |
| 516 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, |
| 517 | AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); |
| 518 | |
| 519 | REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); |
| 520 | REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); |
| 521 | |
| 522 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, |
| 523 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); |
| 524 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, |
| 525 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); |
| 526 | } |
| 527 | } |
| 528 | |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 529 | /* |
| 530 | * We don't enable WEP aggregation on mac80211 but we keep this |
| 531 | * around for HAL unification purposes. |
| 532 | */ |
| 533 | void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah) |
| 534 | { |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 535 | if (AR_SREV_9287_13_OR_LATER(ah)) { |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 536 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 537 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 538 | } |
| 539 | } |
| 540 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 541 | /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ |
| 542 | void ar9002_hw_attach_ops(struct ath_hw *ah) |
| 543 | { |
| 544 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 545 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 546 | |
| 547 | priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 548 | priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 549 | |
| 550 | ops->config_pci_powersave = ar9002_hw_configpcipowersave; |
| 551 | |
| 552 | ar5008_hw_attach_phy_ops(ah); |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 553 | if (AR_SREV_9280_20_OR_LATER(ah)) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 554 | ar9002_hw_attach_phy_ops(ah); |
| 555 | |
| 556 | ar9002_hw_attach_calib_ops(ah); |
| 557 | ar9002_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 558 | } |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 559 | |
| 560 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) |
| 561 | { |
| 562 | u32 modesIndex; |
| 563 | int i; |
| 564 | |
| 565 | switch (chan->chanmode) { |
| 566 | case CHANNEL_A: |
| 567 | case CHANNEL_A_HT20: |
| 568 | modesIndex = 1; |
| 569 | break; |
| 570 | case CHANNEL_A_HT40PLUS: |
| 571 | case CHANNEL_A_HT40MINUS: |
| 572 | modesIndex = 2; |
| 573 | break; |
| 574 | case CHANNEL_G: |
| 575 | case CHANNEL_G_HT20: |
| 576 | case CHANNEL_B: |
| 577 | modesIndex = 4; |
| 578 | break; |
| 579 | case CHANNEL_G_HT40PLUS: |
| 580 | case CHANNEL_G_HT40MINUS: |
| 581 | modesIndex = 3; |
| 582 | break; |
| 583 | |
| 584 | default: |
| 585 | return; |
| 586 | } |
| 587 | |
| 588 | ENABLE_REGWRITE_BUFFER(ah); |
| 589 | |
| 590 | for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { |
| 591 | u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); |
| 592 | u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); |
| 593 | u32 val_orig; |
| 594 | |
| 595 | if (reg == AR_PHY_CCK_DETECT) { |
| 596 | val_orig = REG_READ(ah, reg); |
| 597 | val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
| 598 | val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
| 599 | |
| 600 | REG_WRITE(ah, reg, val|val_orig); |
| 601 | } else |
| 602 | REG_WRITE(ah, reg, val); |
| 603 | } |
| 604 | |
| 605 | REGWRITE_BUFFER_FLUSH(ah); |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 606 | } |