blob: 2eb8ae1b2d03f6780584ac6651ce488d3a70aaaf [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Tomasz Nowicki0cb07862016-06-10 21:55:19 +02006 select ACPI_MCFG if ACPI
Aleksey Makarov888125a2016-09-27 23:54:14 +03007 select ACPI_SPCR_TABLE if ACPI
Scott Wood1d8f51d2016-09-22 03:35:18 -05008 select ARCH_CLOCKSOURCE_DATA
Dan Williams21266be2015-11-19 18:19:29 -08009 select ARCH_HAS_DEVMEM_IS_ALLOWED
Jon Masters38b04a72016-06-20 13:56:13 +030010 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
Kees Cook2b68f6c2015-04-14 15:48:00 -070011 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -080012 select ARCH_HAS_GCOV_PROFILE_ALL
Yisheng Xie14f09912016-10-07 17:01:49 -070013 select ARCH_HAS_GIGANTIC_PAGE
Alexander Potapenko5e4c7542016-06-16 18:39:52 +020014 select ARCH_HAS_KCOV
Laura Abbott308c09f2014-08-08 14:23:25 -070015 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010016 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010017 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020018 select ARCH_SUPPORTS_ATOMIC_RMW
Ganapatrao Kulkarni56166232016-04-08 15:50:28 -070019 select ARCH_SUPPORTS_NUMA_BALANCING
Will Deacon6212a512012-11-07 14:16:28 +000020 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000021 select ARCH_WANT_FRAME_POINTERS
Yang Shif0b7f8a2016-02-05 15:50:18 -080022 select ARCH_HAS_UBSAN_SANITIZE_ALL
Catalin Marinas25c92a32012-12-18 15:26:13 +000023 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000024 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000025 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010026 select AUDIT_ARCH_COMPAT_GENERIC
Arnd Bergmann3ee80362016-06-15 15:47:33 -050027 select ARM_GIC_V2M if PCI
Marc Zyngier021f6532014-06-30 16:01:31 +010028 select ARM_GIC_V3
Arnd Bergmann3ee80362016-06-15 15:47:33 -050029 select ARM_GIC_V3_ITS if PCI
Mark Rutlandbff60792015-07-31 15:46:16 +010030 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010031 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000032 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070033 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000034 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000035 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010036 select EDAC_SUPPORT
Yang Shi2f34f172015-11-09 10:09:55 -080037 select FRAME_POINTER
Laura Abbottd4932f92014-10-09 15:26:44 -070038 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010040 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000041 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070042 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010043 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010044 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010046 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010047 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070048 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010049 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000050 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010053 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010054 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010055 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010056 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010057 select HAVE_ARCH_BITREVERSE
Kees Cookfaf5b632016-06-23 15:59:42 -070058 select HAVE_ARCH_HARDENED_USERCOPY
Ard Biesheuvel324420b2016-02-16 13:52:35 +010059 select HAVE_ARCH_HUGE_VMAP
Jiang Liu9732caf2014-01-07 22:17:13 +080060 select HAVE_ARCH_JUMP_LABEL
Andrey Ryabininf1b90322015-11-17 18:47:08 +030061 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
Vijaya Kumar K95292472014-01-28 11:20:22 +000062 select HAVE_ARCH_KGDB
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -080063 select HAVE_ARCH_MMAP_RND_BITS
64 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000065 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010066 select HAVE_ARCH_TRACEHOOK
Yang Shi8ee70872016-04-18 11:16:14 -070067 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
68 select HAVE_ARM_SMCCC
Daniel Borkmann60777762016-05-13 19:08:28 +020069 select HAVE_EBPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010070 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010071 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010072 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010073 select HAVE_CMPXCHG_LOCAL
Yang Shi8ee70872016-04-18 11:16:14 -070074 select HAVE_CONTEXT_TRACKING
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070075 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070076 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010077 select HAVE_DMA_API_DEBUG
Laura Abbott6ac21042013-12-12 19:28:33 +000078 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010079 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000080 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010081 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090082 select HAVE_FUNCTION_TRACER
83 select HAVE_FUNCTION_GRAPH_TRACER
Emese Revfy6b90bd42016-05-24 00:09:38 +020084 select HAVE_GCC_PLUGINS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010086 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Will Deacon24da2082015-11-23 15:12:59 +000087 select HAVE_IRQ_TIME_ACCOUNTING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010088 select HAVE_MEMBLOCK
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -070089 select HAVE_MEMBLOCK_NODE_MAP if NUMA
Mark Rutland55834a72014-02-07 17:12:45 +000090 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010091 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010092 select HAVE_PERF_REGS
93 select HAVE_PERF_USER_STACK_DUMP
David A. Long0a8ea522016-07-08 12:35:45 -040094 select HAVE_REGS_AND_STACK_ACCESS_API
Steve Capper5e5f6dc2014-10-09 15:29:23 -070095 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010096 select HAVE_SYSCALL_TRACEPOINTS
Sandeepa Prabhu2dd0e8d2016-07-08 12:35:48 -040097 select HAVE_KPROBES
Sandeepa Prabhufcfd7082016-07-08 12:35:53 -040098 select HAVE_KRETPROBES if HAVE_KPROBES
Robin Murphy876945d2015-10-01 20:14:00 +010099 select IOMMU_DMA if IOMMU_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100100 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +0200101 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +0100102 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100103 select NO_BOOTMEM
104 select OF
105 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +0100106 select OF_RESERVED_MEM
Tomasz Nowicki0cb07862016-06-10 21:55:19 +0200107 select PCI_ECAM if ACPI
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000108 select POWER_RESET
109 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100110 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -0700111 select SYSCTL_EXCEPTION_TRACE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100112 help
113 ARM 64-bit (AArch64) Linux support.
114
115config 64BIT
116 def_bool y
117
118config ARCH_PHYS_ADDR_T_64BIT
119 def_bool y
120
121config MMU
122 def_bool y
123
Mark Rutland40982fd2016-08-25 17:23:23 +0100124config DEBUG_RODATA
125 def_bool y
126
Mark Rutland030c4d22016-05-31 15:57:59 +0100127config ARM64_PAGE_SHIFT
128 int
129 default 16 if ARM64_64K_PAGES
130 default 14 if ARM64_16K_PAGES
131 default 12
132
133config ARM64_CONT_SHIFT
134 int
135 default 5 if ARM64_64K_PAGES
136 default 7 if ARM64_16K_PAGES
137 default 4
138
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -0800139config ARCH_MMAP_RND_BITS_MIN
140 default 14 if ARM64_64K_PAGES
141 default 16 if ARM64_16K_PAGES
142 default 18
143
144# max bits determined by the following formula:
145# VA_BITS - PAGE_SHIFT - 3
146config ARCH_MMAP_RND_BITS_MAX
147 default 19 if ARM64_VA_BITS=36
148 default 24 if ARM64_VA_BITS=39
149 default 27 if ARM64_VA_BITS=42
150 default 30 if ARM64_VA_BITS=47
151 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
152 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
153 default 33 if ARM64_VA_BITS=48
154 default 14 if ARM64_64K_PAGES
155 default 16 if ARM64_16K_PAGES
156 default 18
157
158config ARCH_MMAP_RND_COMPAT_BITS_MIN
159 default 7 if ARM64_64K_PAGES
160 default 9 if ARM64_16K_PAGES
161 default 11
162
163config ARCH_MMAP_RND_COMPAT_BITS_MAX
164 default 16
165
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700166config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100167 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100168
169config STACKTRACE_SUPPORT
170 def_bool y
171
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100172config ILLEGAL_POINTER_VALUE
173 hex
174 default 0xdead000000000000
175
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100176config LOCKDEP_SUPPORT
177 def_bool y
178
179config TRACE_IRQFLAGS_SUPPORT
180 def_bool y
181
Will Deaconc209f792014-03-14 17:47:05 +0000182config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100183 def_bool y
184
Dave P Martin9fb74102015-07-24 16:37:48 +0100185config GENERIC_BUG
186 def_bool y
187 depends on BUG
188
189config GENERIC_BUG_RELATIVE_POINTERS
190 def_bool y
191 depends on GENERIC_BUG
192
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100193config GENERIC_HWEIGHT
194 def_bool y
195
196config GENERIC_CSUM
197 def_bool y
198
199config GENERIC_CALIBRATE_DELAY
200 def_bool y
201
Catalin Marinas19e76402014-02-27 12:09:22 +0000202config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100203 def_bool y
204
Steve Capper29e56942014-10-09 15:29:25 -0700205config HAVE_GENERIC_RCU_GUP
206 def_bool y
207
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100208config ARCH_DMA_ADDR_T_64BIT
209 def_bool y
210
211config NEED_DMA_MAP_STATE
212 def_bool y
213
214config NEED_SG_DMA_LENGTH
215 def_bool y
216
Will Deacon4b3dc962015-05-29 18:28:44 +0100217config SMP
218 def_bool y
219
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100220config SWIOTLB
221 def_bool y
222
223config IOMMU_HELPER
224 def_bool SWIOTLB
225
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100226config KERNEL_MODE_NEON
227 def_bool y
228
Rob Herring92cc15f2014-04-18 17:19:59 -0500229config FIX_EARLYCON_MEM
230 def_bool y
231
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700232config PGTABLE_LEVELS
233 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100234 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700235 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
236 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
237 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100238 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
239 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700240
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100241source "init/Kconfig"
242
243source "kernel/Kconfig.freezer"
244
Olof Johansson6a377492015-07-20 12:09:16 -0700245source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100246
247menu "Bus support"
248
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100249config PCI
250 bool "PCI support"
251 help
252 This feature enables support for PCI bus system. If you say Y
253 here, the kernel will include drivers and infrastructure code
254 to support PCI bus devices.
255
256config PCI_DOMAINS
257 def_bool PCI
258
259config PCI_DOMAINS_GENERIC
260 def_bool PCI
261
262config PCI_SYSCALL
263 def_bool PCI
264
265source "drivers/pci/Kconfig"
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100266
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100267endmenu
268
269menu "Kernel Features"
270
Andre Przywarac0a01b82014-11-14 15:54:12 +0000271menu "ARM errata workarounds via the alternatives framework"
272
273config ARM64_ERRATUM_826319
274 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
275 default y
276 help
277 This option adds an alternative code sequence to work around ARM
278 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
279 AXI master interface and an L2 cache.
280
281 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
282 and is unable to accept a certain write via this interface, it will
283 not progress on read data presented on the read data channel and the
284 system can deadlock.
285
286 The workaround promotes data cache clean instructions to
287 data cache clean-and-invalidate.
288 Please note that this does not necessarily enable the workaround,
289 as it depends on the alternative framework, which will only patch
290 the kernel if an affected CPU is detected.
291
292 If unsure, say Y.
293
294config ARM64_ERRATUM_827319
295 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
296 default y
297 help
298 This option adds an alternative code sequence to work around ARM
299 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
300 master interface and an L2 cache.
301
302 Under certain conditions this erratum can cause a clean line eviction
303 to occur at the same time as another transaction to the same address
304 on the AMBA 5 CHI interface, which can cause data corruption if the
305 interconnect reorders the two transactions.
306
307 The workaround promotes data cache clean instructions to
308 data cache clean-and-invalidate.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
312
313 If unsure, say Y.
314
315config ARM64_ERRATUM_824069
316 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
317 default y
318 help
319 This option adds an alternative code sequence to work around ARM
320 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
321 to a coherent interconnect.
322
323 If a Cortex-A53 processor is executing a store or prefetch for
324 write instruction at the same time as a processor in another
325 cluster is executing a cache maintenance operation to the same
326 address, then this erratum might cause a clean cache line to be
327 incorrectly marked as dirty.
328
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this option does not necessarily enable the
332 workaround, as it depends on the alternative framework, which will
333 only patch the kernel if an affected CPU is detected.
334
335 If unsure, say Y.
336
337config ARM64_ERRATUM_819472
338 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
339 default y
340 help
341 This option adds an alternative code sequence to work around ARM
342 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
343 present when it is connected to a coherent interconnect.
344
345 If the processor is executing a load and store exclusive sequence at
346 the same time as a processor in another cluster is executing a cache
347 maintenance operation to the same address, then this erratum might
348 cause data corruption.
349
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
355
356 If unsure, say Y.
357
358config ARM64_ERRATUM_832075
359 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
360 default y
361 help
362 This option adds an alternative code sequence to work around ARM
363 erratum 832075 on Cortex-A57 parts up to r1p2.
364
365 Affected Cortex-A57 parts might deadlock when exclusive load/store
366 instructions to Write-Back memory are mixed with Device loads.
367
368 The workaround is to promote device loads to use Load-Acquire
369 semantics.
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
373
374 If unsure, say Y.
375
Marc Zyngier498cd5c2015-11-16 10:28:18 +0000376config ARM64_ERRATUM_834220
377 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
378 depends on KVM
379 default y
380 help
381 This option adds an alternative code sequence to work around ARM
382 erratum 834220 on Cortex-A57 parts up to r1p2.
383
384 Affected Cortex-A57 parts might report a Stage 2 translation
385 fault as the result of a Stage 1 fault for load crossing a
386 page boundary when there is a permission or device memory
387 alignment fault at Stage 1 and a translation fault at Stage 2.
388
389 The workaround is to verify that the Stage 1 translation
390 doesn't generate a fault before handling the Stage 2 fault.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
394
395 If unsure, say Y.
396
Will Deacon905e8c52015-03-23 19:07:02 +0000397config ARM64_ERRATUM_845719
398 bool "Cortex-A53: 845719: a load might read incorrect data"
399 depends on COMPAT
400 default y
401 help
402 This option adds an alternative code sequence to work around ARM
403 erratum 845719 on Cortex-A53 parts up to r0p4.
404
405 When running a compat (AArch32) userspace on an affected Cortex-A53
406 part, a load at EL0 from a virtual address that matches the bottom 32
407 bits of the virtual address used by a recent load at (AArch64) EL1
408 might return incorrect data.
409
410 The workaround is to write the contextidr_el1 register on exception
411 return to a 32-bit task.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
415
416 If unsure, say Y.
417
Will Deacondf057cc2015-03-17 12:15:02 +0000418config ARM64_ERRATUM_843419
419 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
Will Deacondf057cc2015-03-17 12:15:02 +0000420 default y
Will Deacon6ffe9922016-08-22 11:58:36 +0100421 select ARM64_MODULE_CMODEL_LARGE if MODULES
Will Deacondf057cc2015-03-17 12:15:02 +0000422 help
Will Deacon6ffe9922016-08-22 11:58:36 +0100423 This option links the kernel with '--fix-cortex-a53-843419' and
424 builds modules using the large memory model in order to avoid the use
425 of the ADRP instruction, which can cause a subsequent memory access
426 to use an incorrect address on Cortex-A53 parts up to r0p4.
Will Deacondf057cc2015-03-17 12:15:02 +0000427
428 If unsure, say Y.
429
Suzuki K Pouloseb8c32082018-03-26 15:12:49 +0100430config ARM64_ERRATUM_1024718
431 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
432 default y
433 help
434 This option adds work around for Arm Cortex-A55 Erratum 1024718.
435
436 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
437 update of the hardware dirty bit when the DBM/AP bits are updated
438 without a break-before-make. The work around is to disable the usage
439 of hardware DBM locally on the affected cores. CPUs not affected by
440 erratum will continue to use the feature.
441
442 If unsure, say Y.
443
Robert Richter94100972015-09-21 22:58:38 +0200444config CAVIUM_ERRATUM_22375
445 bool "Cavium erratum 22375, 24313"
446 default y
447 help
448 Enable workaround for erratum 22375, 24313.
449
450 This implements two gicv3-its errata workarounds for ThunderX. Both
451 with small impact affecting only ITS table allocation.
452
453 erratum 22375: only alloc 8MB table size
454 erratum 24313: ignore memory access type
455
456 The fixes are in ITS initialization and basically ignore memory access
457 type and table size provided by the TYPER and BASER registers.
458
459 If unsure, say Y.
460
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +0200461config CAVIUM_ERRATUM_23144
462 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
463 depends on NUMA
464 default y
465 help
466 ITS SYNC command hang for cross node io and collections/cpu mapping.
467
468 If unsure, say Y.
469
Robert Richter6d4e11c2015-09-21 22:58:35 +0200470config CAVIUM_ERRATUM_23154
471 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
472 default y
473 help
474 The gicv3 of ThunderX requires a modified version for
475 reading the IAR status to ensure data synchronization
476 (access to icc_iar1_el1 is not sync'ed before and after).
477
478 If unsure, say Y.
479
Andrew Pinski104a0c02016-02-24 17:44:57 -0800480config CAVIUM_ERRATUM_27456
481 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
482 default y
483 help
484 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
485 instructions may cause the icache to become corrupted if it
486 contains data for a non-current ASID. The fix is to
487 invalidate the icache when changing the mm context.
488
489 If unsure, say Y.
490
Shanker Donthineni095635b2017-03-07 08:20:38 -0600491config QCOM_QDF2400_ERRATUM_0065
492 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
493 default y
494 help
495 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
496 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
497 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
498
499 If unsure, say Y.
500
Andre Przywarac0a01b82014-11-14 15:54:12 +0000501endmenu
502
503
Jungseok Leee41ceed2014-05-12 10:40:38 +0100504choice
505 prompt "Page size"
506 default ARM64_4K_PAGES
507 help
508 Page size (translation granule) configuration.
509
510config ARM64_4K_PAGES
511 bool "4KB"
512 help
513 This feature enables 4KB pages support.
514
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100515config ARM64_16K_PAGES
516 bool "16KB"
517 help
518 The system will use 16KB pages support. AArch32 emulation
519 requires applications compiled with 16K (or a multiple of 16K)
520 aligned segments.
521
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100522config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100523 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100524 help
525 This feature enables 64KB pages support (4KB by default)
526 allowing only two levels of page tables and faster TLB
Suzuki K. Poulosedb488be2015-10-19 14:19:34 +0100527 look-up. AArch32 emulation requires applications compiled
528 with 64K aligned segments.
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100529
Jungseok Leee41ceed2014-05-12 10:40:38 +0100530endchoice
531
532choice
533 prompt "Virtual address space size"
534 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100535 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100536 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
537 help
538 Allows choosing one of multiple possible virtual address
539 space sizes. The level of translation table is determined by
540 a combination of page size and virtual address space size.
541
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100542config ARM64_VA_BITS_36
Catalin Marinas56a3f302015-10-20 14:59:20 +0100543 bool "36-bit" if EXPERT
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100544 depends on ARM64_16K_PAGES
545
Jungseok Leee41ceed2014-05-12 10:40:38 +0100546config ARM64_VA_BITS_39
547 bool "39-bit"
548 depends on ARM64_4K_PAGES
549
550config ARM64_VA_BITS_42
551 bool "42-bit"
552 depends on ARM64_64K_PAGES
553
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100554config ARM64_VA_BITS_47
555 bool "47-bit"
556 depends on ARM64_16K_PAGES
557
Jungseok Leec79b9542014-05-12 18:40:51 +0900558config ARM64_VA_BITS_48
559 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900560
Jungseok Leee41ceed2014-05-12 10:40:38 +0100561endchoice
562
563config ARM64_VA_BITS
564 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100565 default 36 if ARM64_VA_BITS_36
Jungseok Leee41ceed2014-05-12 10:40:38 +0100566 default 39 if ARM64_VA_BITS_39
567 default 42 if ARM64_VA_BITS_42
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100568 default 47 if ARM64_VA_BITS_47
Jungseok Leec79b9542014-05-12 18:40:51 +0900569 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100570
Will Deacona8720132013-10-11 14:52:19 +0100571config CPU_BIG_ENDIAN
572 bool "Build big-endian kernel"
573 help
574 Say Y if you plan on running a kernel in big-endian mode.
575
Mark Brownf6e763b2014-03-04 07:51:17 +0000576config SCHED_MC
577 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000578 help
579 Multi-core scheduler support improves the CPU scheduler's decision
580 making when dealing with multi-core CPU chips at a cost of slightly
581 increased overhead in some places. If unsure say N here.
582
583config SCHED_SMT
584 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000585 help
586 Improves the CPU scheduler's decision making when dealing with
587 MultiThreading at a cost of slightly increased overhead in some
588 places. If unsure say N here.
589
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100590config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000591 int "Maximum number of CPUs (2-4096)"
592 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100593 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100594 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100595
Mark Rutland9327e2c2013-10-24 20:30:18 +0100596config HOTPLUG_CPU
597 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800598 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100599 help
600 Say Y here to experiment with turning CPUs off and on. CPUs
601 can be controlled through /sys/devices/system/cpu.
602
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -0700603# Common NUMA Features
604config NUMA
605 bool "Numa Memory Allocation and Scheduler Support"
Kefeng Wang0c2a6cc2016-09-26 15:36:50 +0800606 select ACPI_NUMA if ACPI
607 select OF_NUMA
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -0700608 help
609 Enable NUMA (Non Uniform Memory Access) support.
610
611 The kernel will try to allocate memory used by a CPU on the
612 local memory of the CPU and add some more
613 NUMA awareness to the kernel.
614
615config NODES_SHIFT
616 int "Maximum NUMA Nodes (as a power of 2)"
617 range 1 10
618 default "2"
619 depends on NEED_MULTIPLE_NODES
620 help
621 Specify the maximum number of NUMA Nodes available on the target
622 system. Increases memory reserved to accommodate various tables.
623
624config USE_PERCPU_NUMA_NODE_ID
625 def_bool y
626 depends on NUMA
627
Zhen Lei7af3a0a2016-09-01 14:55:00 +0800628config HAVE_SETUP_PER_CPU_AREA
629 def_bool y
630 depends on NUMA
631
632config NEED_PER_CPU_EMBED_FIRST_CHUNK
633 def_bool y
634 depends on NUMA
635
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100636source kernel/Kconfig.preempt
Kefeng Wangf90df5e2015-10-26 11:48:16 +0800637source kernel/Kconfig.hz
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100638
Laura Abbott83863f22016-02-05 16:24:47 -0800639config ARCH_SUPPORTS_DEBUG_PAGEALLOC
640 def_bool y
641
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100642config ARCH_HAS_HOLES_MEMORYMODEL
643 def_bool y if SPARSEMEM
644
645config ARCH_SPARSEMEM_ENABLE
646 def_bool y
647 select SPARSEMEM_VMEMMAP_ENABLE
648
649config ARCH_SPARSEMEM_DEFAULT
650 def_bool ARCH_SPARSEMEM_ENABLE
651
652config ARCH_SELECT_MEMORY_MODEL
653 def_bool ARCH_SPARSEMEM_ENABLE
654
655config HAVE_ARCH_PFN_VALID
656 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
657
658config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100659 def_bool y
660 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100661
Steve Capper084bd292013-04-10 13:48:00 +0100662config SYS_SUPPORTS_HUGETLBFS
663 def_bool y
664
Steve Capper084bd292013-04-10 13:48:00 +0100665config ARCH_WANT_HUGE_PMD_SHARE
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100666 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
Steve Capper084bd292013-04-10 13:48:00 +0100667
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100668config ARCH_HAS_CACHE_LINE_SIZE
669 def_bool y
670
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100671source "mm/Kconfig"
672
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000673config SECCOMP
674 bool "Enable seccomp to safely compute untrusted bytecode"
675 ---help---
676 This kernel feature is useful for number crunching applications
677 that may need to compute untrusted bytecode during their
678 execution. By using pipes or other transports made available to
679 the process as file descriptors supporting the read/write
680 syscalls, it's possible to isolate those applications in
681 their own address space using seccomp. Once seccomp is
682 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
683 and the task is only allowed to execute a few safe syscalls
684 defined by each seccomp mode.
685
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000686config PARAVIRT
687 bool "Enable paravirtualization code"
688 help
689 This changes the kernel so it can modify itself when it is run
690 under a hypervisor, potentially improving performance significantly
691 over full virtualization.
692
693config PARAVIRT_TIME_ACCOUNTING
694 bool "Paravirtual steal time accounting"
695 select PARAVIRT
696 default n
697 help
698 Select this option to enable fine granularity task steal time
699 accounting. Time spent executing other tasks in parallel with
700 the current vCPU is discounted from the vCPU power. To account for
701 that, there can be a small performance impact.
702
703 If in doubt, say N here.
704
Geoff Levandd28f6df2016-06-23 17:54:48 +0000705config KEXEC
706 depends on PM_SLEEP_SMP
707 select KEXEC_CORE
708 bool "kexec system call"
709 ---help---
710 kexec is a system call that implements the ability to shutdown your
711 current kernel, and to start another kernel. It is like a reboot
712 but it is independent of the system firmware. And like a reboot
713 you can start any kernel with it, not just Linux.
714
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000715config XEN_DOM0
716 def_bool y
717 depends on XEN
718
719config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700720 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000721 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000722 select SWIOTLB_XEN
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000723 select PARAVIRT
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000724 help
725 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
726
Steve Capperd03bb142013-04-25 15:19:21 +0100727config FORCE_MAX_ZONEORDER
728 int
729 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100730 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
Steve Capperd03bb142013-04-25 15:19:21 +0100731 default "11"
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100732 help
733 The kernel memory allocator divides physically contiguous memory
734 blocks into "zones", where each zone is a power of two number of
735 pages. This option selects the largest power of two that the kernel
736 keeps in the memory allocator. If you need to allocate very large
737 blocks of physically contiguous memory, then you may need to
738 increase this value.
739
740 This config option is actually maximum order plus one. For example,
741 a value of 11 means that the largest free memory block is 2^10 pages.
742
743 We make sure that we can allocate upto a HugePage size for each configuration.
744 Hence we have :
745 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
746
747 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
748 4M allocations matching the default size used by generic code.
Steve Capperd03bb142013-04-25 15:19:21 +0100749
Will Deacon531a0eb2018-04-03 12:09:12 +0100750config UNMAP_KERNEL_AT_EL0
Will Deaconded98c62018-04-03 12:09:13 +0100751 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
Will Deacon531a0eb2018-04-03 12:09:12 +0100752 default y
753 help
Will Deaconded98c62018-04-03 12:09:13 +0100754 Speculation attacks against some high-performance processors can
755 be used to bypass MMU permission checks and leak kernel data to
756 userspace. This can be defended against by unmapping the kernel
757 when running in userspace, mapping it back in on exception entry
758 via a trampoline page in the vector table.
Will Deacon531a0eb2018-04-03 12:09:12 +0100759
760 If unsure, say Y.
761
Mark Rutland47320012018-04-12 12:11:13 +0100762config HARDEN_BRANCH_PREDICTOR
763 bool "Harden the branch predictor against aliasing attacks" if EXPERT
764 default y
765 help
766 Speculation attacks against some high-performance processors rely on
767 being able to manipulate the branch predictor for a victim context by
768 executing aliasing branches in the attacker context. Such attacks
769 can be partially mitigated against by clearing internal branch
770 predictor state and limiting the prediction logic in some situations.
771
772 This config option will take CPU-specific actions to harden the
773 branch predictor against aliasing attacks and may rely on specific
774 instruction sequences or control bits being set by the system
775 firmware.
776
777 If unsure, say Y.
778
Marc Zyngiere7037bd2018-07-20 10:56:24 +0100779config ARM64_SSBD
780 bool "Speculative Store Bypass Disable" if EXPERT
781 default y
782 help
783 This enables mitigation of the bypassing of previous stores
784 by speculative loads.
785
786 If unsure, say Y.
787
Will Deacon1b907f42014-11-20 16:51:10 +0000788menuconfig ARMV8_DEPRECATED
789 bool "Emulate deprecated/obsolete ARMv8 instructions"
790 depends on COMPAT
791 help
792 Legacy software support may require certain instructions
793 that have been deprecated or obsoleted in the architecture.
794
795 Enable this config to enable selective emulation of these
796 features.
797
798 If unsure, say Y
799
800if ARMV8_DEPRECATED
801
802config SWP_EMULATION
803 bool "Emulate SWP/SWPB instructions"
804 help
805 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
806 they are always undefined. Say Y here to enable software
807 emulation of these instructions for userspace using LDXR/STXR.
808
809 In some older versions of glibc [<=2.8] SWP is used during futex
810 trylock() operations with the assumption that the code will not
811 be preempted. This invalid assumption may be more likely to fail
812 with SWP emulation enabled, leading to deadlock of the user
813 application.
814
815 NOTE: when accessing uncached shared regions, LDXR/STXR rely
816 on an external transaction monitoring block called a global
817 monitor to maintain update atomicity. If your system does not
818 implement a global monitor, this option can cause programs that
819 perform SWP operations to uncached memory to deadlock.
820
821 If unsure, say Y
822
823config CP15_BARRIER_EMULATION
824 bool "Emulate CP15 Barrier instructions"
825 help
826 The CP15 barrier instructions - CP15ISB, CP15DSB, and
827 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
828 strongly recommended to use the ISB, DSB, and DMB
829 instructions instead.
830
831 Say Y here to enable software emulation of these
832 instructions for AArch32 userspace code. When this option is
833 enabled, CP15 barrier usage is traced which can help
834 identify software that needs updating.
835
836 If unsure, say Y
837
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000838config SETEND_EMULATION
839 bool "Emulate SETEND instruction"
840 help
841 The SETEND instruction alters the data-endianness of the
842 AArch32 EL0, and is deprecated in ARMv8.
843
844 Say Y here to enable software emulation of the instruction
845 for AArch32 userspace code.
846
847 Note: All the cpus on the system must have mixed endian support at EL0
848 for this feature to be enabled. If a new CPU - which doesn't support mixed
849 endian - is hotplugged in after this feature has been enabled, there could
850 be unexpected results in the applications.
851
852 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000853endif
854
Will Deacon0e4a0702015-07-27 15:54:13 +0100855menu "ARMv8.1 architectural features"
856
857config ARM64_HW_AFDBM
858 bool "Support for hardware updates of the Access and Dirty page flags"
859 default y
860 help
861 The ARMv8.1 architecture extensions introduce support for
862 hardware updates of the access and dirty information in page
863 table entries. When enabled in TCR_EL1 (HA and HD bits) on
864 capable processors, accesses to pages with PTE_AF cleared will
865 set this bit instead of raising an access flag fault.
866 Similarly, writes to read-only pages with the DBM bit set will
867 clear the read-only bit (AP[2]) instead of raising a
868 permission fault.
869
870 Kernels built with this configuration option enabled continue
871 to work on pre-ARMv8.1 hardware and the performance impact is
872 minimal. If unsure, say Y.
873
874config ARM64_PAN
875 bool "Enable support for Privileged Access Never (PAN)"
876 default y
877 help
878 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
879 prevents the kernel or hypervisor from accessing user-space (EL0)
880 memory directly.
881
882 Choosing this option will cause any unprotected (not using
883 copy_to_user et al) memory access to fail with a permission fault.
884
885 The feature is detected at runtime, and will remain as a 'nop'
886 instruction if the cpu does not implement the feature.
887
888config ARM64_LSE_ATOMICS
889 bool "Atomic instructions"
890 help
891 As part of the Large System Extensions, ARMv8.1 introduces new
892 atomic instructions that are designed specifically to scale in
893 very large systems.
894
895 Say Y here to make use of these instructions for the in-kernel
896 atomic routines. This incurs a small overhead on CPUs that do
897 not support these instructions and requires the kernel to be
898 built with binutils >= 2.25.
899
Marc Zyngier1f364c82014-02-19 09:33:14 +0000900config ARM64_VHE
901 bool "Enable support for Virtualization Host Extensions (VHE)"
902 default y
903 help
904 Virtualization Host Extensions (VHE) allow the kernel to run
905 directly at EL2 (instead of EL1) on processors that support
906 it. This leads to better performance for KVM, as they reduce
907 the cost of the world switch.
908
909 Selecting this option allows the VHE feature to be detected
910 at runtime, and does not affect processors that do not
911 implement this feature.
912
Will Deacon0e4a0702015-07-27 15:54:13 +0100913endmenu
914
Will Deaconf9933182016-02-26 16:30:14 +0000915menu "ARMv8.2 architectural features"
916
James Morse57f49592016-02-05 14:58:48 +0000917config ARM64_UAO
918 bool "Enable support for User Access Override (UAO)"
919 default y
920 help
921 User Access Override (UAO; part of the ARMv8.2 Extensions)
922 causes the 'unprivileged' variant of the load/store instructions to
923 be overriden to be privileged.
924
925 This option changes get_user() and friends to use the 'unprivileged'
926 variant of the load/store instructions. This ensures that user-space
927 really did have access to the supplied memory. When addr_limit is
928 set to kernel memory the UAO bit will be set, allowing privileged
929 access to kernel memory.
930
931 Choosing this option will cause copy_to_user() et al to use user-space
932 memory permissions.
933
934 The feature is detected at runtime, the kernel will use the
935 regular load/store instructions if the cpu does not implement the
936 feature.
937
Will Deaconf9933182016-02-26 16:30:14 +0000938endmenu
939
Ard Biesheuvelfd045f62015-11-24 12:37:35 +0100940config ARM64_MODULE_CMODEL_LARGE
941 bool
942
943config ARM64_MODULE_PLTS
944 bool
945 select ARM64_MODULE_CMODEL_LARGE
946 select HAVE_MOD_ARCH_SPECIFIC
947
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +0100948config RELOCATABLE
949 bool
950 help
951 This builds the kernel as a Position Independent Executable (PIE),
952 which retains all relocation metadata required to relocate the
953 kernel binary at runtime to a different virtual address than the
954 address it was linked at.
955 Since AArch64 uses the RELA relocation format, this requires a
956 relocation pass at runtime even if the kernel is loaded at the
957 same address it was linked at.
958
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100959config RANDOMIZE_BASE
960 bool "Randomize the address of the kernel image"
Catalin Marinasb9c220b2016-07-26 10:16:55 -0700961 select ARM64_MODULE_PLTS if MODULES
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100962 select RELOCATABLE
963 help
964 Randomizes the virtual address at which the kernel image is
965 loaded, as a security feature that deters exploit attempts
966 relying on knowledge of the location of kernel internals.
967
968 It is the bootloader's job to provide entropy, by passing a
969 random u64 value in /chosen/kaslr-seed at kernel entry.
970
Ard Biesheuvel2b5fe072016-01-26 14:48:29 +0100971 When booting via the UEFI stub, it will invoke the firmware's
972 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
973 to the kernel proper. In addition, it will randomise the physical
974 location of the kernel Image as well.
975
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100976 If unsure, say N.
977
978config RANDOMIZE_MODULE_REGION_FULL
979 bool "Randomize the module region independently from the core kernel"
Ard Biesheuvel8fe88a42016-10-17 16:18:39 +0100980 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100981 default y
982 help
983 Randomizes the location of the module region without considering the
984 location of the core kernel. This way, it is impossible for modules
985 to leak information about the location of core kernel data structures
986 but it does imply that function calls between modules and the core
987 kernel will need to be resolved via veneers in the module PLT.
988
989 When this option is not set, the module region will be randomized over
990 a limited range that contains the [_stext, _etext] interval of the
991 core kernel, so branch relocations are always in range.
992
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100993endmenu
994
995menu "Boot options"
996
Lorenzo Pieralisi5e89c552016-01-26 11:10:38 +0000997config ARM64_ACPI_PARKING_PROTOCOL
998 bool "Enable support for the ARM64 ACPI parking protocol"
999 depends on ACPI
1000 help
1001 Enable support for the ARM64 ACPI parking protocol. If disabled
1002 the kernel will not allow booting through the ARM64 ACPI parking
1003 protocol even if the corresponding data is present in the ACPI
1004 MADT table.
1005
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001006config CMDLINE
1007 string "Default kernel command string"
1008 default ""
1009 help
1010 Provide a set of default command-line options at build time by
1011 entering them here. As a minimum, you should specify the the
1012 root device (e.g. root=/dev/nfs).
1013
1014config CMDLINE_FORCE
1015 bool "Always use the default kernel command string"
1016 help
1017 Always use the default kernel command string, even if the boot
1018 loader passes other arguments to the kernel.
1019 This is useful if you cannot or don't want to change the
1020 command-line options your boot loader passes to the kernel.
1021
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02001022config EFI_STUB
1023 bool
1024
Mark Salterf84d0272014-04-15 21:59:30 -04001025config EFI
1026 bool "UEFI runtime support"
1027 depends on OF && !CPU_BIG_ENDIAN
1028 select LIBFDT
1029 select UCS2_STRING
1030 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +02001031 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02001032 select EFI_STUB
1033 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -04001034 default y
1035 help
1036 This option provides support for runtime services provided
1037 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -04001038 clock, and platform reset). A UEFI stub is also provided to
1039 allow the kernel to be booted as an EFI application. This
1040 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -04001041
Yi Lid1ae8c02014-10-04 23:46:43 +08001042config DMI
1043 bool "Enable support for SMBIOS (DMI) tables"
1044 depends on EFI
1045 default y
1046 help
1047 This enables SMBIOS/DMI feature for systems.
1048
1049 This option is only useful on systems that have UEFI firmware.
1050 However, even with this option, the resultant kernel should
1051 continue to boot on existing non-UEFI platforms.
1052
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001053endmenu
1054
1055menu "Userspace binary formats"
1056
1057source "fs/Kconfig.binfmt"
1058
1059config COMPAT
1060 bool "Kernel support for 32-bit EL0"
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +01001061 depends on ARM64_4K_PAGES || EXPERT
Kefeng Wange631a1a2017-01-26 11:19:55 +08001062 select COMPAT_BINFMT_ELF if BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -07001063 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -05001064 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -05001065 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001066 help
1067 This option enables support for a 32-bit EL0 running under a 64-bit
1068 kernel at EL1. AArch32-specific components such as system calls,
1069 the user helper functions, VFP support and the ptrace interface are
1070 handled appropriately by the kernel.
1071
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +01001072 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1073 that you will only be able to execute AArch32 binaries that were compiled
1074 with page size aligned segments.
Alexander Grafa8fcd8b2015-03-16 16:32:23 +00001075
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001076 If you want to execute 32-bit userspace applications, say Y.
1077
1078config SYSVIPC_COMPAT
1079 def_bool y
1080 depends on COMPAT && SYSVIPC
1081
Eric Biggerscc2852a2017-03-08 16:27:04 -08001082config KEYS_COMPAT
1083 def_bool y
1084 depends on COMPAT && KEYS
1085
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001086endmenu
1087
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001088menu "Power management options"
1089
1090source "kernel/power/Kconfig"
1091
James Morse82869ac2016-04-27 17:47:12 +01001092config ARCH_HIBERNATION_POSSIBLE
1093 def_bool y
1094 depends on CPU_PM
1095
1096config ARCH_HIBERNATION_HEADER
1097 def_bool y
1098 depends on HIBERNATION
1099
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001100config ARCH_SUSPEND_POSSIBLE
1101 def_bool y
1102
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001103endmenu
1104
Lorenzo Pieralisi13072202013-07-17 14:54:21 +01001105menu "CPU Power Management"
1106
1107source "drivers/cpuidle/Kconfig"
1108
Rob Herring52e7e812014-02-24 11:27:57 +09001109source "drivers/cpufreq/Kconfig"
1110
1111endmenu
1112
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001113source "net/Kconfig"
1114
1115source "drivers/Kconfig"
1116
Mark Salterf84d0272014-04-15 21:59:30 -04001117source "drivers/firmware/Kconfig"
1118
Graeme Gregoryb6a02172015-03-24 14:02:53 +00001119source "drivers/acpi/Kconfig"
1120
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001121source "fs/Kconfig"
1122
Marc Zyngierc3eb5b12013-07-04 13:34:32 +01001123source "arch/arm64/kvm/Kconfig"
1124
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001125source "arch/arm64/Kconfig.debug"
1126
1127source "security/Kconfig"
1128
1129source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +08001130if CRYPTO
1131source "arch/arm64/crypto/Kconfig"
1132endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001133
1134source "lib/Kconfig"