Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/process.c |
| 3 | * |
| 4 | * Original Copyright (C) 1995 Linus Torvalds |
| 5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <stdarg.h> |
| 22 | |
AKASHI Takahiro | fd92d4a | 2014-04-30 10:51:32 +0100 | [diff] [blame] | 23 | #include <linux/compat.h> |
Ard Biesheuvel | 60c0d45 | 2015-03-06 15:49:24 +0100 | [diff] [blame] | 24 | #include <linux/efi.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 25 | #include <linux/export.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/kernel.h> |
| 28 | #include <linux/mm.h> |
| 29 | #include <linux/stddef.h> |
| 30 | #include <linux/unistd.h> |
| 31 | #include <linux/user.h> |
| 32 | #include <linux/delay.h> |
| 33 | #include <linux/reboot.h> |
| 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/kallsyms.h> |
| 36 | #include <linux/init.h> |
| 37 | #include <linux/cpu.h> |
| 38 | #include <linux/elfcore.h> |
| 39 | #include <linux/pm.h> |
| 40 | #include <linux/tick.h> |
| 41 | #include <linux/utsname.h> |
| 42 | #include <linux/uaccess.h> |
| 43 | #include <linux/random.h> |
| 44 | #include <linux/hw_breakpoint.h> |
| 45 | #include <linux/personality.h> |
| 46 | #include <linux/notifier.h> |
Jisheng Zhang | 096b322 | 2015-09-16 22:23:21 +0800 | [diff] [blame] | 47 | #include <trace/events/power.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 48 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 49 | #include <asm/alternative.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 50 | #include <asm/compat.h> |
| 51 | #include <asm/cacheflush.h> |
James Morse | d085441 | 2016-10-18 11:27:48 +0100 | [diff] [blame] | 52 | #include <asm/exec.h> |
Will Deacon | ec45d1c | 2013-01-17 12:31:45 +0000 | [diff] [blame] | 53 | #include <asm/fpsimd.h> |
| 54 | #include <asm/mmu_context.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 55 | #include <asm/processor.h> |
| 56 | #include <asm/stacktrace.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 57 | |
Laura Abbott | c0c264a | 2014-06-25 23:55:03 +0100 | [diff] [blame] | 58 | #ifdef CONFIG_CC_STACKPROTECTOR |
| 59 | #include <linux/stackprotector.h> |
| 60 | unsigned long __stack_chk_guard __read_mostly; |
| 61 | EXPORT_SYMBOL(__stack_chk_guard); |
| 62 | #endif |
| 63 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 64 | /* |
| 65 | * Function pointers to optional machine specific functions |
| 66 | */ |
| 67 | void (*pm_power_off)(void); |
| 68 | EXPORT_SYMBOL_GPL(pm_power_off); |
| 69 | |
Catalin Marinas | b0946fc | 2013-07-23 11:05:10 +0100 | [diff] [blame] | 70 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 71 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 72 | /* |
| 73 | * This is our default idle handler. |
| 74 | */ |
Thomas Gleixner | 0087298 | 2013-03-21 22:49:39 +0100 | [diff] [blame] | 75 | void arch_cpu_idle(void) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 76 | { |
| 77 | /* |
| 78 | * This should do all the clock switching and wait for interrupt |
| 79 | * tricks |
| 80 | */ |
Jisheng Zhang | 096b322 | 2015-09-16 22:23:21 +0800 | [diff] [blame] | 81 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
Nicolas Pitre | 6990566 | 2014-02-17 10:59:30 -0500 | [diff] [blame] | 82 | cpu_do_idle(); |
| 83 | local_irq_enable(); |
Jisheng Zhang | 096b322 | 2015-09-16 22:23:21 +0800 | [diff] [blame] | 84 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 85 | } |
| 86 | |
Mark Rutland | 9327e2c | 2013-10-24 20:30:18 +0100 | [diff] [blame] | 87 | #ifdef CONFIG_HOTPLUG_CPU |
| 88 | void arch_cpu_idle_dead(void) |
| 89 | { |
| 90 | cpu_die(); |
| 91 | } |
| 92 | #endif |
| 93 | |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 94 | /* |
| 95 | * Called by kexec, immediately prior to machine_kexec(). |
| 96 | * |
| 97 | * This must completely disable all secondary CPUs; simply causing those CPUs |
| 98 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the |
| 99 | * kexec'd kernel to use any and all RAM as it sees fit, without having to |
| 100 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug |
| 101 | * functionality embodied in disable_nonboot_cpus() to achieve this. |
| 102 | */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 103 | void machine_shutdown(void) |
| 104 | { |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 105 | disable_nonboot_cpus(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 106 | } |
| 107 | |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 108 | /* |
| 109 | * Halting simply requires that the secondary CPUs stop performing any |
| 110 | * activity (executing tasks, handling interrupts). smp_send_stop() |
| 111 | * achieves this. |
| 112 | */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 113 | void machine_halt(void) |
| 114 | { |
Arun KS | b9acc49 | 2014-05-07 02:41:23 +0100 | [diff] [blame] | 115 | local_irq_disable(); |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 116 | smp_send_stop(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 117 | while (1); |
| 118 | } |
| 119 | |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 120 | /* |
| 121 | * Power-off simply requires that the secondary CPUs stop performing any |
| 122 | * activity (executing tasks, handling interrupts). smp_send_stop() |
| 123 | * achieves this. When the system power is turned off, it will take all CPUs |
| 124 | * with it. |
| 125 | */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 126 | void machine_power_off(void) |
| 127 | { |
Arun KS | b9acc49 | 2014-05-07 02:41:23 +0100 | [diff] [blame] | 128 | local_irq_disable(); |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 129 | smp_send_stop(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 130 | if (pm_power_off) |
| 131 | pm_power_off(); |
| 132 | } |
| 133 | |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 134 | /* |
| 135 | * Restart requires that the secondary CPUs stop performing any activity |
Mark Rutland | 68234df | 2015-04-20 10:24:35 +0100 | [diff] [blame] | 136 | * while the primary CPU resets the system. Systems with multiple CPUs must |
Arun KS | 90f51a0 | 2014-05-07 02:41:22 +0100 | [diff] [blame] | 137 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
| 138 | * This is required so that any code running after reset on the primary CPU |
| 139 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still |
| 140 | * executing pre-reset code, and using RAM that the primary CPU's code wishes |
| 141 | * to use. Implementing such co-ordination would be essentially impossible. |
| 142 | */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 143 | void machine_restart(char *cmd) |
| 144 | { |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 145 | /* Disable interrupts first */ |
| 146 | local_irq_disable(); |
Arun KS | b9acc49 | 2014-05-07 02:41:23 +0100 | [diff] [blame] | 147 | smp_send_stop(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 148 | |
Ard Biesheuvel | 60c0d45 | 2015-03-06 15:49:24 +0100 | [diff] [blame] | 149 | /* |
| 150 | * UpdateCapsule() depends on the system being reset via |
| 151 | * ResetSystem(). |
| 152 | */ |
| 153 | if (efi_enabled(EFI_RUNTIME_SERVICES)) |
| 154 | efi_reboot(reboot_mode, NULL); |
| 155 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 156 | /* Now call the architecture specific reboot code. */ |
Catalin Marinas | aa1e8ec | 2013-02-28 18:14:37 +0000 | [diff] [blame] | 157 | if (arm_pm_restart) |
Marc Zyngier | ff70130 | 2013-07-11 12:13:00 +0100 | [diff] [blame] | 158 | arm_pm_restart(reboot_mode, cmd); |
Guenter Roeck | 1c7ffc3 | 2014-09-26 00:03:16 +0000 | [diff] [blame] | 159 | else |
| 160 | do_kernel_restart(cmd); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 161 | |
| 162 | /* |
| 163 | * Whoops - the architecture was unable to reboot. |
| 164 | */ |
| 165 | printk("Reboot failed -- System halted\n"); |
| 166 | while (1); |
| 167 | } |
| 168 | |
| 169 | void __show_regs(struct pt_regs *regs) |
| 170 | { |
Catalin Marinas | 6ca68e8 | 2013-09-17 18:49:46 +0100 | [diff] [blame] | 171 | int i, top_reg; |
| 172 | u64 lr, sp; |
| 173 | |
| 174 | if (compat_user_mode(regs)) { |
| 175 | lr = regs->compat_lr; |
| 176 | sp = regs->compat_sp; |
| 177 | top_reg = 12; |
| 178 | } else { |
| 179 | lr = regs->regs[30]; |
| 180 | sp = regs->sp; |
| 181 | top_reg = 29; |
| 182 | } |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 183 | |
Tejun Heo | a43cb95 | 2013-04-30 15:27:17 -0700 | [diff] [blame] | 184 | show_regs_print_info(KERN_DEFAULT); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 185 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
Catalin Marinas | 6ca68e8 | 2013-09-17 18:49:46 +0100 | [diff] [blame] | 186 | print_symbol("LR is at %s\n", lr); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 187 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
Catalin Marinas | 6ca68e8 | 2013-09-17 18:49:46 +0100 | [diff] [blame] | 188 | regs->pc, lr, regs->pstate); |
| 189 | printk("sp : %016llx\n", sp); |
Mark Rutland | db4b071 | 2016-10-20 12:23:16 +0100 | [diff] [blame] | 190 | |
| 191 | i = top_reg; |
| 192 | |
| 193 | while (i >= 0) { |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 194 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
Mark Rutland | db4b071 | 2016-10-20 12:23:16 +0100 | [diff] [blame] | 195 | i--; |
| 196 | |
| 197 | if (i % 2 == 0) { |
| 198 | pr_cont("x%-2d: %016llx ", i, regs->regs[i]); |
| 199 | i--; |
| 200 | } |
| 201 | |
| 202 | pr_cont("\n"); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 203 | } |
| 204 | printk("\n"); |
| 205 | } |
| 206 | |
| 207 | void show_regs(struct pt_regs * regs) |
| 208 | { |
| 209 | printk("\n"); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 210 | __show_regs(regs); |
| 211 | } |
| 212 | |
Will Deacon | eb35bdd | 2014-09-11 14:38:16 +0100 | [diff] [blame] | 213 | static void tls_thread_flush(void) |
| 214 | { |
Mark Rutland | adf7589 | 2016-09-08 13:55:38 +0100 | [diff] [blame] | 215 | write_sysreg(0, tpidr_el0); |
Will Deacon | eb35bdd | 2014-09-11 14:38:16 +0100 | [diff] [blame] | 216 | |
| 217 | if (is_compat_task()) { |
| 218 | current->thread.tp_value = 0; |
| 219 | |
| 220 | /* |
| 221 | * We need to ensure ordering between the shadow state and the |
| 222 | * hardware state, so that we don't corrupt the hardware state |
| 223 | * with a stale shadow state during context switch. |
| 224 | */ |
| 225 | barrier(); |
Mark Rutland | adf7589 | 2016-09-08 13:55:38 +0100 | [diff] [blame] | 226 | write_sysreg(0, tpidrro_el0); |
Will Deacon | eb35bdd | 2014-09-11 14:38:16 +0100 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 230 | void flush_thread(void) |
| 231 | { |
| 232 | fpsimd_flush_thread(); |
Will Deacon | eb35bdd | 2014-09-11 14:38:16 +0100 | [diff] [blame] | 233 | tls_thread_flush(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 234 | flush_ptrace_hw_breakpoint(current); |
| 235 | } |
| 236 | |
| 237 | void release_thread(struct task_struct *dead_task) |
| 238 | { |
| 239 | } |
| 240 | |
| 241 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 242 | { |
Janet Liu | 6eb6c80 | 2015-06-11 12:04:32 +0800 | [diff] [blame] | 243 | if (current->mm) |
| 244 | fpsimd_preserve_current_state(); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 245 | *dst = *src; |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); |
| 250 | |
| 251 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, |
Al Viro | afa86fc | 2012-10-22 22:51:14 -0400 | [diff] [blame] | 252 | unsigned long stk_sz, struct task_struct *p) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 253 | { |
| 254 | struct pt_regs *childregs = task_pt_regs(p); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 255 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 256 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 257 | |
Dave Martin | a392241 | 2017-12-05 14:56:42 +0000 | [diff] [blame] | 258 | /* |
| 259 | * In case p was allocated the same task_struct pointer as some |
| 260 | * other recently-exited task, make sure p is disassociated from |
| 261 | * any cpu that may have run that now-exited task recently. |
| 262 | * Otherwise we could erroneously skip reloading the FPSIMD |
| 263 | * registers for p. |
| 264 | */ |
| 265 | fpsimd_flush_task_state(p); |
| 266 | |
Al Viro | 9ac0800 | 2012-10-21 15:56:52 -0400 | [diff] [blame] | 267 | if (likely(!(p->flags & PF_KTHREAD))) { |
| 268 | *childregs = *current_pt_regs(); |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 269 | childregs->regs[0] = 0; |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 270 | |
| 271 | /* |
| 272 | * Read the current TLS pointer from tpidr_el0 as it may be |
| 273 | * out-of-sync with the saved value. |
| 274 | */ |
Mark Rutland | adf7589 | 2016-09-08 13:55:38 +0100 | [diff] [blame] | 275 | *task_user_tls(p) = read_sysreg(tpidr_el0); |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 276 | |
| 277 | if (stack_start) { |
| 278 | if (is_compat_thread(task_thread_info(p))) |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 279 | childregs->compat_sp = stack_start; |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 280 | else |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 281 | childregs->sp = stack_start; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 282 | } |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 283 | |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 284 | /* |
| 285 | * If a TLS pointer was passed to clone (4th argument), use it |
| 286 | * for the new thread. |
| 287 | */ |
| 288 | if (clone_flags & CLONE_SETTLS) |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 289 | p->thread.tp_value = childregs->regs[3]; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 290 | } else { |
| 291 | memset(childregs, 0, sizeof(struct pt_regs)); |
| 292 | childregs->pstate = PSR_MODE_EL1h; |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 293 | if (IS_ENABLED(CONFIG_ARM64_UAO) && |
Suzuki K Poulose | fe64d7d | 2016-11-08 13:56:20 +0000 | [diff] [blame] | 294 | cpus_have_const_cap(ARM64_HAS_UAO)) |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 295 | childregs->pstate |= PSR_UAO_BIT; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 296 | p->thread.cpu_context.x19 = stack_start; |
| 297 | p->thread.cpu_context.x20 = stk_sz; |
| 298 | } |
| 299 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
| 300 | p->thread.cpu_context.sp = (unsigned long)childregs; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 301 | |
| 302 | ptrace_hw_copy_thread(p); |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static void tls_thread_switch(struct task_struct *next) |
| 308 | { |
Will Deacon | 6e7fb7c | 2018-04-03 12:09:08 +0100 | [diff] [blame] | 309 | unsigned long tpidr; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 310 | |
Mark Rutland | adf7589 | 2016-09-08 13:55:38 +0100 | [diff] [blame] | 311 | tpidr = read_sysreg(tpidr_el0); |
Will Deacon | d00a381 | 2015-05-27 15:39:40 +0100 | [diff] [blame] | 312 | *task_user_tls(current) = tpidr; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 313 | |
Will Deacon | 6e7fb7c | 2018-04-03 12:09:08 +0100 | [diff] [blame] | 314 | if (is_compat_thread(task_thread_info(next))) |
| 315 | write_sysreg(next->thread.tp_value, tpidrro_el0); |
| 316 | else if (!arm64_kernel_unmapped_at_el0()) |
| 317 | write_sysreg(0, tpidrro_el0); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 318 | |
Will Deacon | 6e7fb7c | 2018-04-03 12:09:08 +0100 | [diff] [blame] | 319 | write_sysreg(*task_user_tls(next), tpidr_el0); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 320 | } |
| 321 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 322 | /* Restore the UAO state depending on next's addr_limit */ |
James Morse | d085441 | 2016-10-18 11:27:48 +0100 | [diff] [blame] | 323 | void uao_thread_switch(struct task_struct *next) |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 324 | { |
Catalin Marinas | e950631 | 2016-02-18 15:50:04 +0000 | [diff] [blame] | 325 | if (IS_ENABLED(CONFIG_ARM64_UAO)) { |
| 326 | if (task_thread_info(next)->addr_limit == KERNEL_DS) |
| 327 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); |
| 328 | else |
| 329 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); |
| 330 | } |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 331 | } |
| 332 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 333 | /* |
| 334 | * Thread switching. |
| 335 | */ |
| 336 | struct task_struct *__switch_to(struct task_struct *prev, |
| 337 | struct task_struct *next) |
| 338 | { |
| 339 | struct task_struct *last; |
| 340 | |
| 341 | fpsimd_thread_switch(next); |
| 342 | tls_thread_switch(next); |
| 343 | hw_breakpoint_thread_switch(next); |
Christopher Covington | 3325732 | 2013-04-03 19:01:01 +0100 | [diff] [blame] | 344 | contextidr_thread_switch(next); |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 345 | uao_thread_switch(next); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 346 | |
Catalin Marinas | 5108c67 | 2013-04-24 14:47:02 +0100 | [diff] [blame] | 347 | /* |
| 348 | * Complete any pending TLB or cache maintenance on this CPU in case |
| 349 | * the thread migrates to a different CPU. |
| 350 | */ |
Will Deacon | 98f7685 | 2014-05-02 16:24:10 +0100 | [diff] [blame] | 351 | dsb(ish); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 352 | |
| 353 | /* the actual thread switch */ |
| 354 | last = cpu_switch_to(prev, next); |
| 355 | |
| 356 | return last; |
| 357 | } |
| 358 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 359 | unsigned long get_wchan(struct task_struct *p) |
| 360 | { |
| 361 | struct stackframe frame; |
Konstantin Khlebnikov | 408c365 | 2013-12-05 13:30:10 +0000 | [diff] [blame] | 362 | unsigned long stack_page; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 363 | int count = 0; |
| 364 | if (!p || p == current || p->state == TASK_RUNNING) |
| 365 | return 0; |
| 366 | |
| 367 | frame.fp = thread_saved_fp(p); |
| 368 | frame.sp = thread_saved_sp(p); |
| 369 | frame.pc = thread_saved_pc(p); |
AKASHI Takahiro | 20380bb | 2015-12-15 17:33:41 +0900 | [diff] [blame] | 370 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 371 | frame.graph = p->curr_ret_stack; |
| 372 | #endif |
Konstantin Khlebnikov | 408c365 | 2013-12-05 13:30:10 +0000 | [diff] [blame] | 373 | stack_page = (unsigned long)task_stack_page(p); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 374 | do { |
Konstantin Khlebnikov | 408c365 | 2013-12-05 13:30:10 +0000 | [diff] [blame] | 375 | if (frame.sp < stack_page || |
| 376 | frame.sp >= stack_page + THREAD_SIZE || |
AKASHI Takahiro | fe13f95 | 2015-12-15 17:33:40 +0900 | [diff] [blame] | 377 | unwind_frame(p, &frame)) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 378 | return 0; |
| 379 | if (!in_sched_functions(frame.pc)) |
| 380 | return frame.pc; |
| 381 | } while (count ++ < 16); |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | unsigned long arch_align_stack(unsigned long sp) |
| 386 | { |
| 387 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 388 | sp -= get_random_int() & ~PAGE_MASK; |
| 389 | return sp & ~0xf; |
| 390 | } |
| 391 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 392 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 393 | { |
Kees Cook | 61462c8 | 2016-05-10 10:55:49 -0700 | [diff] [blame] | 394 | if (is_compat_task()) |
Jason Cooper | fa5114c | 2016-10-11 13:54:02 -0700 | [diff] [blame] | 395 | return randomize_page(mm->brk, 0x02000000); |
Kees Cook | 61462c8 | 2016-05-10 10:55:49 -0700 | [diff] [blame] | 396 | else |
Jason Cooper | fa5114c | 2016-10-11 13:54:02 -0700 | [diff] [blame] | 397 | return randomize_page(mm->brk, 0x40000000); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 398 | } |