Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* cpudata.h: Per-cpu parameters. |
| 2 | * |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 3 | * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _SPARC64_CPUDATA_H |
| 7 | #define _SPARC64_CPUDATA_H |
| 8 | |
David S. Miller | d257d5d | 2006-02-06 23:44:37 -0800 | [diff] [blame] | 9 | #include <asm/hypervisor.h> |
David S. Miller | 89a5264 | 2006-02-07 21:15:41 -0800 | [diff] [blame] | 10 | #include <asm/asi.h> |
David S. Miller | d257d5d | 2006-02-06 23:44:37 -0800 | [diff] [blame] | 11 | |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 12 | #ifndef __ASSEMBLY__ |
| 13 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/percpu.h> |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 15 | #include <linux/threads.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | typedef struct { |
| 18 | /* Dcache line 1 */ |
David S. Miller | d7ce78f | 2005-08-29 22:46:43 -0700 | [diff] [blame] | 19 | unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ |
David S. Miller | 777a447 | 2007-02-22 06:24:10 -0800 | [diff] [blame] | 20 | unsigned int __pad0_1; |
| 21 | unsigned int __pad0_2; |
David S. Miller | 1bd0cd7 | 2006-02-21 15:41:01 -0800 | [diff] [blame] | 22 | unsigned int __pad1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | unsigned long clock_tick; /* %tick's per second */ |
| 24 | unsigned long udelay_val; |
| 25 | |
David S. Miller | 3c93646 | 2006-01-31 18:30:27 -0800 | [diff] [blame] | 26 | /* Dcache line 2, rarely used */ |
David S. Miller | 80dc0d6 | 2005-09-26 00:32:17 -0700 | [diff] [blame] | 27 | unsigned int dcache_size; |
| 28 | unsigned int dcache_line_size; |
| 29 | unsigned int icache_size; |
| 30 | unsigned int icache_line_size; |
| 31 | unsigned int ecache_size; |
| 32 | unsigned int ecache_line_size; |
David S. Miller | 80dc0d6 | 2005-09-26 00:32:17 -0700 | [diff] [blame] | 33 | unsigned int __pad3; |
David S. Miller | 05e28f9 | 2006-01-31 18:30:13 -0800 | [diff] [blame] | 34 | unsigned int __pad4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | } cpuinfo_sparc; |
| 36 | |
| 37 | DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data); |
| 38 | #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) |
| 39 | #define local_cpu_data() __get_cpu_var(__cpu_data) |
| 40 | |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 41 | /* Trap handling code needs to get at a few critical values upon |
| 42 | * trap entry and to process TSB misses. These cannot be in the |
| 43 | * per_cpu() area as we really need to lock them into the TLB and |
| 44 | * thus make them part of the main kernel image. As a result we |
| 45 | * try to make this as small as possible. |
| 46 | * |
| 47 | * This is padded out and aligned to 64-bytes to avoid false sharing |
| 48 | * on SMP. |
| 49 | */ |
| 50 | |
| 51 | /* If you modify the size of this structure, please update |
| 52 | * TRAP_BLOCK_SZ_SHIFT below. |
| 53 | */ |
| 54 | struct thread_info; |
| 55 | struct trap_per_cpu { |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 56 | /* D-cache line 1: Basic thread information, cpu and device mondo queues */ |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 57 | struct thread_info *thread; |
| 58 | unsigned long pgd_paddr; |
David S. Miller | 7202c55 | 2006-02-07 22:53:56 -0800 | [diff] [blame] | 59 | unsigned long cpu_mondo_pa; |
| 60 | unsigned long dev_mondo_pa; |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 61 | |
| 62 | /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */ |
David S. Miller | 7202c55 | 2006-02-07 22:53:56 -0800 | [diff] [blame] | 63 | unsigned long resum_mondo_pa; |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 64 | unsigned long resum_kernel_buf_pa; |
David S. Miller | 7202c55 | 2006-02-07 22:53:56 -0800 | [diff] [blame] | 65 | unsigned long nonresum_mondo_pa; |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 66 | unsigned long nonresum_kernel_buf_pa; |
David S. Miller | d257d5d | 2006-02-06 23:44:37 -0800 | [diff] [blame] | 67 | |
David S. Miller | 1d2f1f9 | 2006-02-08 16:41:20 -0800 | [diff] [blame] | 68 | /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */ |
David S. Miller | d257d5d | 2006-02-06 23:44:37 -0800 | [diff] [blame] | 69 | struct hv_fault_status fault_info; |
David S. Miller | 1d2f1f9 | 2006-02-08 16:41:20 -0800 | [diff] [blame] | 70 | |
| 71 | /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */ |
| 72 | unsigned long cpu_mondo_block_pa; |
| 73 | unsigned long cpu_list_pa; |
David S. Miller | dcc1e8d | 2006-03-22 00:49:59 -0800 | [diff] [blame] | 74 | unsigned long tsb_huge; |
| 75 | unsigned long tsb_huge_temp; |
David S. Miller | 1d2f1f9 | 2006-02-08 16:41:20 -0800 | [diff] [blame] | 76 | |
David S. Miller | fd0504c3 | 2006-06-20 01:20:00 -0700 | [diff] [blame] | 77 | /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */ |
| 78 | unsigned int irq_worklist; |
| 79 | unsigned int __pad1; |
| 80 | unsigned long __pad2[3]; |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 81 | } __attribute__((aligned(64))); |
| 82 | extern struct trap_per_cpu trap_block[NR_CPUS]; |
David S. Miller | 72aff53 | 2006-02-17 01:29:17 -0800 | [diff] [blame] | 83 | extern void init_cur_cpu_trap(struct thread_info *); |
David S. Miller | a8b900d | 2006-01-31 18:33:37 -0800 | [diff] [blame] | 84 | extern void setup_tba(void); |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 85 | |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 86 | struct cpuid_patch_entry { |
| 87 | unsigned int addr; |
| 88 | unsigned int cheetah_safari[4]; |
| 89 | unsigned int cheetah_jbus[4]; |
| 90 | unsigned int starfire[4]; |
David S. Miller | d96b815 | 2006-02-04 15:40:53 -0800 | [diff] [blame] | 91 | unsigned int sun4v[4]; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 92 | }; |
| 93 | extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 94 | |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 95 | struct sun4v_1insn_patch_entry { |
David S. Miller | 936f482 | 2006-02-05 21:29:28 -0800 | [diff] [blame] | 96 | unsigned int addr; |
| 97 | unsigned int insn; |
| 98 | }; |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 99 | extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch, |
| 100 | __sun4v_1insn_patch_end; |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 101 | |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 102 | struct sun4v_2insn_patch_entry { |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 103 | unsigned int addr; |
| 104 | unsigned int insns[2]; |
| 105 | }; |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 106 | extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch, |
| 107 | __sun4v_2insn_patch_end; |
| 108 | |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 109 | #endif /* !(__ASSEMBLY__) */ |
| 110 | |
David S. Miller | 7202c55 | 2006-02-07 22:53:56 -0800 | [diff] [blame] | 111 | #define TRAP_PER_CPU_THREAD 0x00 |
| 112 | #define TRAP_PER_CPU_PGD_PADDR 0x08 |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 113 | #define TRAP_PER_CPU_CPU_MONDO_PA 0x10 |
| 114 | #define TRAP_PER_CPU_DEV_MONDO_PA 0x18 |
| 115 | #define TRAP_PER_CPU_RESUM_MONDO_PA 0x20 |
| 116 | #define TRAP_PER_CPU_RESUM_KBUF_PA 0x28 |
| 117 | #define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30 |
| 118 | #define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38 |
David S. Miller | 7202c55 | 2006-02-07 22:53:56 -0800 | [diff] [blame] | 119 | #define TRAP_PER_CPU_FAULT_INFO 0x40 |
David S. Miller | 1d2f1f9 | 2006-02-08 16:41:20 -0800 | [diff] [blame] | 120 | #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0 |
| 121 | #define TRAP_PER_CPU_CPU_LIST_PA 0xc8 |
David S. Miller | dcc1e8d | 2006-03-22 00:49:59 -0800 | [diff] [blame] | 122 | #define TRAP_PER_CPU_TSB_HUGE 0xd0 |
| 123 | #define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8 |
David S. Miller | fd0504c3 | 2006-06-20 01:20:00 -0700 | [diff] [blame] | 124 | #define TRAP_PER_CPU_IRQ_WORKLIST 0xe0 |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 125 | |
David S. Miller | 1d2f1f9 | 2006-02-08 16:41:20 -0800 | [diff] [blame] | 126 | #define TRAP_BLOCK_SZ_SHIFT 8 |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 127 | |
David S. Miller | d96b815 | 2006-02-04 15:40:53 -0800 | [diff] [blame] | 128 | #include <asm/scratchpad.h> |
| 129 | |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 130 | #define __GET_CPUID(REG) \ |
| 131 | /* Spitfire implementation (default). */ \ |
| 132 | 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \ |
| 133 | srlx REG, 17, REG; \ |
| 134 | and REG, 0x1f, REG; \ |
| 135 | nop; \ |
| 136 | .section .cpuid_patch, "ax"; \ |
| 137 | /* Instruction location. */ \ |
| 138 | .word 661b; \ |
| 139 | /* Cheetah Safari implementation. */ \ |
| 140 | ldxa [%g0] ASI_SAFARI_CONFIG, REG; \ |
| 141 | srlx REG, 17, REG; \ |
| 142 | and REG, 0x3ff, REG; \ |
| 143 | nop; \ |
| 144 | /* Cheetah JBUS implementation. */ \ |
| 145 | ldxa [%g0] ASI_JBUS_CONFIG, REG; \ |
| 146 | srlx REG, 17, REG; \ |
| 147 | and REG, 0x1f, REG; \ |
| 148 | nop; \ |
| 149 | /* Starfire implementation. */ \ |
| 150 | sethi %hi(0x1fff40000d0 >> 9), REG; \ |
| 151 | sllx REG, 9, REG; \ |
| 152 | or REG, 0xd0, REG; \ |
| 153 | lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\ |
David S. Miller | d96b815 | 2006-02-04 15:40:53 -0800 | [diff] [blame] | 154 | /* sun4v implementation. */ \ |
| 155 | mov SCRATCHPAD_CPUID, REG; \ |
David S. Miller | d96b815 | 2006-02-04 15:40:53 -0800 | [diff] [blame] | 156 | ldxa [REG] ASI_SCRATCHPAD, REG; \ |
| 157 | nop; \ |
David S. Miller | 89a5264 | 2006-02-07 21:15:41 -0800 | [diff] [blame] | 158 | nop; \ |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 159 | .previous; |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 160 | |
David S. Miller | ebd8c56 | 2006-02-17 08:38:06 -0800 | [diff] [blame] | 161 | #ifdef CONFIG_SMP |
| 162 | |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 163 | #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 164 | __GET_CPUID(TMP) \ |
| 165 | sethi %hi(trap_block), DEST; \ |
| 166 | sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ |
| 167 | or DEST, %lo(trap_block), DEST; \ |
| 168 | add DEST, TMP, DEST; \ |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 169 | |
| 170 | /* Clobbers TMP, current address space PGD phys address into DEST. */ |
| 171 | #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ |
| 172 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 173 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 174 | |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 175 | /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ |
| 176 | #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \ |
David S. Miller | fd0504c3 | 2006-06-20 01:20:00 -0700 | [diff] [blame] | 177 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
| 178 | add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST; |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 179 | |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 180 | /* Clobbers TMP, loads DEST with current thread info pointer. */ |
| 181 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 182 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
| 183 | ldx [DEST + TRAP_PER_CPU_THREAD], DEST; |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 184 | |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 185 | /* Given the current thread info pointer in THR, load the per-cpu |
| 186 | * area base of the current processor into DEST. REG1, REG2, and REG3 are |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 187 | * clobbered. |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 188 | * |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 189 | * You absolutely cannot use DEST as a temporary in this code. The |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 190 | * reason is that traps can happen during execution, and return from |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 191 | * trap will load the fully resolved DEST per-cpu base. This can corrupt |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 192 | * the calculations done by the macro mid-stream. |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 193 | */ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 194 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ |
| 195 | ldub [THR + TI_CPU], REG1; \ |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 196 | sethi %hi(__per_cpu_shift), REG3; \ |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 197 | sethi %hi(__per_cpu_base), REG2; \ |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 198 | ldx [REG3 + %lo(__per_cpu_shift)], REG3; \ |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 199 | ldx [REG2 + %lo(__per_cpu_base)], REG2; \ |
David S. Miller | 86b8186 | 2006-01-31 18:34:51 -0800 | [diff] [blame] | 200 | sllx REG1, REG3, REG3; \ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 201 | add REG3, REG2, DEST; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 202 | |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 203 | #else |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 204 | |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 205 | #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
| 206 | sethi %hi(trap_block), DEST; \ |
| 207 | or DEST, %lo(trap_block), DEST; \ |
David S. Miller | 5b0c057 | 2006-02-08 02:53:50 -0800 | [diff] [blame] | 208 | |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 209 | /* Uniprocessor versions, we know the cpuid is zero. */ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 210 | #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 211 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 212 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 213 | |
David S. Miller | fd0504c3 | 2006-06-20 01:20:00 -0700 | [diff] [blame] | 214 | /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 215 | #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \ |
David S. Miller | fd0504c3 | 2006-06-20 01:20:00 -0700 | [diff] [blame] | 216 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
| 217 | add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 218 | |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 219 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
David S. Miller | 12eaa32 | 2006-02-10 15:39:51 -0800 | [diff] [blame] | 220 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
| 221 | ldx [DEST + TRAP_PER_CPU_THREAD], DEST; |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 222 | |
David S. Miller | ffe483d | 2006-02-02 21:55:10 -0800 | [diff] [blame] | 223 | /* No per-cpu areas on uniprocessor, so no need to load DEST. */ |
| 224 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) |
David S. Miller | 92704a1 | 2006-02-26 23:27:19 -0800 | [diff] [blame] | 225 | |
| 226 | #endif /* !(CONFIG_SMP) */ |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 227 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | #endif /* _SPARC64_CPUDATA_H */ |