blob: a200fa16beae406757095f0f7090999b7a596b9c [file] [log] [blame]
Alan Ott3731a332012-09-02 15:44:13 +00001/*
2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
3 *
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
5 * Signal 11 Software
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Alan Ott3731a332012-09-02 15:44:13 +000016 */
17
18#include <linux/spi/spi.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
Alexander Aring4ca24ac2014-10-25 09:41:04 +020021#include <linux/ieee802154.h>
Alexander Aring5ad60d32014-10-25 09:41:02 +020022#include <net/cfg802154.h>
Alan Ott3731a332012-09-02 15:44:13 +000023#include <net/mac802154.h>
24
25/* MRF24J40 Short Address Registers */
26#define REG_RXMCR 0x00 /* Receive MAC control */
27#define REG_PANIDL 0x01 /* PAN ID (low) */
28#define REG_PANIDH 0x02 /* PAN ID (high) */
29#define REG_SADRL 0x03 /* Short address (low) */
30#define REG_SADRH 0x04 /* Short address (high) */
31#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
32#define REG_TXMCR 0x11 /* Transmit MAC control */
33#define REG_PACON0 0x16 /* Power Amplifier Control */
34#define REG_PACON1 0x17 /* Power Amplifier Control */
35#define REG_PACON2 0x18 /* Power Amplifier Control */
36#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
37#define REG_TXSTAT 0x24 /* TX MAC Status Register */
38#define REG_SOFTRST 0x2A /* Soft Reset */
39#define REG_TXSTBL 0x2E /* TX Stabilization */
40#define REG_INTSTAT 0x31 /* Interrupt Status */
41#define REG_INTCON 0x32 /* Interrupt Control */
Simon Vincentdb9e0ee2014-10-06 10:39:45 +010042#define REG_GPIO 0x33 /* GPIO */
43#define REG_TRISGPIO 0x34 /* GPIO direction */
Alan Ott3731a332012-09-02 15:44:13 +000044#define REG_RFCTL 0x36 /* RF Control Mode Register */
45#define REG_BBREG1 0x39 /* Baseband Registers */
46#define REG_BBREG2 0x3A /* */
47#define REG_BBREG6 0x3E /* */
48#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
49
50/* MRF24J40 Long Address Registers */
51#define REG_RFCON0 0x200 /* RF Control Registers */
52#define REG_RFCON1 0x201
53#define REG_RFCON2 0x202
54#define REG_RFCON3 0x203
55#define REG_RFCON5 0x205
56#define REG_RFCON6 0x206
57#define REG_RFCON7 0x207
58#define REG_RFCON8 0x208
59#define REG_RSSI 0x210
60#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
61#define REG_SLPCON1 0x220
62#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
63#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
Simon Vincentdb9e0ee2014-10-06 10:39:45 +010064#define REG_TESTMODE 0x22F /* Test mode */
Alan Ott3731a332012-09-02 15:44:13 +000065#define REG_RX_FIFO 0x300 /* Receive FIFO */
66
67/* Device configuration: Only channels 11-26 on page 0 are supported. */
68#define MRF24J40_CHAN_MIN 11
69#define MRF24J40_CHAN_MAX 26
70#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
71 - ((u32)1 << MRF24J40_CHAN_MIN))
72
73#define TX_FIFO_SIZE 128 /* From datasheet */
74#define RX_FIFO_SIZE 144 /* From datasheet */
75#define SET_CHANNEL_DELAY_US 192 /* From datasheet */
76
Simon Vincentdb9e0ee2014-10-06 10:39:45 +010077enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
78
Alan Ott3731a332012-09-02 15:44:13 +000079/* Device Private Data */
80struct mrf24j40 {
81 struct spi_device *spi;
Alexander Aring5a504392014-10-25 17:16:34 +020082 struct ieee802154_hw *hw;
Alan Ott3731a332012-09-02 15:44:13 +000083
84 struct mutex buffer_mutex; /* only used to protect buf */
85 struct completion tx_complete;
Alan Ott3731a332012-09-02 15:44:13 +000086 u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
87};
88
89/* Read/Write SPI Commands for Short and Long Address registers. */
90#define MRF24J40_READSHORT(reg) ((reg) << 1)
91#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
92#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
93#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
94
Alan Ottcf82dab2013-03-18 12:06:42 +000095/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
96#define MAX_SPI_SPEED_HZ 10000000
Alan Ott3731a332012-09-02 15:44:13 +000097
98#define printdev(X) (&X->spi->dev)
99
100static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
101{
102 int ret;
103 struct spi_message msg;
104 struct spi_transfer xfer = {
105 .len = 2,
106 .tx_buf = devrec->buf,
107 .rx_buf = devrec->buf,
108 };
109
110 spi_message_init(&msg);
111 spi_message_add_tail(&xfer, &msg);
112
113 mutex_lock(&devrec->buffer_mutex);
114 devrec->buf[0] = MRF24J40_WRITESHORT(reg);
115 devrec->buf[1] = value;
116
117 ret = spi_sync(devrec->spi, &msg);
118 if (ret)
119 dev_err(printdev(devrec),
120 "SPI write Failed for short register 0x%hhx\n", reg);
121
122 mutex_unlock(&devrec->buffer_mutex);
123 return ret;
124}
125
126static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
127{
128 int ret = -1;
129 struct spi_message msg;
130 struct spi_transfer xfer = {
131 .len = 2,
132 .tx_buf = devrec->buf,
133 .rx_buf = devrec->buf,
134 };
135
136 spi_message_init(&msg);
137 spi_message_add_tail(&xfer, &msg);
138
139 mutex_lock(&devrec->buffer_mutex);
140 devrec->buf[0] = MRF24J40_READSHORT(reg);
141 devrec->buf[1] = 0;
142
143 ret = spi_sync(devrec->spi, &msg);
144 if (ret)
145 dev_err(printdev(devrec),
146 "SPI read Failed for short register 0x%hhx\n", reg);
147 else
148 *val = devrec->buf[1];
149
150 mutex_unlock(&devrec->buffer_mutex);
151 return ret;
152}
153
154static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
155{
156 int ret;
157 u16 cmd;
158 struct spi_message msg;
159 struct spi_transfer xfer = {
160 .len = 3,
161 .tx_buf = devrec->buf,
162 .rx_buf = devrec->buf,
163 };
164
165 spi_message_init(&msg);
166 spi_message_add_tail(&xfer, &msg);
167
168 cmd = MRF24J40_READLONG(reg);
169 mutex_lock(&devrec->buffer_mutex);
170 devrec->buf[0] = cmd >> 8 & 0xff;
171 devrec->buf[1] = cmd & 0xff;
172 devrec->buf[2] = 0;
173
174 ret = spi_sync(devrec->spi, &msg);
175 if (ret)
176 dev_err(printdev(devrec),
177 "SPI read Failed for long register 0x%hx\n", reg);
178 else
179 *value = devrec->buf[2];
180
181 mutex_unlock(&devrec->buffer_mutex);
182 return ret;
183}
184
185static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
186{
187 int ret;
188 u16 cmd;
189 struct spi_message msg;
190 struct spi_transfer xfer = {
191 .len = 3,
192 .tx_buf = devrec->buf,
193 .rx_buf = devrec->buf,
194 };
195
196 spi_message_init(&msg);
197 spi_message_add_tail(&xfer, &msg);
198
199 cmd = MRF24J40_WRITELONG(reg);
200 mutex_lock(&devrec->buffer_mutex);
201 devrec->buf[0] = cmd >> 8 & 0xff;
202 devrec->buf[1] = cmd & 0xff;
203 devrec->buf[2] = val;
204
205 ret = spi_sync(devrec->spi, &msg);
206 if (ret)
207 dev_err(printdev(devrec),
208 "SPI write Failed for long register 0x%hx\n", reg);
209
210 mutex_unlock(&devrec->buffer_mutex);
211 return ret;
212}
213
214/* This function relies on an undocumented write method. Once a write command
215 and address is set, as many bytes of data as desired can be clocked into
216 the device. The datasheet only shows setting one byte at a time. */
217static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
218 const u8 *data, size_t length)
219{
220 int ret;
221 u16 cmd;
222 u8 lengths[2];
223 struct spi_message msg;
224 struct spi_transfer addr_xfer = {
225 .len = 2,
226 .tx_buf = devrec->buf,
227 };
228 struct spi_transfer lengths_xfer = {
229 .len = 2,
230 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
231 };
232 struct spi_transfer data_xfer = {
233 .len = length,
234 .tx_buf = data,
235 };
236
237 /* Range check the length. 2 bytes are used for the length fields.*/
238 if (length > TX_FIFO_SIZE-2) {
239 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
240 length = TX_FIFO_SIZE-2;
241 }
242
243 spi_message_init(&msg);
244 spi_message_add_tail(&addr_xfer, &msg);
245 spi_message_add_tail(&lengths_xfer, &msg);
246 spi_message_add_tail(&data_xfer, &msg);
247
248 cmd = MRF24J40_WRITELONG(reg);
249 mutex_lock(&devrec->buffer_mutex);
250 devrec->buf[0] = cmd >> 8 & 0xff;
251 devrec->buf[1] = cmd & 0xff;
252 lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
253 lengths[1] = length; /* Total length */
254
255 ret = spi_sync(devrec->spi, &msg);
256 if (ret)
257 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
258
259 mutex_unlock(&devrec->buffer_mutex);
260 return ret;
261}
262
263static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
264 u8 *data, u8 *len, u8 *lqi)
265{
266 u8 rx_len;
267 u8 addr[2];
268 u8 lqi_rssi[2];
269 u16 cmd;
270 int ret;
271 struct spi_message msg;
272 struct spi_transfer addr_xfer = {
273 .len = 2,
274 .tx_buf = &addr,
275 };
276 struct spi_transfer data_xfer = {
277 .len = 0x0, /* set below */
278 .rx_buf = data,
279 };
280 struct spi_transfer status_xfer = {
281 .len = 2,
282 .rx_buf = &lqi_rssi,
283 };
284
285 /* Get the length of the data in the RX FIFO. The length in this
286 * register exclues the 1-byte length field at the beginning. */
287 ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
288 if (ret)
289 goto out;
290
291 /* Range check the RX FIFO length, accounting for the one-byte
292 * length field at the begining. */
293 if (rx_len > RX_FIFO_SIZE-1) {
294 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
295 rx_len = RX_FIFO_SIZE-1;
296 }
297
298 if (rx_len > *len) {
299 /* Passed in buffer wasn't big enough. Should never happen. */
300 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
301 rx_len = *len;
302 }
303
304 /* Set up the commands to read the data. */
305 cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
306 addr[0] = cmd >> 8 & 0xff;
307 addr[1] = cmd & 0xff;
308 data_xfer.len = rx_len;
309
310 spi_message_init(&msg);
311 spi_message_add_tail(&addr_xfer, &msg);
312 spi_message_add_tail(&data_xfer, &msg);
313 spi_message_add_tail(&status_xfer, &msg);
314
315 ret = spi_sync(devrec->spi, &msg);
316 if (ret) {
317 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
318 goto out;
319 }
320
321 *lqi = lqi_rssi[0];
322 *len = rx_len;
323
324#ifdef DEBUG
325 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
326 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
Varka Bhadramca079ad2014-09-24 12:21:32 +0200327 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
328 lqi_rssi[0], lqi_rssi[1]);
Alan Ott3731a332012-09-02 15:44:13 +0000329#endif
330
331out:
332 return ret;
333}
334
Alexander Aring5a504392014-10-25 17:16:34 +0200335static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
Alan Ott3731a332012-09-02 15:44:13 +0000336{
Alexander Aring5a504392014-10-25 17:16:34 +0200337 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000338 u8 val;
339 int ret = 0;
340
341 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
342
343 ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
344 if (ret)
345 goto err;
346
Wolfram Sang16735d02013-11-14 14:32:02 -0800347 reinit_completion(&devrec->tx_complete);
Alan Ott9757f1d2013-10-05 23:52:22 -0400348
Alan Ott3731a332012-09-02 15:44:13 +0000349 /* Set TXNTRIG bit of TXNCON to send packet */
350 ret = read_short_reg(devrec, REG_TXNCON, &val);
351 if (ret)
352 goto err;
353 val |= 0x1;
Alan Ottcbde8122013-04-05 10:34:51 +0000354 /* Set TXNACKREQ if the ACK bit is set in the packet. */
355 if (skb->data[0] & IEEE802154_FC_ACK_REQ)
356 val |= 0x4;
Alan Ott3731a332012-09-02 15:44:13 +0000357 write_short_reg(devrec, REG_TXNCON, val);
358
Alan Ott3731a332012-09-02 15:44:13 +0000359 /* Wait for the device to send the TX complete interrupt. */
360 ret = wait_for_completion_interruptible_timeout(
361 &devrec->tx_complete,
362 5 * HZ);
363 if (ret == -ERESTARTSYS)
364 goto err;
365 if (ret == 0) {
Alan Ott7a1c2312013-03-18 12:06:41 +0000366 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
Alan Ott3731a332012-09-02 15:44:13 +0000367 ret = -ETIMEDOUT;
368 goto err;
369 }
370
371 /* Check for send error from the device. */
372 ret = read_short_reg(devrec, REG_TXSTAT, &val);
373 if (ret)
374 goto err;
375 if (val & 0x1) {
Alan Ottcbde8122013-04-05 10:34:51 +0000376 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
Alan Ott3731a332012-09-02 15:44:13 +0000377 ret = -ECOMM; /* TODO: Better error code ? */
378 } else
379 dev_dbg(printdev(devrec), "Packet Sent\n");
380
381err:
382
383 return ret;
384}
385
Alexander Aring5a504392014-10-25 17:16:34 +0200386static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
Alan Ott3731a332012-09-02 15:44:13 +0000387{
388 /* TODO: */
Varka Bhadramca079ad2014-09-24 12:21:32 +0200389 pr_warn("mrf24j40: ed not implemented\n");
Alan Ott3731a332012-09-02 15:44:13 +0000390 *level = 0;
391 return 0;
392}
393
Alexander Aring5a504392014-10-25 17:16:34 +0200394static int mrf24j40_start(struct ieee802154_hw *hw)
Alan Ott3731a332012-09-02 15:44:13 +0000395{
Alexander Aring5a504392014-10-25 17:16:34 +0200396 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000397 u8 val;
398 int ret;
399
400 dev_dbg(printdev(devrec), "start\n");
401
402 ret = read_short_reg(devrec, REG_INTCON, &val);
403 if (ret)
404 return ret;
405 val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
406 write_short_reg(devrec, REG_INTCON, val);
407
408 return 0;
409}
410
Alexander Aring5a504392014-10-25 17:16:34 +0200411static void mrf24j40_stop(struct ieee802154_hw *hw)
Alan Ott3731a332012-09-02 15:44:13 +0000412{
Alexander Aring5a504392014-10-25 17:16:34 +0200413 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000414 u8 val;
415 int ret;
Varka Bhadram529160d2014-09-24 12:21:30 +0200416
Alan Ott3731a332012-09-02 15:44:13 +0000417 dev_dbg(printdev(devrec), "stop\n");
418
419 ret = read_short_reg(devrec, REG_INTCON, &val);
420 if (ret)
421 return;
422 val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
423 write_short_reg(devrec, REG_INTCON, val);
Alan Ott3731a332012-09-02 15:44:13 +0000424}
425
Alexander Aringe37d2ec2014-10-28 18:21:19 +0100426static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
Alan Ott3731a332012-09-02 15:44:13 +0000427{
Alexander Aring5a504392014-10-25 17:16:34 +0200428 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000429 u8 val;
430 int ret;
431
432 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
433
434 WARN_ON(page != 0);
435 WARN_ON(channel < MRF24J40_CHAN_MIN);
436 WARN_ON(channel > MRF24J40_CHAN_MAX);
437
438 /* Set Channel TODO */
439 val = (channel-11) << 4 | 0x03;
440 write_long_reg(devrec, REG_RFCON0, val);
441
442 /* RF Reset */
443 ret = read_short_reg(devrec, REG_RFCTL, &val);
444 if (ret)
445 return ret;
446 val |= 0x04;
447 write_short_reg(devrec, REG_RFCTL, val);
448 val &= ~0x04;
449 write_short_reg(devrec, REG_RFCTL, val);
450
451 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
452
453 return 0;
454}
455
Alexander Aring5a504392014-10-25 17:16:34 +0200456static int mrf24j40_filter(struct ieee802154_hw *hw,
Alan Ott3731a332012-09-02 15:44:13 +0000457 struct ieee802154_hw_addr_filt *filt,
458 unsigned long changed)
459{
Alexander Aring5a504392014-10-25 17:16:34 +0200460 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000461
462 dev_dbg(printdev(devrec), "filter\n");
463
Alexander Aring57205c12014-10-25 05:25:09 +0200464 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000465 /* Short Addr */
466 u8 addrh, addrl;
Varka Bhadram529160d2014-09-24 12:21:30 +0200467
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100468 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
469 addrl = le16_to_cpu(filt->short_addr) & 0xff;
Alan Ott3731a332012-09-02 15:44:13 +0000470
471 write_short_reg(devrec, REG_SADRH, addrh);
472 write_short_reg(devrec, REG_SADRL, addrl);
473 dev_dbg(printdev(devrec),
474 "Set short addr to %04hx\n", filt->short_addr);
475 }
476
Alexander Aring57205c12014-10-25 05:25:09 +0200477 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000478 /* Device Address */
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100479 u8 i, addr[8];
480
481 memcpy(addr, &filt->ieee_addr, 8);
Alan Ott3731a332012-09-02 15:44:13 +0000482 for (i = 0; i < 8; i++)
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100483 write_short_reg(devrec, REG_EADR0 + i, addr[i]);
Alan Ott3731a332012-09-02 15:44:13 +0000484
485#ifdef DEBUG
Varka Bhadramca079ad2014-09-24 12:21:32 +0200486 pr_debug("Set long addr to: ");
Alan Ott3731a332012-09-02 15:44:13 +0000487 for (i = 0; i < 8; i++)
Varka Bhadramca079ad2014-09-24 12:21:32 +0200488 pr_debug("%02hhx ", addr[7 - i]);
489 pr_debug("\n");
Alan Ott3731a332012-09-02 15:44:13 +0000490#endif
491 }
492
Alexander Aring57205c12014-10-25 05:25:09 +0200493 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000494 /* PAN ID */
495 u8 panidl, panidh;
Varka Bhadram529160d2014-09-24 12:21:30 +0200496
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100497 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
498 panidl = le16_to_cpu(filt->pan_id) & 0xff;
Alan Ott3731a332012-09-02 15:44:13 +0000499 write_short_reg(devrec, REG_PANIDH, panidh);
500 write_short_reg(devrec, REG_PANIDL, panidl);
501
502 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
503 }
504
Alexander Aring57205c12014-10-25 05:25:09 +0200505 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000506 /* Pan Coordinator */
507 u8 val;
508 int ret;
509
510 ret = read_short_reg(devrec, REG_RXMCR, &val);
511 if (ret)
512 return ret;
513 if (filt->pan_coord)
514 val |= 0x8;
515 else
516 val &= ~0x8;
517 write_short_reg(devrec, REG_RXMCR, val);
518
519 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
520 * REG_ORDER is maintained as default (no beacon/superframe).
521 */
522
523 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
524 filt->pan_coord ? "on" : "off");
525 }
526
527 return 0;
528}
529
530static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
531{
532 u8 len = RX_FIFO_SIZE;
533 u8 lqi = 0;
534 u8 val;
535 int ret = 0;
536 struct sk_buff *skb;
537
538 /* Turn off reception of packets off the air. This prevents the
539 * device from overwriting the buffer while we're reading it. */
540 ret = read_short_reg(devrec, REG_BBREG1, &val);
541 if (ret)
542 goto out;
543 val |= 4; /* SET RXDECINV */
544 write_short_reg(devrec, REG_BBREG1, val);
545
Alexander Aring61a22812014-10-27 17:13:29 +0100546 skb = dev_alloc_skb(len);
Alan Ott3731a332012-09-02 15:44:13 +0000547 if (!skb) {
548 ret = -ENOMEM;
549 goto out;
550 }
551
552 ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
553 if (ret < 0) {
554 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
555 kfree_skb(skb);
556 ret = -EINVAL;
557 goto out;
558 }
559
560 /* Cut off the checksum */
561 skb_trim(skb, len-2);
562
563 /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
564 * also from a workqueue). I think irqsafe is not necessary here.
565 * Can someone confirm? */
Alexander Aring5a504392014-10-25 17:16:34 +0200566 ieee802154_rx_irqsafe(devrec->hw, skb, lqi);
Alan Ott3731a332012-09-02 15:44:13 +0000567
568 dev_dbg(printdev(devrec), "RX Handled\n");
569
570out:
571 /* Turn back on reception of packets off the air. */
572 ret = read_short_reg(devrec, REG_BBREG1, &val);
573 if (ret)
574 return ret;
575 val &= ~0x4; /* Clear RXDECINV */
576 write_short_reg(devrec, REG_BBREG1, val);
577
578 return ret;
579}
580
Alexander Aring16301862014-10-28 18:21:18 +0100581static const struct ieee802154_ops mrf24j40_ops = {
Alan Ott3731a332012-09-02 15:44:13 +0000582 .owner = THIS_MODULE,
Alexander Aringed0a5dc2014-10-26 09:37:08 +0100583 .xmit_sync = mrf24j40_tx,
Alan Ott3731a332012-09-02 15:44:13 +0000584 .ed = mrf24j40_ed,
585 .start = mrf24j40_start,
586 .stop = mrf24j40_stop,
587 .set_channel = mrf24j40_set_channel,
588 .set_hw_addr_filt = mrf24j40_filter,
589};
590
591static irqreturn_t mrf24j40_isr(int irq, void *data)
592{
593 struct mrf24j40 *devrec = data;
Alan Ott3731a332012-09-02 15:44:13 +0000594 u8 intstat;
595 int ret;
596
597 /* Read the interrupt status */
598 ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
599 if (ret)
600 goto out;
601
602 /* Check for TX complete */
603 if (intstat & 0x1)
604 complete(&devrec->tx_complete);
605
606 /* Check for Rx */
607 if (intstat & 0x8)
608 mrf24j40_handle_rx(devrec);
609
610out:
Alan Ott4a4e1da2013-10-05 23:52:23 -0400611 return IRQ_HANDLED;
Alan Ott3731a332012-09-02 15:44:13 +0000612}
613
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530614static int mrf24j40_hw_init(struct mrf24j40 *devrec)
615{
616 int ret;
617 u8 val;
618
619 /* Initialize the device.
620 From datasheet section 3.2: Initialization. */
621 ret = write_short_reg(devrec, REG_SOFTRST, 0x07);
622 if (ret)
623 goto err_ret;
624
625 ret = write_short_reg(devrec, REG_PACON2, 0x98);
626 if (ret)
627 goto err_ret;
628
629 ret = write_short_reg(devrec, REG_TXSTBL, 0x95);
630 if (ret)
631 goto err_ret;
632
633 ret = write_long_reg(devrec, REG_RFCON0, 0x03);
634 if (ret)
635 goto err_ret;
636
637 ret = write_long_reg(devrec, REG_RFCON1, 0x01);
638 if (ret)
639 goto err_ret;
640
641 ret = write_long_reg(devrec, REG_RFCON2, 0x80);
642 if (ret)
643 goto err_ret;
644
645 ret = write_long_reg(devrec, REG_RFCON6, 0x90);
646 if (ret)
647 goto err_ret;
648
649 ret = write_long_reg(devrec, REG_RFCON7, 0x80);
650 if (ret)
651 goto err_ret;
652
653 ret = write_long_reg(devrec, REG_RFCON8, 0x10);
654 if (ret)
655 goto err_ret;
656
657 ret = write_long_reg(devrec, REG_SLPCON1, 0x21);
658 if (ret)
659 goto err_ret;
660
661 ret = write_short_reg(devrec, REG_BBREG2, 0x80);
662 if (ret)
663 goto err_ret;
664
665 ret = write_short_reg(devrec, REG_CCAEDTH, 0x60);
666 if (ret)
667 goto err_ret;
668
669 ret = write_short_reg(devrec, REG_BBREG6, 0x40);
670 if (ret)
671 goto err_ret;
672
673 ret = write_short_reg(devrec, REG_RFCTL, 0x04);
674 if (ret)
675 goto err_ret;
676
677 ret = write_short_reg(devrec, REG_RFCTL, 0x0);
678 if (ret)
679 goto err_ret;
680
681 udelay(192);
682
683 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
684 ret = read_short_reg(devrec, REG_RXMCR, &val);
685 if (ret)
686 goto err_ret;
687
688 val &= ~0x3; /* Clear RX mode (normal) */
689
690 ret = write_short_reg(devrec, REG_RXMCR, val);
691 if (ret)
692 goto err_ret;
693
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100694 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
695 /* Enable external amplifier.
696 * From MRF24J40MC datasheet section 1.3: Operation.
697 */
698 read_long_reg(devrec, REG_TESTMODE, &val);
699 val |= 0x7; /* Configure GPIO 0-2 to control amplifier */
700 write_long_reg(devrec, REG_TESTMODE, val);
701
702 read_short_reg(devrec, REG_TRISGPIO, &val);
703 val |= 0x8; /* Set GPIO3 as output. */
704 write_short_reg(devrec, REG_TRISGPIO, val);
705
706 read_short_reg(devrec, REG_GPIO, &val);
707 val |= 0x8; /* Set GPIO3 HIGH to enable U5 voltage regulator */
708 write_short_reg(devrec, REG_GPIO, val);
709
710 /* Reduce TX pwr to meet FCC requirements.
711 * From MRF24J40MC datasheet section 3.1.1
712 */
713 write_long_reg(devrec, REG_RFCON3, 0x28);
714 }
715
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530716 return 0;
717
718err_ret:
719 return ret;
720}
721
Bill Pembertonbb1f4602012-12-03 09:24:12 -0500722static int mrf24j40_probe(struct spi_device *spi)
Alan Ott3731a332012-09-02 15:44:13 +0000723{
724 int ret = -ENOMEM;
Alan Ott3731a332012-09-02 15:44:13 +0000725 struct mrf24j40 *devrec;
726
Varka Bhadramca079ad2014-09-24 12:21:32 +0200727 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
Alan Ott3731a332012-09-02 15:44:13 +0000728
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530729 devrec = devm_kzalloc(&spi->dev, sizeof(struct mrf24j40), GFP_KERNEL);
Alan Ott3731a332012-09-02 15:44:13 +0000730 if (!devrec)
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530731 goto err_ret;
732 devrec->buf = devm_kzalloc(&spi->dev, 3, GFP_KERNEL);
Alan Ott3731a332012-09-02 15:44:13 +0000733 if (!devrec->buf)
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530734 goto err_ret;
Alan Ott3731a332012-09-02 15:44:13 +0000735
736 spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
737 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
738 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
739
740 mutex_init(&devrec->buffer_mutex);
741 init_completion(&devrec->tx_complete);
Alan Ott3731a332012-09-02 15:44:13 +0000742 devrec->spi = spi;
Jingoo Han4fa0a0e2013-04-05 20:34:18 +0000743 spi_set_drvdata(spi, devrec);
Alan Ott3731a332012-09-02 15:44:13 +0000744
745 /* Register with the 802154 subsystem */
746
Alexander Aring5a504392014-10-25 17:16:34 +0200747 devrec->hw = ieee802154_alloc_hw(0, &mrf24j40_ops);
748 if (!devrec->hw)
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530749 goto err_ret;
Alan Ott3731a332012-09-02 15:44:13 +0000750
Alexander Aring5a504392014-10-25 17:16:34 +0200751 devrec->hw->priv = devrec;
752 devrec->hw->parent = &devrec->spi->dev;
753 devrec->hw->phy->channels_supported[0] = CHANNEL_MASK;
Alexander Aringc8fc84e2014-10-29 21:34:31 +0100754 devrec->hw->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK |
755 IEEE802154_HW_AFILT;
Alan Ott3731a332012-09-02 15:44:13 +0000756
757 dev_dbg(printdev(devrec), "registered mrf24j40\n");
Alexander Aring5a504392014-10-25 17:16:34 +0200758 ret = ieee802154_register_hw(devrec->hw);
Alan Ott3731a332012-09-02 15:44:13 +0000759 if (ret)
760 goto err_register_device;
761
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530762 ret = mrf24j40_hw_init(devrec);
Alan Ott3731a332012-09-02 15:44:13 +0000763 if (ret)
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530764 goto err_hw_init;
Alan Ott3731a332012-09-02 15:44:13 +0000765
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530766 ret = devm_request_threaded_irq(&spi->dev,
767 spi->irq,
768 NULL,
769 mrf24j40_isr,
770 IRQF_TRIGGER_LOW|IRQF_ONESHOT,
771 dev_name(&spi->dev),
772 devrec);
Alan Ott3731a332012-09-02 15:44:13 +0000773
774 if (ret) {
775 dev_err(printdev(devrec), "Unable to get IRQ");
776 goto err_irq;
777 }
778
779 return 0;
780
781err_irq:
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530782err_hw_init:
Alexander Aring5a504392014-10-25 17:16:34 +0200783 ieee802154_unregister_hw(devrec->hw);
Alan Ott3731a332012-09-02 15:44:13 +0000784err_register_device:
Alexander Aring5a504392014-10-25 17:16:34 +0200785 ieee802154_free_hw(devrec->hw);
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530786err_ret:
Alan Ott3731a332012-09-02 15:44:13 +0000787 return ret;
788}
789
Bill Pembertonbb1f4602012-12-03 09:24:12 -0500790static int mrf24j40_remove(struct spi_device *spi)
Alan Ott3731a332012-09-02 15:44:13 +0000791{
Jingoo Han4fa0a0e2013-04-05 20:34:18 +0000792 struct mrf24j40 *devrec = spi_get_drvdata(spi);
Alan Ott3731a332012-09-02 15:44:13 +0000793
794 dev_dbg(printdev(devrec), "remove\n");
795
Alexander Aring5a504392014-10-25 17:16:34 +0200796 ieee802154_unregister_hw(devrec->hw);
797 ieee802154_free_hw(devrec->hw);
Alan Ott3731a332012-09-02 15:44:13 +0000798 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
799 * complete? */
800
Alan Ott3731a332012-09-02 15:44:13 +0000801 return 0;
802}
803
804static const struct spi_device_id mrf24j40_ids[] = {
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100805 { "mrf24j40", MRF24J40 },
806 { "mrf24j40ma", MRF24J40MA },
807 { "mrf24j40mc", MRF24J40MC },
Alan Ott3731a332012-09-02 15:44:13 +0000808 { },
809};
810MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
811
812static struct spi_driver mrf24j40_driver = {
813 .driver = {
814 .name = "mrf24j40",
815 .bus = &spi_bus_type,
816 .owner = THIS_MODULE,
817 },
818 .id_table = mrf24j40_ids,
819 .probe = mrf24j40_probe,
Bill Pembertonbb1f4602012-12-03 09:24:12 -0500820 .remove = mrf24j40_remove,
Alan Ott3731a332012-09-02 15:44:13 +0000821};
822
Wei Yongjun3d4a1312013-04-08 20:34:44 +0000823module_spi_driver(mrf24j40_driver);
Alan Ott3731a332012-09-02 15:44:13 +0000824
825MODULE_LICENSE("GPL");
826MODULE_AUTHOR("Alan Ott");
827MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");