Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2002 Andi Kleen, SuSE Labs. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Thanks to Ben LaHaise for precious feedback. |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 4 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | #include <linux/highmem.h> |
Ingo Molnar | 8192206 | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 6 | #include <linux/bootmem.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | #include <linux/module.h> |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 8 | #include <linux/sched.h> |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 9 | #include <linux/mm.h> |
Thomas Gleixner | 76ebd05 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 10 | #include <linux/interrupt.h> |
Thomas Gleixner | ee7ae7a | 2008-04-17 17:40:45 +0200 | [diff] [blame] | 11 | #include <linux/seq_file.h> |
| 12 | #include <linux/debugfs.h> |
Tejun Heo | e59a1bb | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 13 | #include <linux/pfn.h> |
Tejun Heo | 8c4bfc6 | 2009-07-04 08:10:59 +0900 | [diff] [blame] | 14 | #include <linux/percpu.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 15 | #include <linux/gfp.h> |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 16 | |
Thomas Gleixner | 950f9d9 | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 17 | #include <asm/e820.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <asm/processor.h> |
| 19 | #include <asm/tlbflush.h> |
Dave Jones | f8af095 | 2006-01-06 00:12:10 -0800 | [diff] [blame] | 20 | #include <asm/sections.h> |
Jeremy Fitzhardinge | 93dbda7 | 2009-02-26 17:35:44 -0800 | [diff] [blame] | 21 | #include <asm/setup.h> |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 22 | #include <asm/uaccess.h> |
| 23 | #include <asm/pgalloc.h> |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 24 | #include <asm/proto.h> |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 25 | #include <asm/pat.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 27 | /* |
| 28 | * The current flushing context - we pass it instead of 5 arguments: |
| 29 | */ |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 30 | struct cpa_data { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 31 | unsigned long *vaddr; |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 32 | pgprot_t mask_set; |
| 33 | pgprot_t mask_clr; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 34 | int numpages; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 35 | int flags; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 36 | unsigned long pfn; |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 37 | unsigned force_split : 1; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 38 | int curpage; |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 39 | struct page **pages; |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 40 | }; |
| 41 | |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 42 | /* |
| 43 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) |
| 44 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb |
| 45 | * entries change the page attribute in parallel to some other cpu |
| 46 | * splitting a large page entry along with changing the attribute. |
| 47 | */ |
| 48 | static DEFINE_SPINLOCK(cpa_lock); |
| 49 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 50 | #define CPA_FLUSHTLB 1 |
| 51 | #define CPA_ARRAY 2 |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 52 | #define CPA_PAGES_ARRAY 4 |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 53 | |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 54 | #ifdef CONFIG_PROC_FS |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 55 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
| 56 | |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 57 | void update_page_count(int level, unsigned long pages) |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 58 | { |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 59 | unsigned long flags; |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 60 | |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 61 | /* Protect against CPA */ |
| 62 | spin_lock_irqsave(&pgd_lock, flags); |
| 63 | direct_pages_count[level] += pages; |
| 64 | spin_unlock_irqrestore(&pgd_lock, flags); |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 65 | } |
| 66 | |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 67 | static void split_page_count(int level) |
| 68 | { |
| 69 | direct_pages_count[level]--; |
| 70 | direct_pages_count[level - 1] += PTRS_PER_PTE; |
| 71 | } |
| 72 | |
Alexey Dobriyan | e1759c2 | 2008-10-15 23:50:22 +0400 | [diff] [blame] | 73 | void arch_report_meminfo(struct seq_file *m) |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 74 | { |
Hugh Dickins | b9c3bfc | 2008-11-06 12:05:40 +0000 | [diff] [blame] | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
Hugh Dickins | a06de63 | 2008-08-15 13:58:32 +0100 | [diff] [blame] | 76 | direct_pages_count[PG_LEVEL_4K] << 2); |
| 77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) |
Hugh Dickins | b9c3bfc | 2008-11-06 12:05:40 +0000 | [diff] [blame] | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
Hugh Dickins | a06de63 | 2008-08-15 13:58:32 +0100 | [diff] [blame] | 79 | direct_pages_count[PG_LEVEL_2M] << 11); |
| 80 | #else |
Hugh Dickins | b9c3bfc | 2008-11-06 12:05:40 +0000 | [diff] [blame] | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
Hugh Dickins | a06de63 | 2008-08-15 13:58:32 +0100 | [diff] [blame] | 82 | direct_pages_count[PG_LEVEL_2M] << 12); |
| 83 | #endif |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 84 | #ifdef CONFIG_X86_64 |
Hugh Dickins | a06de63 | 2008-08-15 13:58:32 +0100 | [diff] [blame] | 85 | if (direct_gbpages) |
Hugh Dickins | b9c3bfc | 2008-11-06 12:05:40 +0000 | [diff] [blame] | 86 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
Hugh Dickins | a06de63 | 2008-08-15 13:58:32 +0100 | [diff] [blame] | 87 | direct_pages_count[PG_LEVEL_1G] << 20); |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 88 | #endif |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 89 | } |
| 90 | #else |
| 91 | static inline void split_page_count(int level) { } |
| 92 | #endif |
| 93 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 94 | #ifdef CONFIG_X86_64 |
| 95 | |
| 96 | static inline unsigned long highmap_start_pfn(void) |
| 97 | { |
| 98 | return __pa(_text) >> PAGE_SHIFT; |
| 99 | } |
| 100 | |
| 101 | static inline unsigned long highmap_end_pfn(void) |
| 102 | { |
Jeremy Fitzhardinge | 93dbda7 | 2009-02-26 17:35:44 -0800 | [diff] [blame] | 103 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | #endif |
| 107 | |
Ingo Molnar | 92cb54a | 2008-02-13 14:37:52 +0100 | [diff] [blame] | 108 | #ifdef CONFIG_DEBUG_PAGEALLOC |
| 109 | # define debug_pagealloc 1 |
| 110 | #else |
| 111 | # define debug_pagealloc 0 |
| 112 | #endif |
| 113 | |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 114 | static inline int |
| 115 | within(unsigned long addr, unsigned long start, unsigned long end) |
Ingo Molnar | 687c482 | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 116 | { |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 117 | return addr >= start && addr < end; |
| 118 | } |
| 119 | |
| 120 | /* |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 121 | * Flushing functions |
| 122 | */ |
Thomas Gleixner | cd8ddf1 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 123 | |
Thomas Gleixner | cd8ddf1 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 124 | /** |
| 125 | * clflush_cache_range - flush a cache range with clflush |
| 126 | * @addr: virtual start address |
| 127 | * @size: number of bytes to flush |
| 128 | * |
| 129 | * clflush is an unordered instruction which needs fencing with mfence |
| 130 | * to avoid ordering issues. |
| 131 | */ |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 132 | void clflush_cache_range(void *vaddr, unsigned int size) |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 133 | { |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 134 | void *vend = vaddr + size - 1; |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 135 | |
Thomas Gleixner | cd8ddf1 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 136 | mb(); |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 137 | |
| 138 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) |
| 139 | clflush(vaddr); |
| 140 | /* |
| 141 | * Flush any possible final partial cacheline: |
| 142 | */ |
| 143 | clflush(vend); |
| 144 | |
Thomas Gleixner | cd8ddf1 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 145 | mb(); |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 146 | } |
Eric Anholt | e517a5e | 2009-09-10 17:48:48 -0700 | [diff] [blame] | 147 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 148 | |
Thomas Gleixner | af1e684 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 149 | static void __cpa_flush_all(void *arg) |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 150 | { |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 151 | unsigned long cache = (unsigned long)arg; |
| 152 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 153 | /* |
| 154 | * Flush all to work around Errata in early athlons regarding |
| 155 | * large page flushing. |
| 156 | */ |
| 157 | __flush_tlb_all(); |
| 158 | |
venkatesh.pallipadi@intel.com | 0b82753 | 2009-05-22 13:23:37 -0700 | [diff] [blame] | 159 | if (cache && boot_cpu_data.x86 >= 4) |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 160 | wbinvd(); |
| 161 | } |
| 162 | |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 163 | static void cpa_flush_all(unsigned long cache) |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 164 | { |
| 165 | BUG_ON(irqs_disabled()); |
| 166 | |
Jens Axboe | 15c8b6c | 2008-05-09 09:39:44 +0200 | [diff] [blame] | 167 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 168 | } |
| 169 | |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 170 | static void __cpa_flush_range(void *arg) |
| 171 | { |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 172 | /* |
| 173 | * We could optimize that further and do individual per page |
| 174 | * tlb invalidates for a low number of pages. Caveat: we must |
| 175 | * flush the high aliases on 64bit as well. |
| 176 | */ |
| 177 | __flush_tlb_all(); |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 178 | } |
| 179 | |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 180 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 181 | { |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 182 | unsigned int i, level; |
| 183 | unsigned long addr; |
| 184 | |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 185 | BUG_ON(irqs_disabled()); |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 186 | WARN_ON(PAGE_ALIGN(start) != start); |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 187 | |
Jens Axboe | 15c8b6c | 2008-05-09 09:39:44 +0200 | [diff] [blame] | 188 | on_each_cpu(__cpa_flush_range, NULL, 1); |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 189 | |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 190 | if (!cache) |
| 191 | return; |
| 192 | |
Thomas Gleixner | 3b233e5 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 193 | /* |
| 194 | * We only need to flush on one CPU, |
| 195 | * clflush is a MESI-coherent instruction that |
| 196 | * will cause all other CPUs to flush the same |
| 197 | * cachelines: |
| 198 | */ |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 199 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
| 200 | pte_t *pte = lookup_address(addr, &level); |
| 201 | |
| 202 | /* |
| 203 | * Only flush present addresses: |
| 204 | */ |
Thomas Gleixner | 7bfb72e | 2008-02-04 16:48:08 +0100 | [diff] [blame] | 205 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 206 | clflush_cache_range((void *) addr, PAGE_SIZE); |
| 207 | } |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 208 | } |
| 209 | |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 210 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
| 211 | int in_flags, struct page **pages) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 212 | { |
| 213 | unsigned int i, level; |
Pallipadi, Venkatesh | 2171787 | 2009-05-26 10:33:35 -0700 | [diff] [blame] | 214 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 215 | |
| 216 | BUG_ON(irqs_disabled()); |
| 217 | |
Pallipadi, Venkatesh | 2171787 | 2009-05-26 10:33:35 -0700 | [diff] [blame] | 218 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 219 | |
Pallipadi, Venkatesh | 2171787 | 2009-05-26 10:33:35 -0700 | [diff] [blame] | 220 | if (!cache || do_wbinvd) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 221 | return; |
| 222 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 223 | /* |
| 224 | * We only need to flush on one CPU, |
| 225 | * clflush is a MESI-coherent instruction that |
| 226 | * will cause all other CPUs to flush the same |
| 227 | * cachelines: |
| 228 | */ |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 229 | for (i = 0; i < numpages; i++) { |
| 230 | unsigned long addr; |
| 231 | pte_t *pte; |
| 232 | |
| 233 | if (in_flags & CPA_PAGES_ARRAY) |
| 234 | addr = (unsigned long)page_address(pages[i]); |
| 235 | else |
| 236 | addr = start[i]; |
| 237 | |
| 238 | pte = lookup_address(addr, &level); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 239 | |
| 240 | /* |
| 241 | * Only flush present addresses: |
| 242 | */ |
| 243 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 244 | clflush_cache_range((void *)addr, PAGE_SIZE); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 245 | } |
| 246 | } |
| 247 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 248 | /* |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 249 | * Certain areas of memory on x86 require very specific protection flags, |
| 250 | * for example the BIOS area or kernel text. Callers don't always get this |
| 251 | * right (again, ioremap() on BIOS memory is not uncommon) so this function |
| 252 | * checks and fixes these known static required protection bits. |
| 253 | */ |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 254 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
| 255 | unsigned long pfn) |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 256 | { |
| 257 | pgprot_t forbidden = __pgprot(0); |
| 258 | |
Ingo Molnar | 687c482 | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 259 | /* |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 260 | * The BIOS area between 640k and 1Mb needs to be executable for |
| 261 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. |
Ingo Molnar | 687c482 | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 262 | */ |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 263 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 264 | pgprot_val(forbidden) |= _PAGE_NX; |
| 265 | |
| 266 | /* |
| 267 | * The kernel text needs to be executable for obvious reasons |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 268 | * Does not cover __inittext since that is gone later on. On |
| 269 | * 64bit we do not enforce !NX on the low mapping |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 270 | */ |
| 271 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) |
| 272 | pgprot_val(forbidden) |= _PAGE_NX; |
Arjan van de Ven | cc0f21b | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 273 | |
Arjan van de Ven | cc0f21b | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 274 | /* |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 275 | * The .rodata section needs to be read-only. Using the pfn |
| 276 | * catches all aliases. |
Arjan van de Ven | cc0f21b | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 277 | */ |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 278 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
| 279 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) |
Arjan van de Ven | cc0f21b | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 280 | pgprot_val(forbidden) |= _PAGE_RW; |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 281 | |
Suresh Siddha | 55ca3cc | 2009-10-28 18:46:57 -0800 | [diff] [blame] | 282 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
Suresh Siddha | 74e0817 | 2009-10-14 14:46:56 -0700 | [diff] [blame] | 283 | /* |
Suresh Siddha | 502f660 | 2009-10-28 18:46:56 -0800 | [diff] [blame] | 284 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
| 285 | * kernel text mappings for the large page aligned text, rodata sections |
| 286 | * will be always read-only. For the kernel identity mappings covering |
| 287 | * the holes caused by this alignment can be anything that user asks. |
Suresh Siddha | 74e0817 | 2009-10-14 14:46:56 -0700 | [diff] [blame] | 288 | * |
| 289 | * This will preserve the large page mappings for kernel text/data |
| 290 | * at no extra cost. |
| 291 | */ |
Suresh Siddha | 502f660 | 2009-10-28 18:46:56 -0800 | [diff] [blame] | 292 | if (kernel_set_to_readonly && |
| 293 | within(address, (unsigned long)_text, |
Suresh Siddha | 281ff33 | 2010-02-18 11:51:40 -0800 | [diff] [blame] | 294 | (unsigned long)__end_rodata_hpage_align)) { |
| 295 | unsigned int level; |
| 296 | |
| 297 | /* |
| 298 | * Don't enforce the !RW mapping for the kernel text mapping, |
| 299 | * if the current mapping is already using small page mapping. |
| 300 | * No need to work hard to preserve large page mappings in this |
| 301 | * case. |
| 302 | * |
| 303 | * This also fixes the Linux Xen paravirt guest boot failure |
| 304 | * (because of unexpected read-only mappings for kernel identity |
| 305 | * mappings). In this paravirt guest case, the kernel text |
| 306 | * mapping and the kernel identity mapping share the same |
| 307 | * page-table pages. Thus we can't really use different |
| 308 | * protections for the kernel text and identity mappings. Also, |
| 309 | * these shared mappings are made of small page mappings. |
| 310 | * Thus this don't enforce !RW mapping for small page kernel |
| 311 | * text mapping logic will help Linux Xen parvirt guest boot |
| 312 | * aswell. |
| 313 | */ |
| 314 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) |
| 315 | pgprot_val(forbidden) |= _PAGE_RW; |
| 316 | } |
Suresh Siddha | 74e0817 | 2009-10-14 14:46:56 -0700 | [diff] [blame] | 317 | #endif |
| 318 | |
Arjan van de Ven | ed724be | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 319 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
Ingo Molnar | 687c482 | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 320 | |
| 321 | return prot; |
| 322 | } |
| 323 | |
Thomas Gleixner | 9a14aef | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 324 | /* |
| 325 | * Lookup the page table entry for a virtual address. Return a pointer |
| 326 | * to the entry and the level of the mapping. |
| 327 | * |
| 328 | * Note: We return pud and pmd either when the entry is marked large |
| 329 | * or when the present bit is not set. Otherwise we would return a |
| 330 | * pointer to a nonexisting mapping. |
| 331 | */ |
Harvey Harrison | da7bfc5 | 2008-02-09 23:24:08 +0100 | [diff] [blame] | 332 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 333 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | pgd_t *pgd = pgd_offset_k(address); |
| 335 | pud_t *pud; |
| 336 | pmd_t *pmd; |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 337 | |
Thomas Gleixner | 30551bb | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 338 | *level = PG_LEVEL_NONE; |
| 339 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | if (pgd_none(*pgd)) |
| 341 | return NULL; |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | pud = pud_offset(pgd, address); |
| 344 | if (pud_none(*pud)) |
| 345 | return NULL; |
Andi Kleen | c2f71ee | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 346 | |
| 347 | *level = PG_LEVEL_1G; |
| 348 | if (pud_large(*pud) || !pud_present(*pud)) |
| 349 | return (pte_t *)pud; |
| 350 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | pmd = pmd_offset(pud, address); |
| 352 | if (pmd_none(*pmd)) |
| 353 | return NULL; |
Thomas Gleixner | 30551bb | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 354 | |
| 355 | *level = PG_LEVEL_2M; |
Thomas Gleixner | 9a14aef | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 356 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | return (pte_t *)pmd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | |
Thomas Gleixner | 30551bb | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 359 | *level = PG_LEVEL_4K; |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 360 | |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 361 | return pte_offset_kernel(pmd, address); |
| 362 | } |
Pekka Paalanen | 75bb883 | 2008-05-12 21:20:56 +0200 | [diff] [blame] | 363 | EXPORT_SYMBOL_GPL(lookup_address); |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 364 | |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 365 | /* |
| 366 | * Set the new pmd in all the pgds we know about: |
| 367 | */ |
Ingo Molnar | 9a3dc78 | 2008-01-30 13:33:57 +0100 | [diff] [blame] | 368 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 369 | { |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 370 | /* change init_mm */ |
| 371 | set_pte_atomic(kpte, pte); |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 372 | #ifdef CONFIG_X86_32 |
Ingo Molnar | e4b71dc | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 373 | if (!SHARED_KERNEL_PMD) { |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 374 | struct page *page; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | |
Jeremy Fitzhardinge | e3ed910 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 376 | list_for_each_entry(page, &pgd_list, lru) { |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 377 | pgd_t *pgd; |
| 378 | pud_t *pud; |
| 379 | pmd_t *pmd; |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 380 | |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 381 | pgd = (pgd_t *)page_address(page) + pgd_index(address); |
| 382 | pud = pud_offset(pgd, address); |
| 383 | pmd = pmd_offset(pud, address); |
| 384 | set_pte_atomic((pte_t *)pmd, pte); |
| 385 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | } |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 387 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | } |
| 389 | |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 390 | static int |
| 391 | try_preserve_large_page(pte_t *kpte, unsigned long address, |
| 392 | struct cpa_data *cpa) |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 393 | { |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 394 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 395 | pte_t new_pte, old_pte, *tmp; |
| 396 | pgprot_t old_prot, new_prot; |
Thomas Gleixner | fac8493 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 397 | int i, do_split = 1; |
Harvey Harrison | da7bfc5 | 2008-02-09 23:24:08 +0100 | [diff] [blame] | 398 | unsigned int level; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 399 | |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 400 | if (cpa->force_split) |
| 401 | return 1; |
| 402 | |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 403 | spin_lock_irqsave(&pgd_lock, flags); |
| 404 | /* |
| 405 | * Check for races, another CPU might have split this page |
| 406 | * up already: |
| 407 | */ |
| 408 | tmp = lookup_address(address, &level); |
| 409 | if (tmp != kpte) |
| 410 | goto out_unlock; |
| 411 | |
| 412 | switch (level) { |
| 413 | case PG_LEVEL_2M: |
Andi Kleen | 31422c5 | 2008-02-04 16:48:08 +0100 | [diff] [blame] | 414 | psize = PMD_PAGE_SIZE; |
| 415 | pmask = PMD_PAGE_MASK; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 416 | break; |
Andi Kleen | f07333f | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 417 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 418 | case PG_LEVEL_1G: |
Andi Kleen | 5d3c8b2 | 2008-02-13 16:20:35 +0100 | [diff] [blame] | 419 | psize = PUD_PAGE_SIZE; |
| 420 | pmask = PUD_PAGE_MASK; |
Andi Kleen | f07333f | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 421 | break; |
| 422 | #endif |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 423 | default: |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 424 | do_split = -EINVAL; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 425 | goto out_unlock; |
| 426 | } |
| 427 | |
| 428 | /* |
| 429 | * Calculate the number of pages, which fit into this large |
| 430 | * page starting at address: |
| 431 | */ |
| 432 | nextpage_addr = (address + psize) & pmask; |
| 433 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 434 | if (numpages < cpa->numpages) |
| 435 | cpa->numpages = numpages; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 436 | |
| 437 | /* |
| 438 | * We are safe now. Check whether the new pgprot is the same: |
| 439 | */ |
| 440 | old_pte = *kpte; |
| 441 | old_prot = new_prot = pte_pgprot(old_pte); |
| 442 | |
| 443 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
| 444 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 445 | |
| 446 | /* |
| 447 | * old_pte points to the large page base address. So we need |
| 448 | * to add the offset of the virtual address: |
| 449 | */ |
| 450 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); |
| 451 | cpa->pfn = pfn; |
| 452 | |
| 453 | new_prot = static_protections(new_prot, address, pfn); |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 454 | |
| 455 | /* |
Thomas Gleixner | fac8493 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 456 | * We need to check the full range, whether |
| 457 | * static_protection() requires a different pgprot for one of |
| 458 | * the pages in the range we try to preserve: |
| 459 | */ |
| 460 | addr = address + PAGE_SIZE; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 461 | pfn++; |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 462 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 463 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
Thomas Gleixner | fac8493 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 464 | |
| 465 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) |
| 466 | goto out_unlock; |
| 467 | } |
| 468 | |
| 469 | /* |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 470 | * If there are no changes, return. maxpages has been updated |
| 471 | * above: |
| 472 | */ |
| 473 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 474 | do_split = 0; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 475 | goto out_unlock; |
| 476 | } |
| 477 | |
| 478 | /* |
| 479 | * We need to change the attributes. Check, whether we can |
| 480 | * change the large page in one go. We request a split, when |
| 481 | * the address is not aligned and the number of pages is |
| 482 | * smaller than the number of pages in the large page. Note |
| 483 | * that we limited the number of possible pages already to |
| 484 | * the number of pages in the large page. |
| 485 | */ |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 486 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 487 | /* |
| 488 | * The address is aligned and the number of pages |
| 489 | * covers the full page. |
| 490 | */ |
| 491 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); |
| 492 | __set_pmd_pte(kpte, address, new_pte); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 493 | cpa->flags |= CPA_FLUSHTLB; |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 494 | do_split = 0; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 495 | } |
| 496 | |
| 497 | out_unlock: |
| 498 | spin_unlock_irqrestore(&pgd_lock, flags); |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 499 | |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 500 | return do_split; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 501 | } |
| 502 | |
Ingo Molnar | 7afe15b | 2008-01-30 13:33:57 +0100 | [diff] [blame] | 503 | static int split_large_page(pte_t *kpte, unsigned long address) |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 504 | { |
Thomas Gleixner | 7b610ee | 2008-02-04 16:48:10 +0100 | [diff] [blame] | 505 | unsigned long flags, pfn, pfninc = 1; |
Ingo Molnar | 86f0398 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 506 | unsigned int i, level; |
Ingo Molnar | 9df8499 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 507 | pte_t *pbase, *tmp; |
| 508 | pgprot_t ref_prot; |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 509 | struct page *base; |
| 510 | |
| 511 | if (!debug_pagealloc) |
| 512 | spin_unlock(&cpa_lock); |
Vegard Nossum | 9e73023 | 2009-02-22 11:28:25 +0100 | [diff] [blame] | 513 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 514 | if (!debug_pagealloc) |
| 515 | spin_lock(&cpa_lock); |
Suresh Siddha | 8311eb8 | 2008-09-23 14:00:41 -0700 | [diff] [blame] | 516 | if (!base) |
| 517 | return -ENOMEM; |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 518 | |
Ingo Molnar | 9a3dc78 | 2008-01-30 13:33:57 +0100 | [diff] [blame] | 519 | spin_lock_irqsave(&pgd_lock, flags); |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 520 | /* |
| 521 | * Check for races, another CPU might have split this page |
| 522 | * up for us already: |
| 523 | */ |
| 524 | tmp = lookup_address(address, &level); |
Ingo Molnar | 6ce9fc1 | 2008-02-04 16:48:08 +0100 | [diff] [blame] | 525 | if (tmp != kpte) |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 526 | goto out_unlock; |
| 527 | |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 528 | pbase = (pte_t *)page_address(base); |
Jeremy Fitzhardinge | 6944a9c | 2008-03-17 16:37:01 -0700 | [diff] [blame] | 529 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
Thomas Gleixner | 07cf89c | 2008-02-04 16:48:08 +0100 | [diff] [blame] | 530 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
Ingo Molnar | 7a5714e | 2009-02-20 17:44:21 +0100 | [diff] [blame] | 531 | /* |
| 532 | * If we ever want to utilize the PAT bit, we need to |
| 533 | * update this function to make sure it's converted from |
| 534 | * bit 12 to bit 7 when we cross from the 2MB level to |
| 535 | * the 4K level: |
| 536 | */ |
| 537 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 538 | |
Andi Kleen | f07333f | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 539 | #ifdef CONFIG_X86_64 |
| 540 | if (level == PG_LEVEL_1G) { |
| 541 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
| 542 | pgprot_val(ref_prot) |= _PAGE_PSE; |
Andi Kleen | f07333f | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 543 | } |
| 544 | #endif |
| 545 | |
Thomas Gleixner | 63c1dcf | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 546 | /* |
| 547 | * Get the target pfn from the original entry: |
| 548 | */ |
| 549 | pfn = pte_pfn(*kpte); |
Andi Kleen | f07333f | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 550 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
Thomas Gleixner | 63c1dcf | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 551 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 552 | |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 553 | if (address >= (unsigned long)__va(0) && |
Yinghai Lu | f361a45 | 2008-07-10 20:38:26 -0700 | [diff] [blame] | 554 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
| 555 | split_page_count(level); |
| 556 | |
| 557 | #ifdef CONFIG_X86_64 |
| 558 | if (address >= (unsigned long)__va(1UL<<32) && |
Thomas Gleixner | 65280e6 | 2008-05-05 16:35:21 +0200 | [diff] [blame] | 559 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
| 560 | split_page_count(level); |
Yinghai Lu | f361a45 | 2008-07-10 20:38:26 -0700 | [diff] [blame] | 561 | #endif |
Andi Kleen | ce0c0e5 | 2008-05-02 11:46:49 +0200 | [diff] [blame] | 562 | |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 563 | /* |
Ingo Molnar | 07a66d7 | 2009-02-20 08:04:13 +0100 | [diff] [blame] | 564 | * Install the new, split up pagetable. |
Huang, Ying | 4c881ca | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 565 | * |
Ingo Molnar | 07a66d7 | 2009-02-20 08:04:13 +0100 | [diff] [blame] | 566 | * We use the standard kernel pagetable protections for the new |
| 567 | * pagetable protections, the actual ptes set above control the |
| 568 | * primary protection behavior: |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 569 | */ |
Ingo Molnar | 07a66d7 | 2009-02-20 08:04:13 +0100 | [diff] [blame] | 570 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
Ingo Molnar | 211b3d0 | 2009-03-10 22:31:03 +0100 | [diff] [blame] | 571 | |
| 572 | /* |
| 573 | * Intel Atom errata AAH41 workaround. |
| 574 | * |
| 575 | * The real fix should be in hw or in a microcode update, but |
| 576 | * we also probabilistically try to reduce the window of having |
| 577 | * a large TLB mixed with 4K TLBs while instruction fetches are |
| 578 | * going on. |
| 579 | */ |
| 580 | __flush_tlb_all(); |
| 581 | |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 582 | base = NULL; |
| 583 | |
| 584 | out_unlock: |
Thomas Gleixner | eb5b5f0 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 585 | /* |
| 586 | * If we dropped out via the lookup_address check under |
| 587 | * pgd_lock then stick the page back into the pool: |
| 588 | */ |
Suresh Siddha | 8311eb8 | 2008-09-23 14:00:41 -0700 | [diff] [blame] | 589 | if (base) |
| 590 | __free_page(base); |
Ingo Molnar | 9a3dc78 | 2008-01-30 13:33:57 +0100 | [diff] [blame] | 591 | spin_unlock_irqrestore(&pgd_lock, flags); |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 592 | |
Ingo Molnar | bb5c2db | 2008-01-30 13:33:56 +0100 | [diff] [blame] | 593 | return 0; |
| 594 | } |
| 595 | |
Suresh Siddha | a1e4621 | 2009-01-20 14:20:21 -0800 | [diff] [blame] | 596 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
| 597 | int primary) |
| 598 | { |
| 599 | /* |
| 600 | * Ignore all non primary paths. |
| 601 | */ |
| 602 | if (!primary) |
| 603 | return 0; |
| 604 | |
| 605 | /* |
| 606 | * Ignore the NULL PTE for kernel identity mapping, as it is expected |
| 607 | * to have holes. |
| 608 | * Also set numpages to '1' indicating that we processed cpa req for |
| 609 | * one virtual address page and its pfn. TBD: numpages can be set based |
| 610 | * on the initial value and the level returned by lookup_address(). |
| 611 | */ |
| 612 | if (within(vaddr, PAGE_OFFSET, |
| 613 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { |
| 614 | cpa->numpages = 1; |
| 615 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; |
| 616 | return 0; |
| 617 | } else { |
| 618 | WARN(1, KERN_WARNING "CPA: called for zero pte. " |
| 619 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, |
| 620 | *cpa->vaddr); |
| 621 | |
| 622 | return -EFAULT; |
| 623 | } |
| 624 | } |
| 625 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 626 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 627 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 628 | unsigned long address; |
Harvey Harrison | da7bfc5 | 2008-02-09 23:24:08 +0100 | [diff] [blame] | 629 | int do_split, err; |
| 630 | unsigned int level; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 631 | pte_t *kpte, old_pte; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | |
Thomas Hellstrom | 8523acf | 2009-08-03 09:25:45 +0200 | [diff] [blame] | 633 | if (cpa->flags & CPA_PAGES_ARRAY) { |
| 634 | struct page *page = cpa->pages[cpa->curpage]; |
| 635 | if (unlikely(PageHighMem(page))) |
| 636 | return 0; |
| 637 | address = (unsigned long)page_address(page); |
| 638 | } else if (cpa->flags & CPA_ARRAY) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 639 | address = cpa->vaddr[cpa->curpage]; |
| 640 | else |
| 641 | address = *cpa->vaddr; |
Ingo Molnar | 97f99fe | 2008-01-30 13:33:55 +0100 | [diff] [blame] | 642 | repeat: |
Ingo Molnar | f0646e4 | 2008-01-30 13:33:43 +0100 | [diff] [blame] | 643 | kpte = lookup_address(address, &level); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | if (!kpte) |
Suresh Siddha | a1e4621 | 2009-01-20 14:20:21 -0800 | [diff] [blame] | 645 | return __cpa_process_fault(cpa, address, primary); |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 646 | |
| 647 | old_pte = *kpte; |
Suresh Siddha | a1e4621 | 2009-01-20 14:20:21 -0800 | [diff] [blame] | 648 | if (!pte_val(old_pte)) |
| 649 | return __cpa_process_fault(cpa, address, primary); |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 650 | |
Thomas Gleixner | 30551bb | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 651 | if (level == PG_LEVEL_4K) { |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 652 | pte_t new_pte; |
Arjan van de Ven | 626c2c9 | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 653 | pgprot_t new_prot = pte_pgprot(old_pte); |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 654 | unsigned long pfn = pte_pfn(old_pte); |
Thomas Gleixner | a72a08a | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 655 | |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 656 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
| 657 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); |
Ingo Molnar | 86f0398 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 658 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 659 | new_prot = static_protections(new_prot, address, pfn); |
Ingo Molnar | 86f0398 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 660 | |
Arjan van de Ven | 626c2c9 | 2008-02-04 16:48:05 +0100 | [diff] [blame] | 661 | /* |
| 662 | * We need to keep the pfn from the existing PTE, |
| 663 | * after all we're only going to change it's attributes |
| 664 | * not the memory it points to |
| 665 | */ |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 666 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
| 667 | cpa->pfn = pfn; |
Thomas Gleixner | f4ae5da | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 668 | /* |
| 669 | * Do we really change anything ? |
| 670 | */ |
| 671 | if (pte_val(old_pte) != pte_val(new_pte)) { |
| 672 | set_pte_atomic(kpte, new_pte); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 673 | cpa->flags |= CPA_FLUSHTLB; |
Thomas Gleixner | f4ae5da | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 674 | } |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 675 | cpa->numpages = 1; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 676 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | } |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 678 | |
| 679 | /* |
| 680 | * Check, whether we can keep the large page intact |
| 681 | * and just change the pte: |
| 682 | */ |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 683 | do_split = try_preserve_large_page(kpte, address, cpa); |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 684 | /* |
| 685 | * When the range fits into the existing large page, |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 686 | * return. cp->numpages and cpa->tlbflush have been updated in |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 687 | * try_large_page: |
| 688 | */ |
Ingo Molnar | 87f7f8f | 2008-02-04 16:48:10 +0100 | [diff] [blame] | 689 | if (do_split <= 0) |
| 690 | return do_split; |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 691 | |
| 692 | /* |
| 693 | * We have to split the large page: |
| 694 | */ |
Ingo Molnar | 87f7f8f | 2008-02-04 16:48:10 +0100 | [diff] [blame] | 695 | err = split_large_page(kpte, address); |
| 696 | if (!err) { |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 697 | /* |
| 698 | * Do a global flush tlb after splitting the large page |
| 699 | * and before we do the actual change page attribute in the PTE. |
| 700 | * |
| 701 | * With out this, we violate the TLB application note, that says |
| 702 | * "The TLBs may contain both ordinary and large-page |
| 703 | * translations for a 4-KByte range of linear addresses. This |
| 704 | * may occur if software modifies the paging structures so that |
| 705 | * the page size used for the address range changes. If the two |
| 706 | * translations differ with respect to page frame or attributes |
| 707 | * (e.g., permissions), processor behavior is undefined and may |
| 708 | * be implementation-specific." |
| 709 | * |
| 710 | * We do this global tlb flush inside the cpa_lock, so that we |
| 711 | * don't allow any other cpu, with stale tlb entries change the |
| 712 | * page attribute in parallel, that also falls into the |
| 713 | * just split large page entry. |
| 714 | */ |
| 715 | flush_tlb_all(); |
Ingo Molnar | 87f7f8f | 2008-02-04 16:48:10 +0100 | [diff] [blame] | 716 | goto repeat; |
| 717 | } |
Ingo Molnar | beaff63 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 718 | |
Ingo Molnar | 87f7f8f | 2008-02-04 16:48:10 +0100 | [diff] [blame] | 719 | return err; |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 720 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 722 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
| 723 | |
| 724 | static int cpa_process_alias(struct cpa_data *cpa) |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 725 | { |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 726 | struct cpa_data alias_cpa; |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 727 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
Tejun Heo | e933a73 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 728 | unsigned long vaddr; |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 729 | int ret; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 730 | |
Yinghai Lu | 965194c | 2008-07-12 14:31:28 -0700 | [diff] [blame] | 731 | if (cpa->pfn >= max_pfn_mapped) |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 732 | return 0; |
| 733 | |
Yinghai Lu | f361a45 | 2008-07-10 20:38:26 -0700 | [diff] [blame] | 734 | #ifdef CONFIG_X86_64 |
Yinghai Lu | 965194c | 2008-07-12 14:31:28 -0700 | [diff] [blame] | 735 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
Yinghai Lu | f361a45 | 2008-07-10 20:38:26 -0700 | [diff] [blame] | 736 | return 0; |
| 737 | #endif |
Thomas Gleixner | f34b439 | 2008-02-15 22:17:57 +0100 | [diff] [blame] | 738 | /* |
| 739 | * No need to redo, when the primary call touched the direct |
| 740 | * mapping already: |
| 741 | */ |
Thomas Hellstrom | 8523acf | 2009-08-03 09:25:45 +0200 | [diff] [blame] | 742 | if (cpa->flags & CPA_PAGES_ARRAY) { |
| 743 | struct page *page = cpa->pages[cpa->curpage]; |
| 744 | if (unlikely(PageHighMem(page))) |
| 745 | return 0; |
| 746 | vaddr = (unsigned long)page_address(page); |
| 747 | } else if (cpa->flags & CPA_ARRAY) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 748 | vaddr = cpa->vaddr[cpa->curpage]; |
| 749 | else |
| 750 | vaddr = *cpa->vaddr; |
| 751 | |
| 752 | if (!(within(vaddr, PAGE_OFFSET, |
Suresh Siddha | a1e4621 | 2009-01-20 14:20:21 -0800 | [diff] [blame] | 753 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 754 | |
Thomas Gleixner | f34b439 | 2008-02-15 22:17:57 +0100 | [diff] [blame] | 755 | alias_cpa = *cpa; |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 756 | alias_cpa.vaddr = &laddr; |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 757 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 758 | |
Thomas Gleixner | f34b439 | 2008-02-15 22:17:57 +0100 | [diff] [blame] | 759 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 760 | if (ret) |
| 761 | return ret; |
Thomas Gleixner | f34b439 | 2008-02-15 22:17:57 +0100 | [diff] [blame] | 762 | } |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 763 | |
Arjan van de Ven | 488fd99 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 764 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0879750 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 765 | /* |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 766 | * If the primary call didn't touch the high mapping already |
| 767 | * and the physical address is inside the kernel map, we need |
Thomas Gleixner | 0879750 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 768 | * to touch the high mapped kernel as well: |
| 769 | */ |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 770 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
| 771 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { |
| 772 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
| 773 | __START_KERNEL_map - phys_base; |
| 774 | alias_cpa = *cpa; |
| 775 | alias_cpa.vaddr = &temp_cpa_vaddr; |
| 776 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
Thomas Gleixner | 0879750 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 777 | |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 778 | /* |
| 779 | * The high mapping range is imprecise, so ignore the |
| 780 | * return value. |
| 781 | */ |
| 782 | __change_page_attr_set_clr(&alias_cpa, 0); |
| 783 | } |
Thomas Gleixner | 0879750 | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 784 | #endif |
Tejun Heo | 992f4c1 | 2009-06-22 11:56:24 +0900 | [diff] [blame] | 785 | |
| 786 | return 0; |
Ingo Molnar | 44af6c4 | 2008-01-30 13:34:03 +0100 | [diff] [blame] | 787 | } |
| 788 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 789 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 790 | { |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 791 | int ret, numpages = cpa->numpages; |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 792 | |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 793 | while (numpages) { |
| 794 | /* |
| 795 | * Store the remaining nr of pages for the large page |
| 796 | * preservation check. |
| 797 | */ |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 798 | cpa->numpages = numpages; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 799 | /* for array changes, we can't use large page */ |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 800 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 801 | cpa->numpages = 1; |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 802 | |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 803 | if (!debug_pagealloc) |
| 804 | spin_lock(&cpa_lock); |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 805 | ret = __change_page_attr(cpa, checkalias); |
Suresh Siddha | ad5ca55 | 2008-09-23 14:00:42 -0700 | [diff] [blame] | 806 | if (!debug_pagealloc) |
| 807 | spin_unlock(&cpa_lock); |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 808 | if (ret) |
| 809 | return ret; |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 810 | |
Thomas Gleixner | c31c7d4 | 2008-02-18 20:54:14 +0100 | [diff] [blame] | 811 | if (checkalias) { |
| 812 | ret = cpa_process_alias(cpa); |
| 813 | if (ret) |
| 814 | return ret; |
| 815 | } |
| 816 | |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 817 | /* |
| 818 | * Adjust the number of pages with the result of the |
| 819 | * CPA operation. Either a large page has been |
| 820 | * preserved or a single page update happened. |
| 821 | */ |
Rafael J. Wysocki | 9b5cf48 | 2008-03-03 01:17:37 +0100 | [diff] [blame] | 822 | BUG_ON(cpa->numpages > numpages); |
| 823 | numpages -= cpa->numpages; |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 824 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 825 | cpa->curpage++; |
| 826 | else |
| 827 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; |
| 828 | |
Thomas Gleixner | 65e074d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 829 | } |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 830 | return 0; |
| 831 | } |
| 832 | |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 833 | static inline int cache_attr(pgprot_t attr) |
| 834 | { |
| 835 | return pgprot_val(attr) & |
| 836 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); |
| 837 | } |
| 838 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 839 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 840 | pgprot_t mask_set, pgprot_t mask_clr, |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 841 | int force_split, int in_flag, |
| 842 | struct page **pages) |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 843 | { |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 844 | struct cpa_data cpa; |
Ingo Molnar | cacf890 | 2008-08-21 13:46:33 +0200 | [diff] [blame] | 845 | int ret, cache, checkalias; |
Jack Steiner | fa526d0 | 2009-09-03 12:56:02 -0500 | [diff] [blame] | 846 | unsigned long baddr = 0; |
Thomas Gleixner | 331e406 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 847 | |
| 848 | /* |
| 849 | * Check, if we are requested to change a not supported |
| 850 | * feature: |
| 851 | */ |
| 852 | mask_set = canon_pgprot(mask_set); |
| 853 | mask_clr = canon_pgprot(mask_clr); |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 854 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
Thomas Gleixner | 331e406 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 855 | return 0; |
| 856 | |
Thomas Gleixner | 69b1415 | 2008-02-13 11:04:50 +0100 | [diff] [blame] | 857 | /* Ensure we are PAGE_SIZE aligned */ |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 858 | if (in_flag & CPA_ARRAY) { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 859 | int i; |
| 860 | for (i = 0; i < numpages; i++) { |
| 861 | if (addr[i] & ~PAGE_MASK) { |
| 862 | addr[i] &= PAGE_MASK; |
| 863 | WARN_ON_ONCE(1); |
| 864 | } |
| 865 | } |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 866 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
| 867 | /* |
| 868 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. |
| 869 | * No need to cehck in that case |
| 870 | */ |
| 871 | if (*addr & ~PAGE_MASK) { |
| 872 | *addr &= PAGE_MASK; |
| 873 | /* |
| 874 | * People should not be passing in unaligned addresses: |
| 875 | */ |
| 876 | WARN_ON_ONCE(1); |
| 877 | } |
Jack Steiner | fa526d0 | 2009-09-03 12:56:02 -0500 | [diff] [blame] | 878 | /* |
| 879 | * Save address for cache flush. *addr is modified in the call |
| 880 | * to __change_page_attr_set_clr() below. |
| 881 | */ |
| 882 | baddr = *addr; |
Thomas Gleixner | 69b1415 | 2008-02-13 11:04:50 +0100 | [diff] [blame] | 883 | } |
| 884 | |
Nick Piggin | 5843d9a | 2008-08-01 03:15:21 +0200 | [diff] [blame] | 885 | /* Must avoid aliasing mappings in the highmem code */ |
| 886 | kmap_flush_unused(); |
| 887 | |
Nick Piggin | db64fe0 | 2008-10-18 20:27:03 -0700 | [diff] [blame] | 888 | vm_unmap_aliases(); |
| 889 | |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 890 | cpa.vaddr = addr; |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 891 | cpa.pages = pages; |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 892 | cpa.numpages = numpages; |
| 893 | cpa.mask_set = mask_set; |
| 894 | cpa.mask_clr = mask_clr; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 895 | cpa.flags = 0; |
| 896 | cpa.curpage = 0; |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 897 | cpa.force_split = force_split; |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 898 | |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 899 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
| 900 | cpa.flags |= in_flag; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 901 | |
Thomas Gleixner | af96e44 | 2008-02-15 21:49:46 +0100 | [diff] [blame] | 902 | /* No alias checking for _NX bit modifications */ |
| 903 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; |
| 904 | |
| 905 | ret = __change_page_attr_set_clr(&cpa, checkalias); |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 906 | |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 907 | /* |
Thomas Gleixner | f4ae5da | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 908 | * Check whether we really changed something: |
| 909 | */ |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 910 | if (!(cpa.flags & CPA_FLUSHTLB)) |
Shaohua Li | 1ac2f7d | 2008-08-04 14:51:24 +0800 | [diff] [blame] | 911 | goto out; |
Ingo Molnar | cacf890 | 2008-08-21 13:46:33 +0200 | [diff] [blame] | 912 | |
Thomas Gleixner | f4ae5da | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 913 | /* |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 914 | * No need to flush, when we did not set any of the caching |
| 915 | * attributes: |
| 916 | */ |
| 917 | cache = cache_attr(mask_set); |
| 918 | |
| 919 | /* |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 920 | * On success we use clflush, when the CPU supports it to |
| 921 | * avoid the wbindv. If the CPU does not support it and in the |
Thomas Gleixner | af1e684 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 922 | * error case we fall back to cpa_flush_all (which uses |
Thomas Gleixner | 57a6a46 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 923 | * wbindv): |
| 924 | */ |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 925 | if (!ret && cpu_has_clflush) { |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 926 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
| 927 | cpa_flush_array(addr, numpages, cache, |
| 928 | cpa.flags, pages); |
| 929 | } else |
Jack Steiner | fa526d0 | 2009-09-03 12:56:02 -0500 | [diff] [blame] | 930 | cpa_flush_range(baddr, numpages, cache); |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 931 | } else |
Andi Kleen | 6bb8383 | 2008-02-04 16:48:06 +0100 | [diff] [blame] | 932 | cpa_flush_all(cache); |
Ingo Molnar | cacf890 | 2008-08-21 13:46:33 +0200 | [diff] [blame] | 933 | |
Thomas Gleixner | 76ebd05 | 2008-02-09 23:24:09 +0100 | [diff] [blame] | 934 | out: |
Thomas Gleixner | ff31452 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 935 | return ret; |
| 936 | } |
| 937 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 938 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
| 939 | pgprot_t mask, int array) |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 940 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 941 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 942 | (array ? CPA_ARRAY : 0), NULL); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 943 | } |
| 944 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 945 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
| 946 | pgprot_t mask, int array) |
Thomas Gleixner | 72932c7 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 947 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 948 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 949 | (array ? CPA_ARRAY : 0), NULL); |
Thomas Gleixner | 72932c7 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 950 | } |
| 951 | |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 952 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
| 953 | pgprot_t mask) |
| 954 | { |
| 955 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, |
| 956 | CPA_PAGES_ARRAY, pages); |
| 957 | } |
| 958 | |
| 959 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, |
| 960 | pgprot_t mask) |
| 961 | { |
| 962 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, |
| 963 | CPA_PAGES_ARRAY, pages); |
| 964 | } |
| 965 | |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 966 | int _set_memory_uc(unsigned long addr, int numpages) |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 967 | { |
Suresh Siddha | de33c44 | 2008-04-25 17:07:22 -0700 | [diff] [blame] | 968 | /* |
| 969 | * for now UC MINUS. see comments in ioremap_nocache() |
| 970 | */ |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 971 | return change_page_attr_set(&addr, numpages, |
| 972 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 973 | } |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 974 | |
| 975 | int set_memory_uc(unsigned long addr, int numpages) |
| 976 | { |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 977 | int ret; |
| 978 | |
Suresh Siddha | de33c44 | 2008-04-25 17:07:22 -0700 | [diff] [blame] | 979 | /* |
| 980 | * for now UC MINUS. see comments in ioremap_nocache() |
| 981 | */ |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 982 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
| 983 | _PAGE_CACHE_UC_MINUS, NULL); |
| 984 | if (ret) |
| 985 | goto out_err; |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 986 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 987 | ret = _set_memory_uc(addr, numpages); |
| 988 | if (ret) |
| 989 | goto out_free; |
| 990 | |
| 991 | return 0; |
| 992 | |
| 993 | out_free: |
| 994 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
| 995 | out_err: |
| 996 | return ret; |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 997 | } |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 998 | EXPORT_SYMBOL(set_memory_uc); |
| 999 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1000 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
| 1001 | { |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1002 | int i, j; |
| 1003 | int ret; |
| 1004 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1005 | /* |
| 1006 | * for now UC MINUS. see comments in ioremap_nocache() |
| 1007 | */ |
| 1008 | for (i = 0; i < addrinarray; i++) { |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1009 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
| 1010 | _PAGE_CACHE_UC_MINUS, NULL); |
| 1011 | if (ret) |
| 1012 | goto out_free; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1013 | } |
| 1014 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1015 | ret = change_page_attr_set(addr, addrinarray, |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1016 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1017 | if (ret) |
| 1018 | goto out_free; |
Rene Herman | c5e147c | 2008-08-22 01:02:20 +0200 | [diff] [blame] | 1019 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1020 | return 0; |
| 1021 | |
| 1022 | out_free: |
| 1023 | for (j = 0; j < i; j++) |
| 1024 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); |
| 1025 | |
| 1026 | return ret; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1027 | } |
| 1028 | EXPORT_SYMBOL(set_memory_array_uc); |
| 1029 | |
venkatesh.pallipadi@intel.com | ef354af | 2008-03-18 17:00:23 -0700 | [diff] [blame] | 1030 | int _set_memory_wc(unsigned long addr, int numpages) |
| 1031 | { |
venkatesh.pallipadi@intel.com | 3869c4a | 2009-04-09 14:26:50 -0700 | [diff] [blame] | 1032 | int ret; |
Pallipadi, Venkatesh | bdc6340 | 2009-07-30 14:43:19 -0700 | [diff] [blame] | 1033 | unsigned long addr_copy = addr; |
| 1034 | |
venkatesh.pallipadi@intel.com | 3869c4a | 2009-04-09 14:26:50 -0700 | [diff] [blame] | 1035 | ret = change_page_attr_set(&addr, numpages, |
| 1036 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); |
venkatesh.pallipadi@intel.com | 3869c4a | 2009-04-09 14:26:50 -0700 | [diff] [blame] | 1037 | if (!ret) { |
Pallipadi, Venkatesh | bdc6340 | 2009-07-30 14:43:19 -0700 | [diff] [blame] | 1038 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
| 1039 | __pgprot(_PAGE_CACHE_WC), |
| 1040 | __pgprot(_PAGE_CACHE_MASK), |
| 1041 | 0, 0, NULL); |
venkatesh.pallipadi@intel.com | 3869c4a | 2009-04-09 14:26:50 -0700 | [diff] [blame] | 1042 | } |
| 1043 | return ret; |
venkatesh.pallipadi@intel.com | ef354af | 2008-03-18 17:00:23 -0700 | [diff] [blame] | 1044 | } |
| 1045 | |
| 1046 | int set_memory_wc(unsigned long addr, int numpages) |
| 1047 | { |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1048 | int ret; |
| 1049 | |
Andreas Herrmann | 499f8f8 | 2008-06-10 16:06:21 +0200 | [diff] [blame] | 1050 | if (!pat_enabled) |
venkatesh.pallipadi@intel.com | ef354af | 2008-03-18 17:00:23 -0700 | [diff] [blame] | 1051 | return set_memory_uc(addr, numpages); |
| 1052 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1053 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
| 1054 | _PAGE_CACHE_WC, NULL); |
| 1055 | if (ret) |
| 1056 | goto out_err; |
venkatesh.pallipadi@intel.com | ef354af | 2008-03-18 17:00:23 -0700 | [diff] [blame] | 1057 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1058 | ret = _set_memory_wc(addr, numpages); |
| 1059 | if (ret) |
| 1060 | goto out_free; |
| 1061 | |
| 1062 | return 0; |
| 1063 | |
| 1064 | out_free: |
| 1065 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
| 1066 | out_err: |
| 1067 | return ret; |
venkatesh.pallipadi@intel.com | ef354af | 2008-03-18 17:00:23 -0700 | [diff] [blame] | 1068 | } |
| 1069 | EXPORT_SYMBOL(set_memory_wc); |
| 1070 | |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 1071 | int _set_memory_wb(unsigned long addr, int numpages) |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1072 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1073 | return change_page_attr_clear(&addr, numpages, |
| 1074 | __pgprot(_PAGE_CACHE_MASK), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1075 | } |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 1076 | |
| 1077 | int set_memory_wb(unsigned long addr, int numpages) |
| 1078 | { |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1079 | int ret; |
| 1080 | |
| 1081 | ret = _set_memory_wb(addr, numpages); |
| 1082 | if (ret) |
| 1083 | return ret; |
| 1084 | |
venkatesh.pallipadi@intel.com | c15238d | 2008-08-20 16:45:51 -0700 | [diff] [blame] | 1085 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1086 | return 0; |
venkatesh.pallipadi@intel.com | 1219333 | 2008-03-18 17:00:18 -0700 | [diff] [blame] | 1087 | } |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1088 | EXPORT_SYMBOL(set_memory_wb); |
| 1089 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1090 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
| 1091 | { |
| 1092 | int i; |
venkatesh.pallipadi@intel.com | a5593e0 | 2009-04-09 14:26:48 -0700 | [diff] [blame] | 1093 | int ret; |
| 1094 | |
| 1095 | ret = change_page_attr_clear(addr, addrinarray, |
| 1096 | __pgprot(_PAGE_CACHE_MASK), 1); |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1097 | if (ret) |
| 1098 | return ret; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1099 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1100 | for (i = 0; i < addrinarray; i++) |
| 1101 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); |
Rene Herman | c5e147c | 2008-08-22 01:02:20 +0200 | [diff] [blame] | 1102 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1103 | return 0; |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1104 | } |
| 1105 | EXPORT_SYMBOL(set_memory_array_wb); |
| 1106 | |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1107 | int set_memory_x(unsigned long addr, int numpages) |
| 1108 | { |
H. Peter Anvin | 583140a | 2009-11-13 15:28:15 -0800 | [diff] [blame] | 1109 | if (!(__supported_pte_mask & _PAGE_NX)) |
| 1110 | return 0; |
| 1111 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1112 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1113 | } |
| 1114 | EXPORT_SYMBOL(set_memory_x); |
| 1115 | |
| 1116 | int set_memory_nx(unsigned long addr, int numpages) |
| 1117 | { |
H. Peter Anvin | 583140a | 2009-11-13 15:28:15 -0800 | [diff] [blame] | 1118 | if (!(__supported_pte_mask & _PAGE_NX)) |
| 1119 | return 0; |
| 1120 | |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1121 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1122 | } |
| 1123 | EXPORT_SYMBOL(set_memory_nx); |
| 1124 | |
| 1125 | int set_memory_ro(unsigned long addr, int numpages) |
| 1126 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1127 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1128 | } |
Bruce Allan | a03352d | 2008-09-29 20:19:22 -0700 | [diff] [blame] | 1129 | EXPORT_SYMBOL_GPL(set_memory_ro); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1130 | |
| 1131 | int set_memory_rw(unsigned long addr, int numpages) |
| 1132 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1133 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1134 | } |
Bruce Allan | a03352d | 2008-09-29 20:19:22 -0700 | [diff] [blame] | 1135 | EXPORT_SYMBOL_GPL(set_memory_rw); |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1136 | |
| 1137 | int set_memory_np(unsigned long addr, int numpages) |
| 1138 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1139 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1140 | } |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1141 | |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 1142 | int set_memory_4k(unsigned long addr, int numpages) |
| 1143 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1144 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
venkatesh.pallipadi@intel.com | 9ae2847 | 2009-03-19 14:51:14 -0700 | [diff] [blame] | 1145 | __pgprot(0), 1, 0, NULL); |
Andi Kleen | c9caa02 | 2008-03-12 03:53:29 +0100 | [diff] [blame] | 1146 | } |
| 1147 | |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1148 | int set_pages_uc(struct page *page, int numpages) |
| 1149 | { |
| 1150 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1151 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1152 | return set_memory_uc(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1153 | } |
| 1154 | EXPORT_SYMBOL(set_pages_uc); |
| 1155 | |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1156 | int set_pages_array_uc(struct page **pages, int addrinarray) |
| 1157 | { |
| 1158 | unsigned long start; |
| 1159 | unsigned long end; |
| 1160 | int i; |
| 1161 | int free_idx; |
| 1162 | |
| 1163 | for (i = 0; i < addrinarray; i++) { |
Thomas Hellstrom | 8523acf | 2009-08-03 09:25:45 +0200 | [diff] [blame] | 1164 | if (PageHighMem(pages[i])) |
| 1165 | continue; |
| 1166 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1167 | end = start + PAGE_SIZE; |
| 1168 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) |
| 1169 | goto err_out; |
| 1170 | } |
| 1171 | |
| 1172 | if (cpa_set_pages_array(pages, addrinarray, |
| 1173 | __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) { |
| 1174 | return 0; /* Success */ |
| 1175 | } |
| 1176 | err_out: |
| 1177 | free_idx = i; |
| 1178 | for (i = 0; i < free_idx; i++) { |
Thomas Hellstrom | 8523acf | 2009-08-03 09:25:45 +0200 | [diff] [blame] | 1179 | if (PageHighMem(pages[i])) |
| 1180 | continue; |
| 1181 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1182 | end = start + PAGE_SIZE; |
| 1183 | free_memtype(start, end); |
| 1184 | } |
| 1185 | return -EINVAL; |
| 1186 | } |
| 1187 | EXPORT_SYMBOL(set_pages_array_uc); |
| 1188 | |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1189 | int set_pages_wb(struct page *page, int numpages) |
| 1190 | { |
| 1191 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1192 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1193 | return set_memory_wb(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1194 | } |
| 1195 | EXPORT_SYMBOL(set_pages_wb); |
| 1196 | |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1197 | int set_pages_array_wb(struct page **pages, int addrinarray) |
| 1198 | { |
| 1199 | int retval; |
| 1200 | unsigned long start; |
| 1201 | unsigned long end; |
| 1202 | int i; |
| 1203 | |
| 1204 | retval = cpa_clear_pages_array(pages, addrinarray, |
| 1205 | __pgprot(_PAGE_CACHE_MASK)); |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1206 | if (retval) |
| 1207 | return retval; |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1208 | |
| 1209 | for (i = 0; i < addrinarray; i++) { |
Thomas Hellstrom | 8523acf | 2009-08-03 09:25:45 +0200 | [diff] [blame] | 1210 | if (PageHighMem(pages[i])) |
| 1211 | continue; |
| 1212 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1213 | end = start + PAGE_SIZE; |
| 1214 | free_memtype(start, end); |
| 1215 | } |
| 1216 | |
venkatesh.pallipadi@intel.com | 9fa3ab3 | 2009-04-09 14:26:49 -0700 | [diff] [blame] | 1217 | return 0; |
venkatesh.pallipadi@intel.com | 0f35075 | 2009-03-19 14:51:15 -0700 | [diff] [blame] | 1218 | } |
| 1219 | EXPORT_SYMBOL(set_pages_array_wb); |
| 1220 | |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1221 | int set_pages_x(struct page *page, int numpages) |
| 1222 | { |
| 1223 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1224 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1225 | return set_memory_x(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1226 | } |
| 1227 | EXPORT_SYMBOL(set_pages_x); |
| 1228 | |
| 1229 | int set_pages_nx(struct page *page, int numpages) |
| 1230 | { |
| 1231 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1232 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1233 | return set_memory_nx(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1234 | } |
| 1235 | EXPORT_SYMBOL(set_pages_nx); |
| 1236 | |
| 1237 | int set_pages_ro(struct page *page, int numpages) |
| 1238 | { |
| 1239 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1240 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1241 | return set_memory_ro(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1242 | } |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1243 | |
| 1244 | int set_pages_rw(struct page *page, int numpages) |
| 1245 | { |
| 1246 | unsigned long addr = (unsigned long)page_address(page); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1247 | |
Thomas Gleixner | d7c8f21 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1248 | return set_memory_rw(addr, numpages); |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1249 | } |
Arjan van de Ven | 75cbade | 2008-01-30 13:34:06 +0100 | [diff] [blame] | 1250 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1251 | #ifdef CONFIG_DEBUG_PAGEALLOC |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1252 | |
| 1253 | static int __set_pages_p(struct page *page, int numpages) |
| 1254 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1255 | unsigned long tempaddr = (unsigned long) page_address(page); |
| 1256 | struct cpa_data cpa = { .vaddr = &tempaddr, |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 1257 | .numpages = numpages, |
| 1258 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1259 | .mask_clr = __pgprot(0), |
| 1260 | .flags = 0}; |
Thomas Gleixner | 72932c7 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 1261 | |
Suresh Siddha | 55121b4 | 2008-09-23 14:00:40 -0700 | [diff] [blame] | 1262 | /* |
| 1263 | * No alias checking needed for setting present flag. otherwise, |
| 1264 | * we may need to break large pages for 64-bit kernel text |
| 1265 | * mappings (this adds to complexity if we want to do this from |
| 1266 | * atomic context especially). Let's keep it simple! |
| 1267 | */ |
| 1268 | return __change_page_attr_set_clr(&cpa, 0); |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1269 | } |
| 1270 | |
| 1271 | static int __set_pages_np(struct page *page, int numpages) |
| 1272 | { |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1273 | unsigned long tempaddr = (unsigned long) page_address(page); |
| 1274 | struct cpa_data cpa = { .vaddr = &tempaddr, |
Thomas Gleixner | 72e458d | 2008-02-04 16:48:07 +0100 | [diff] [blame] | 1275 | .numpages = numpages, |
| 1276 | .mask_set = __pgprot(0), |
Shaohua Li | d75586a | 2008-08-21 10:46:06 +0800 | [diff] [blame] | 1277 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
| 1278 | .flags = 0}; |
Thomas Gleixner | 72932c7 | 2008-01-30 13:34:08 +0100 | [diff] [blame] | 1279 | |
Suresh Siddha | 55121b4 | 2008-09-23 14:00:40 -0700 | [diff] [blame] | 1280 | /* |
| 1281 | * No alias checking needed for setting not present flag. otherwise, |
| 1282 | * we may need to break large pages for 64-bit kernel text |
| 1283 | * mappings (this adds to complexity if we want to do this from |
| 1284 | * atomic context especially). Let's keep it simple! |
| 1285 | */ |
| 1286 | return __change_page_attr_set_clr(&cpa, 0); |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1287 | } |
| 1288 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | void kernel_map_pages(struct page *page, int numpages, int enable) |
| 1290 | { |
| 1291 | if (PageHighMem(page)) |
| 1292 | return; |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 1293 | if (!enable) { |
Ingo Molnar | f9b8404 | 2006-06-27 02:54:49 -0700 | [diff] [blame] | 1294 | debug_check_no_locks_freed(page_address(page), |
| 1295 | numpages * PAGE_SIZE); |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 1296 | } |
Ingo Molnar | de5097c | 2006-01-09 15:59:21 -0800 | [diff] [blame] | 1297 | |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 1298 | /* |
Ingo Molnar | 12d6f21 | 2008-01-30 13:33:58 +0100 | [diff] [blame] | 1299 | * If page allocator is not up yet then do not call c_p_a(): |
| 1300 | */ |
| 1301 | if (!debug_pagealloc_enabled) |
| 1302 | return; |
| 1303 | |
| 1304 | /* |
Ingo Molnar | f8d8406 | 2008-02-13 14:09:53 +0100 | [diff] [blame] | 1305 | * The return value is ignored as the calls cannot fail. |
Suresh Siddha | 55121b4 | 2008-09-23 14:00:40 -0700 | [diff] [blame] | 1306 | * Large pages for identity mappings are not used at boot time |
| 1307 | * and hence no memory allocations during large page split. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1308 | */ |
Ingo Molnar | f62d0f0 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1309 | if (enable) |
| 1310 | __set_pages_p(page, numpages); |
| 1311 | else |
| 1312 | __set_pages_np(page, numpages); |
Ingo Molnar | 9f4c815 | 2008-01-30 13:33:41 +0100 | [diff] [blame] | 1313 | |
| 1314 | /* |
Ingo Molnar | e4b71dc | 2008-01-30 13:34:04 +0100 | [diff] [blame] | 1315 | * We should perform an IPI and flush all tlbs, |
| 1316 | * but that can deadlock->flush only current cpu: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | */ |
| 1318 | __flush_tlb_all(); |
| 1319 | } |
Rafael J. Wysocki | 8a235ef | 2008-02-20 01:47:44 +0100 | [diff] [blame] | 1320 | |
| 1321 | #ifdef CONFIG_HIBERNATION |
| 1322 | |
| 1323 | bool kernel_page_present(struct page *page) |
| 1324 | { |
| 1325 | unsigned int level; |
| 1326 | pte_t *pte; |
| 1327 | |
| 1328 | if (PageHighMem(page)) |
| 1329 | return false; |
| 1330 | |
| 1331 | pte = lookup_address((unsigned long)page_address(page), &level); |
| 1332 | return (pte_val(*pte) & _PAGE_PRESENT); |
| 1333 | } |
| 1334 | |
| 1335 | #endif /* CONFIG_HIBERNATION */ |
| 1336 | |
| 1337 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
Arjan van de Ven | d1028a1 | 2008-01-30 13:34:07 +0100 | [diff] [blame] | 1338 | |
| 1339 | /* |
| 1340 | * The testcases use internal knowledge of the implementation that shouldn't |
| 1341 | * be exposed to the rest of the kernel. Include these directly here. |
| 1342 | */ |
| 1343 | #ifdef CONFIG_CPA_DEBUG |
| 1344 | #include "pageattr-test.c" |
| 1345 | #endif |