Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 28 | #include <linux/async.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 30 | #include <linux/hdmi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/i915_drm.h> |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_crtc_helper.h> |
| 35 | #include <drm/drm_fb_helper.h> |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 36 | #include <drm/drm_dp_mst_helper.h> |
Gustavo Padovan | eeca778 | 2014-09-05 17:04:46 -0300 | [diff] [blame] | 37 | #include <drm/drm_rect.h> |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 38 | |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 39 | /** |
| 40 | * _wait_for - magic (register) wait macro |
| 41 | * |
| 42 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| 43 | * contexts. Note that it's important that we check the condition again after |
| 44 | * having timed out, since the timeout could be due to preemption or similar and |
| 45 | * we've never had a chance to check the condition before the timeout. |
| 46 | */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 47 | #define _wait_for(COND, MS, W) ({ \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 48 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 49 | int ret__ = 0; \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 50 | while (!(COND)) { \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 51 | if (time_after(jiffies, timeout__)) { \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 52 | if (!(COND)) \ |
| 53 | ret__ = -ETIMEDOUT; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 54 | break; \ |
| 55 | } \ |
Ben Widawsky | 0cc2764 | 2012-09-01 22:59:48 -0700 | [diff] [blame] | 56 | if (W && drm_can_sleep()) { \ |
| 57 | msleep(W); \ |
| 58 | } else { \ |
| 59 | cpu_relax(); \ |
| 60 | } \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 61 | } \ |
| 62 | ret__; \ |
| 63 | }) |
| 64 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 65 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 66 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
Daniel Vetter | 6effa33 | 2013-03-28 11:31:04 +0100 | [diff] [blame] | 67 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
| 68 | DIV_ROUND_UP((US), 1000), 0) |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 69 | |
Jani Nikula | 49938ac | 2014-01-10 17:10:20 +0200 | [diff] [blame] | 70 | #define KHz(x) (1000 * (x)) |
| 71 | #define MHz(x) KHz(1000 * (x)) |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 72 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 73 | /* |
| 74 | * Display related stuff |
| 75 | */ |
| 76 | |
| 77 | /* store information about an Ixxx DVO */ |
| 78 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 79 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 80 | #define MAX_OUTPUTS 6 |
| 81 | /* maximum connectors per crtcs in the mode set */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 82 | |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 83 | /* Maximum cursor sizes */ |
| 84 | #define GEN2_CURSOR_WIDTH 64 |
| 85 | #define GEN2_CURSOR_HEIGHT 64 |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 86 | #define MAX_CURSOR_WIDTH 256 |
| 87 | #define MAX_CURSOR_HEIGHT 256 |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 88 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 89 | #define INTEL_I2C_BUS_DVO 1 |
| 90 | #define INTEL_I2C_BUS_SDVO 2 |
| 91 | |
| 92 | /* these are outputs from the chip - integrated only |
| 93 | external chips are via DVO or SDVO output */ |
| 94 | #define INTEL_OUTPUT_UNUSED 0 |
| 95 | #define INTEL_OUTPUT_ANALOG 1 |
| 96 | #define INTEL_OUTPUT_DVO 2 |
| 97 | #define INTEL_OUTPUT_SDVO 3 |
| 98 | #define INTEL_OUTPUT_LVDS 4 |
| 99 | #define INTEL_OUTPUT_TVOUT 5 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 100 | #define INTEL_OUTPUT_HDMI 6 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 101 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 102 | #define INTEL_OUTPUT_EDP 8 |
Jani Nikula | 72ffa33 | 2013-08-27 15:12:17 +0300 | [diff] [blame] | 103 | #define INTEL_OUTPUT_DSI 9 |
| 104 | #define INTEL_OUTPUT_UNKNOWN 10 |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 105 | #define INTEL_OUTPUT_DP_MST 11 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 106 | |
| 107 | #define INTEL_DVO_CHIP_NONE 0 |
| 108 | #define INTEL_DVO_CHIP_LVDS 1 |
| 109 | #define INTEL_DVO_CHIP_TMDS 2 |
| 110 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 111 | |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 112 | #define INTEL_DSI_VIDEO_MODE 0 |
| 113 | #define INTEL_DSI_COMMAND_MODE 1 |
Jani Nikula | 72ffa33 | 2013-08-27 15:12:17 +0300 | [diff] [blame] | 114 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 115 | struct intel_framebuffer { |
| 116 | struct drm_framebuffer base; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 117 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 118 | }; |
| 119 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 120 | struct intel_fbdev { |
| 121 | struct drm_fb_helper helper; |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 122 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 123 | struct list_head fbdev_list; |
| 124 | struct drm_display_mode *our_mode; |
Jesse Barnes | d978ef1 | 2014-03-07 08:57:51 -0800 | [diff] [blame] | 125 | int preferred_bpp; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 126 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 127 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 128 | struct intel_encoder { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 129 | struct drm_encoder base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 130 | /* |
| 131 | * The new crtc this encoder will be driven from. Only differs from |
| 132 | * base->crtc while a modeset is in progress. |
| 133 | */ |
| 134 | struct intel_crtc *new_crtc; |
| 135 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 136 | int type; |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 137 | unsigned int cloneable; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 138 | bool connectors_active; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 139 | void (*hot_plug)(struct intel_encoder *); |
Daniel Vetter | 7ae8923 | 2013-03-27 00:44:52 +0100 | [diff] [blame] | 140 | bool (*compute_config)(struct intel_encoder *, |
| 141 | struct intel_crtc_config *); |
Daniel Vetter | dafd226 | 2012-11-26 17:22:07 +0100 | [diff] [blame] | 142 | void (*pre_pll_enable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8 | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 143 | void (*pre_enable)(struct intel_encoder *); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 144 | void (*enable)(struct intel_encoder *); |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 145 | void (*mode_set)(struct intel_encoder *intel_encoder); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 146 | void (*disable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8 | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 147 | void (*post_disable)(struct intel_encoder *); |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 148 | /* Read out the current hw state of this connector, returning true if |
| 149 | * the encoder is active. If the encoder is enabled it also set the pipe |
| 150 | * it is connected to in the pipe parameter. */ |
| 151 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 152 | /* Reconstructs the equivalent mode flags for the current hardware |
Daniel Vetter | fdafa9e | 2013-06-12 11:47:24 +0200 | [diff] [blame] | 153 | * state. This must be called _after_ display->get_pipe_config has |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 154 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
| 155 | * be set correctly before calling this function. */ |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 156 | void (*get_config)(struct intel_encoder *, |
| 157 | struct intel_crtc_config *pipe_config); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 158 | /* |
| 159 | * Called during system suspend after all pending requests for the |
| 160 | * encoder are flushed (for example for DP AUX transactions) and |
| 161 | * device interrupts are disabled. |
| 162 | */ |
| 163 | void (*suspend)(struct intel_encoder *); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 164 | int crtc_mask; |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 165 | enum hpd_pin hpd_pin; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 166 | }; |
| 167 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 168 | struct intel_panel { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 169 | struct drm_display_mode *fixed_mode; |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 170 | struct drm_display_mode *downclock_mode; |
Jani Nikula | 4d89152 | 2012-10-26 12:03:59 +0300 | [diff] [blame] | 171 | int fitting_mode; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 172 | |
| 173 | /* backlight */ |
| 174 | struct { |
Jani Nikula | c91c9f3 | 2013-11-08 16:48:55 +0200 | [diff] [blame] | 175 | bool present; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 176 | u32 level; |
Jani Nikula | 6dda730 | 2014-06-24 18:27:40 +0300 | [diff] [blame] | 177 | u32 min; |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 178 | u32 max; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 179 | bool enabled; |
Jani Nikula | 636baeb | 2013-11-08 16:49:02 +0200 | [diff] [blame] | 180 | bool combination_mode; /* gen 2/4 only */ |
| 181 | bool active_low_pwm; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 182 | struct backlight_device *device; |
| 183 | } backlight; |
Jani Nikula | ab656bb | 2014-08-13 12:10:12 +0300 | [diff] [blame] | 184 | |
| 185 | void (*backlight_power)(struct intel_connector *, bool enable); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 186 | }; |
| 187 | |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 188 | struct intel_connector { |
| 189 | struct drm_connector base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 190 | /* |
| 191 | * The fixed encoder this connector is connected to. |
| 192 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 193 | struct intel_encoder *encoder; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * The new encoder this connector will be driven. Only differs from |
| 197 | * encoder while a modeset is in progress. |
| 198 | */ |
| 199 | struct intel_encoder *new_encoder; |
| 200 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 201 | /* Reads out the current hw, returning true if the connector is enabled |
| 202 | * and active (i.e. dpms ON state). */ |
| 203 | bool (*get_hw_state)(struct intel_connector *); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 204 | |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 205 | /* |
| 206 | * Removes all interfaces through which the connector is accessible |
| 207 | * - like sysfs, debugfs entries -, so that no new operations can be |
| 208 | * started on the connector. Also makes sure all currently pending |
| 209 | * operations finish before returing. |
| 210 | */ |
| 211 | void (*unregister)(struct intel_connector *); |
| 212 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 213 | /* Panel info for eDP and LVDS */ |
| 214 | struct intel_panel panel; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 215 | |
| 216 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| 217 | struct edid *edid; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 218 | struct edid *detect_edid; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 219 | |
| 220 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| 221 | state of connector->polled in case hotplug storm detection changes it */ |
| 222 | u8 polled; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 223 | |
| 224 | void *port; /* store this opaque as its illegal to dereference it */ |
| 225 | |
| 226 | struct intel_dp *mst_port; |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 227 | }; |
| 228 | |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 229 | typedef struct dpll { |
| 230 | /* given values */ |
| 231 | int n; |
| 232 | int m1, m2; |
| 233 | int p1, p2; |
| 234 | /* derived values */ |
| 235 | int dot; |
| 236 | int vco; |
| 237 | int m; |
| 238 | int p; |
| 239 | } intel_clock_t; |
| 240 | |
Gustavo Padovan | eeca778 | 2014-09-05 17:04:46 -0300 | [diff] [blame] | 241 | struct intel_plane_state { |
| 242 | struct drm_crtc *crtc; |
| 243 | struct drm_framebuffer *fb; |
| 244 | struct drm_rect src; |
| 245 | struct drm_rect dst; |
| 246 | struct drm_rect clip; |
| 247 | struct drm_rect orig_src; |
| 248 | struct drm_rect orig_dst; |
| 249 | bool visible; |
| 250 | }; |
| 251 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 252 | struct intel_plane_config { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 253 | bool tiled; |
| 254 | int size; |
| 255 | u32 base; |
| 256 | }; |
| 257 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 258 | struct intel_crtc_config { |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 259 | /** |
| 260 | * quirks - bitfield with hw state readout quirks |
| 261 | * |
| 262 | * For various reasons the hw state readout code might not be able to |
| 263 | * completely faithfully read out the current state. These cases are |
| 264 | * tracked with quirk flags so that fastboot and state checker can act |
| 265 | * accordingly. |
| 266 | */ |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 267 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| 268 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 269 | unsigned long quirks; |
| 270 | |
Ville Syrjälä | 5113bc9 | 2013-09-04 18:25:29 +0300 | [diff] [blame] | 271 | /* User requested mode, only valid as a starting point to |
| 272 | * compute adjusted_mode, except in the case of (S)DVO where |
| 273 | * it's also for the output timings of the (S)DVO chip. |
| 274 | * adjusted_mode will then correspond to the S(DVO) chip's |
| 275 | * preferred input timings. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 276 | struct drm_display_mode requested_mode; |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 277 | /* Actual pipe timings ie. what we program into the pipe timing |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 278 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 279 | struct drm_display_mode adjusted_mode; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 280 | |
| 281 | /* Pipe source size (ie. panel fitter input size) |
| 282 | * All planes will be positioned inside this space, |
| 283 | * and get clipped at the edges. */ |
| 284 | int pipe_src_w, pipe_src_h; |
| 285 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 286 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| 287 | * between pch encoders and cpu encoders. */ |
| 288 | bool has_pch_encoder; |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 289 | |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 290 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| 291 | * pipe on Haswell (where we have a special eDP transcoder). */ |
| 292 | enum transcoder cpu_transcoder; |
| 293 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 294 | /* |
| 295 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| 296 | * range fed into the crtcs. |
| 297 | */ |
| 298 | bool limited_color_range; |
| 299 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 300 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| 301 | * accordingly. */ |
| 302 | bool has_dp_encoder; |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 303 | |
Daniel Vetter | 6897b4b | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 304 | /* Whether we should send NULL infoframes. Required for audio. */ |
| 305 | bool has_hdmi_sink; |
| 306 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 307 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
| 308 | * has_dp_encoder is set. */ |
| 309 | bool has_audio; |
| 310 | |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 311 | /* |
| 312 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| 313 | * plane bpp. |
| 314 | */ |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 315 | bool dither; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 316 | |
| 317 | /* Controls for the clock computation, to override various stages. */ |
| 318 | bool clock_set; |
| 319 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 320 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
| 321 | * work correctly, we need to track this at runtime.*/ |
| 322 | bool sdvo_tv_clock; |
| 323 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 324 | /* |
| 325 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| 326 | * required. This is set in the 2nd loop of calling encoder's |
| 327 | * ->compute_config if the first pick doesn't work out. |
| 328 | */ |
| 329 | bool bw_constrained; |
| 330 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 331 | /* Settings for the intel dpll used on pretty much everything but |
| 332 | * haswell. */ |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 333 | struct dpll dpll; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 334 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 335 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
| 336 | enum intel_dpll_id shared_dpll; |
| 337 | |
Daniel Vetter | de7cfc6 | 2014-06-25 22:01:54 +0300 | [diff] [blame] | 338 | /* PORT_CLK_SEL for DDI ports. */ |
| 339 | uint32_t ddi_pll_sel; |
| 340 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 341 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| 342 | struct intel_dpll_hw_state dpll_hw_state; |
| 343 | |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 344 | int pipe_bpp; |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 345 | struct intel_link_m_n dp_m_n; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 346 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 347 | /* m2_n2 for eDP downclock */ |
| 348 | struct intel_link_m_n dp_m2_n2; |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 349 | bool has_drrs; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 350 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 351 | /* |
| 352 | * Frequence the dpll for the port should run at. Differs from the |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 353 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 354 | * already multiplied by pixel_multiplier. |
Daniel Vetter | df92b1e | 2013-03-28 10:41:58 +0100 | [diff] [blame] | 355 | */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 356 | int port_clock; |
| 357 | |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 358 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| 359 | unsigned pixel_multiplier; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 360 | |
| 361 | /* Panel fitter controls for gen2-gen4 + VLV */ |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 362 | struct { |
| 363 | u32 control; |
| 364 | u32 pgm_ratios; |
Daniel Vetter | 68fc874 | 2013-04-25 22:52:16 +0200 | [diff] [blame] | 365 | u32 lvds_border_bits; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 366 | } gmch_pfit; |
| 367 | |
| 368 | /* Panel fitter placement and size for Ironlake+ */ |
| 369 | struct { |
| 370 | u32 pos; |
| 371 | u32 size; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 372 | bool enabled; |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 373 | bool force_thru; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 374 | } pch_pfit; |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 375 | |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 376 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 377 | int fdi_lanes; |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 378 | struct intel_link_m_n fdi_m_n; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 379 | |
| 380 | bool ips_enabled; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 381 | |
| 382 | bool double_wide; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 383 | |
| 384 | bool dp_encoder_is_mst; |
| 385 | int pbn; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 386 | }; |
| 387 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 388 | struct intel_pipe_wm { |
| 389 | struct intel_wm_level wm[5]; |
| 390 | uint32_t linetime; |
| 391 | bool fbc_wm_enabled; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 392 | bool pipe_enabled; |
| 393 | bool sprites_enabled; |
| 394 | bool sprites_scaled; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 395 | }; |
| 396 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 397 | struct intel_mmio_flip { |
| 398 | u32 seqno; |
| 399 | u32 ring_id; |
| 400 | }; |
| 401 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 402 | struct intel_crtc { |
| 403 | struct drm_crtc base; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 404 | enum pipe pipe; |
| 405 | enum plane plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 406 | u8 lut_r[256], lut_g[256], lut_b[256]; |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 407 | /* |
| 408 | * Whether the crtc and the connected output pipeline is active. Implies |
| 409 | * that crtc->enabled is set, i.e. the current mode configuration has |
| 410 | * some outputs connected to this crtc. |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 411 | */ |
| 412 | bool active; |
Imre Deak | 6efdf35 | 2013-10-16 17:25:52 +0300 | [diff] [blame] | 413 | unsigned long enabled_power_domains; |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 414 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 415 | bool lowfreq_avail; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 416 | struct intel_overlay *overlay; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 417 | struct intel_unpin_work *unpin_work; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 418 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 419 | atomic_t unpin_work_count; |
| 420 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 421 | /* Display surface base address adjustement for pageflips. Note that on |
| 422 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 423 | * handled in the hw itself (with the TILEOFF register). */ |
| 424 | unsigned long dspaddr_offset; |
| 425 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 426 | struct drm_i915_gem_object *cursor_bo; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 427 | uint32_t cursor_addr; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 428 | int16_t cursor_width, cursor_height; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 429 | uint32_t cursor_cntl; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 430 | uint32_t cursor_size; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 431 | uint32_t cursor_base; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 432 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 433 | struct intel_plane_config plane_config; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 434 | struct intel_crtc_config config; |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 435 | struct intel_crtc_config *new_config; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 436 | bool new_enabled; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 437 | |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 438 | /* reset counter value when the last flip was submitted */ |
| 439 | unsigned int reset_counter; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 440 | |
| 441 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| 442 | bool cpu_fifo_underrun_disabled; |
| 443 | bool pch_fifo_underrun_disabled; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 444 | |
| 445 | /* per-pipe watermark state */ |
| 446 | struct { |
| 447 | /* watermarks currently being used */ |
| 448 | struct intel_pipe_wm active; |
| 449 | } wm; |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 450 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 451 | int scanline_offset; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 452 | struct intel_mmio_flip mmio_flip; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 453 | }; |
| 454 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 455 | struct intel_plane_wm_parameters { |
| 456 | uint32_t horiz_pixels; |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 457 | uint32_t vert_pixels; |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 458 | uint8_t bytes_per_pixel; |
| 459 | bool enabled; |
| 460 | bool scaled; |
| 461 | }; |
| 462 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 463 | struct intel_plane { |
| 464 | struct drm_plane base; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 465 | int plane; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 466 | enum pipe pipe; |
| 467 | struct drm_i915_gem_object *obj; |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 468 | bool can_scale; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 469 | int max_downscale; |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 470 | int crtc_x, crtc_y; |
| 471 | unsigned int crtc_w, crtc_h; |
| 472 | uint32_t src_x, src_y; |
| 473 | uint32_t src_w, src_h; |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 474 | unsigned int rotation; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 475 | |
| 476 | /* Since we need to change the watermarks before/after |
| 477 | * enabling/disabling the planes, we need to store the parameters here |
| 478 | * as the other pieces of the struct may not reflect the values we want |
| 479 | * for the watermark calculations. Currently only Haswell uses this. |
| 480 | */ |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 481 | struct intel_plane_wm_parameters wm; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 482 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 483 | void (*update_plane)(struct drm_plane *plane, |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 484 | struct drm_crtc *crtc, |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 485 | struct drm_framebuffer *fb, |
| 486 | struct drm_i915_gem_object *obj, |
| 487 | int crtc_x, int crtc_y, |
| 488 | unsigned int crtc_w, unsigned int crtc_h, |
| 489 | uint32_t x, uint32_t y, |
| 490 | uint32_t src_w, uint32_t src_h); |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 491 | void (*disable_plane)(struct drm_plane *plane, |
| 492 | struct drm_crtc *crtc); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 493 | int (*update_colorkey)(struct drm_plane *plane, |
| 494 | struct drm_intel_sprite_colorkey *key); |
| 495 | void (*get_colorkey)(struct drm_plane *plane, |
| 496 | struct drm_intel_sprite_colorkey *key); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 497 | }; |
| 498 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 499 | struct intel_watermark_params { |
| 500 | unsigned long fifo_size; |
| 501 | unsigned long max_wm; |
| 502 | unsigned long default_wm; |
| 503 | unsigned long guard_size; |
| 504 | unsigned long cacheline_size; |
| 505 | }; |
| 506 | |
| 507 | struct cxsr_latency { |
| 508 | int is_desktop; |
| 509 | int is_ddr3; |
| 510 | unsigned long fsb_freq; |
| 511 | unsigned long mem_freq; |
| 512 | unsigned long display_sr; |
| 513 | unsigned long display_hpll_disable; |
| 514 | unsigned long cursor_sr; |
| 515 | unsigned long cursor_hpll_disable; |
| 516 | }; |
| 517 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 518 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 519 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 520 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 521 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 522 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
Matt Roper | 155e636 | 2014-07-07 18:21:47 -0700 | [diff] [blame] | 523 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 524 | |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 525 | struct intel_hdmi { |
Paulo Zanoni | b242b7f | 2013-02-18 19:00:26 -0300 | [diff] [blame] | 526 | u32 hdmi_reg; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 527 | int ddc_bus; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 528 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 529 | bool color_range_auto; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 530 | bool has_hdmi_sink; |
| 531 | bool has_audio; |
| 532 | enum hdmi_force_audio force_audio; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 533 | bool rgb_quant_range_selectable; |
Vandana Kannan | 94a11dd | 2014-06-11 11:06:01 +0530 | [diff] [blame] | 534 | enum hdmi_picture_aspect aspect_ratio; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 535 | void (*write_infoframe)(struct drm_encoder *encoder, |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 536 | enum hdmi_infoframe_type type, |
Ville Syrjälä | fff6386 | 2013-12-10 15:19:08 +0200 | [diff] [blame] | 537 | const void *frame, ssize_t len); |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 538 | void (*set_infoframes)(struct drm_encoder *encoder, |
Daniel Vetter | 6897b4b | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 539 | bool enable, |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 540 | struct drm_display_mode *adjusted_mode); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 541 | }; |
| 542 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 543 | struct intel_dp_mst_encoder; |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 544 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 545 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 546 | /** |
| 547 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
| 548 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
| 549 | * parsing for same resolution. |
| 550 | */ |
| 551 | enum edp_drrs_refresh_rate_type { |
| 552 | DRRS_HIGH_RR, |
| 553 | DRRS_LOW_RR, |
| 554 | DRRS_MAX_RR, /* RR count */ |
| 555 | }; |
| 556 | |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 557 | struct intel_dp { |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 558 | uint32_t output_reg; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 559 | uint32_t aux_ch_ctl_reg; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 560 | uint32_t DP; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 561 | bool has_audio; |
| 562 | enum hdmi_force_audio force_audio; |
| 563 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 564 | bool color_range_auto; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 565 | uint8_t link_bw; |
| 566 | uint8_t lane_count; |
| 567 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 568 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 569 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 570 | struct drm_dp_aux aux; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 571 | uint8_t train_set[4]; |
| 572 | int panel_power_up_delay; |
| 573 | int panel_power_down_delay; |
| 574 | int panel_power_cycle_delay; |
| 575 | int backlight_on_delay; |
| 576 | int backlight_off_delay; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 577 | struct delayed_work panel_vdd_work; |
| 578 | bool want_panel_vdd; |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 579 | unsigned long last_power_cycle; |
| 580 | unsigned long last_power_on; |
| 581 | unsigned long last_backlight_off; |
Dave Airlie | 5d42f82 | 2014-08-05 09:04:59 +1000 | [diff] [blame] | 582 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 583 | struct notifier_block edp_notifier; |
| 584 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 585 | /* |
| 586 | * Pipe whose power sequencer is currently locked into |
| 587 | * this port. Only relevant on VLV/CHV. |
| 588 | */ |
| 589 | enum pipe pps_pipe; |
| 590 | |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 591 | bool use_tps3; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 592 | bool can_mst; /* this port supports mst */ |
| 593 | bool is_mst; |
| 594 | int active_mst_links; |
| 595 | /* connector directly attached - won't be use for modeset in mst world */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 596 | struct intel_connector *attached_connector; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 597 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 598 | /* mst connector list */ |
| 599 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
| 600 | struct drm_dp_mst_topology_mgr mst_mgr; |
| 601 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 602 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 603 | /* |
| 604 | * This function returns the value we have to program the AUX_CTL |
| 605 | * register with to kick off an AUX transaction. |
| 606 | */ |
| 607 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
| 608 | bool has_aux_irq, |
| 609 | int send_bytes, |
| 610 | uint32_t aux_clock_divider); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 611 | struct { |
| 612 | enum drrs_support_type type; |
| 613 | enum edp_drrs_refresh_rate_type refresh_rate_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 614 | struct mutex mutex; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 615 | } drrs_state; |
| 616 | |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 617 | }; |
| 618 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 619 | struct intel_digital_port { |
| 620 | struct intel_encoder base; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 621 | enum port port; |
Stéphane Marchesin | bcf53de | 2013-07-12 13:54:41 -0700 | [diff] [blame] | 622 | u32 saved_port_bits; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 623 | struct intel_dp dp; |
| 624 | struct intel_hdmi hdmi; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 625 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 626 | }; |
| 627 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 628 | struct intel_dp_mst_encoder { |
| 629 | struct intel_encoder base; |
| 630 | enum pipe pipe; |
| 631 | struct intel_digital_port *primary; |
| 632 | void *port; /* store this opaque as its illegal to dereference it */ |
| 633 | }; |
| 634 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 635 | static inline int |
| 636 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| 637 | { |
| 638 | switch (dport->port) { |
| 639 | case PORT_B: |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 640 | case PORT_D: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 641 | return DPIO_CH0; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 642 | case PORT_C: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 643 | return DPIO_CH1; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 644 | default: |
| 645 | BUG(); |
| 646 | } |
| 647 | } |
| 648 | |
Chon Ming Lee | eb69b0e | 2014-04-09 13:28:16 +0300 | [diff] [blame] | 649 | static inline int |
| 650 | vlv_pipe_to_channel(enum pipe pipe) |
| 651 | { |
| 652 | switch (pipe) { |
| 653 | case PIPE_A: |
| 654 | case PIPE_C: |
| 655 | return DPIO_CH0; |
| 656 | case PIPE_B: |
| 657 | return DPIO_CH1; |
| 658 | default: |
| 659 | BUG(); |
| 660 | } |
| 661 | } |
| 662 | |
Chris Wilson | f875c15 | 2010-09-09 15:44:14 +0100 | [diff] [blame] | 663 | static inline struct drm_crtc * |
| 664 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 665 | { |
| 666 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 667 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 668 | } |
| 669 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 670 | static inline struct drm_crtc * |
| 671 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 672 | { |
| 673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 674 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 675 | } |
| 676 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 677 | struct intel_unpin_work { |
| 678 | struct work_struct work; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 679 | struct drm_crtc *crtc; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 680 | struct drm_i915_gem_object *old_fb_obj; |
| 681 | struct drm_i915_gem_object *pending_flip_obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 682 | struct drm_pending_vblank_event *event; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 683 | atomic_t pending; |
| 684 | #define INTEL_FLIP_INACTIVE 0 |
| 685 | #define INTEL_FLIP_PENDING 1 |
| 686 | #define INTEL_FLIP_COMPLETE 2 |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 687 | u32 flip_count; |
| 688 | u32 gtt_offset; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 689 | struct intel_engine_cs *flip_queued_ring; |
| 690 | u32 flip_queued_seqno; |
| 691 | int flip_queued_vblank; |
| 692 | int flip_ready_vblank; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 693 | bool enable_stall_check; |
| 694 | }; |
| 695 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 696 | struct intel_set_config { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 697 | struct drm_encoder **save_connector_encoders; |
| 698 | struct drm_crtc **save_encoder_crtcs; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 699 | bool *save_crtc_enabled; |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 700 | |
| 701 | bool fb_changed; |
| 702 | bool mode_changed; |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 703 | }; |
| 704 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 705 | struct intel_load_detect_pipe { |
| 706 | struct drm_framebuffer *release_fb; |
| 707 | bool load_detect_temp; |
| 708 | int dpms_mode; |
| 709 | }; |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 710 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 711 | static inline struct intel_encoder * |
| 712 | intel_attached_encoder(struct drm_connector *connector) |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 713 | { |
| 714 | return to_intel_connector(connector)->encoder; |
| 715 | } |
| 716 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 717 | static inline struct intel_digital_port * |
| 718 | enc_to_dig_port(struct drm_encoder *encoder) |
| 719 | { |
| 720 | return container_of(encoder, struct intel_digital_port, base.base); |
| 721 | } |
| 722 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 723 | static inline struct intel_dp_mst_encoder * |
| 724 | enc_to_mst(struct drm_encoder *encoder) |
| 725 | { |
| 726 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
| 727 | } |
| 728 | |
Imre Deak | 9ff8c9b | 2013-05-08 13:14:02 +0300 | [diff] [blame] | 729 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 730 | { |
| 731 | return &enc_to_dig_port(encoder)->dp; |
| 732 | } |
| 733 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 734 | static inline struct intel_digital_port * |
| 735 | dp_to_dig_port(struct intel_dp *intel_dp) |
| 736 | { |
| 737 | return container_of(intel_dp, struct intel_digital_port, dp); |
| 738 | } |
| 739 | |
| 740 | static inline struct intel_digital_port * |
| 741 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| 742 | { |
| 743 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 744 | } |
| 745 | |
Damien Lespiau | 6af31a6 | 2014-03-28 00:18:33 +0530 | [diff] [blame] | 746 | /* |
| 747 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
| 748 | * (primary plane). This doesn't count the cursor plane then. |
| 749 | */ |
| 750 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
| 751 | { |
| 752 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
| 753 | } |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 754 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 755 | /* i915_irq.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 756 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 757 | enum pipe pipe, bool enable); |
| 758 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 759 | enum transcoder pch_transcoder, |
| 760 | bool enable); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 761 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 762 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 763 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 764 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 765 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 766 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 767 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev); |
| 768 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev); |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 769 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
| 770 | { |
| 771 | /* |
| 772 | * We only use drm_irq_uninstall() at unload and VT switch, so |
| 773 | * this is the only thing we need to check. |
| 774 | */ |
| 775 | return !dev_priv->pm._irqs_disabled; |
| 776 | } |
| 777 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 778 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
Ville Syrjälä | 56b80e1 | 2014-05-16 19:40:22 +0300 | [diff] [blame] | 779 | void i9xx_check_fifo_underruns(struct drm_device *dev); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 780 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 781 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 782 | /* intel_crt.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 783 | void intel_crt_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 784 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 785 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 786 | /* intel_ddi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 787 | void intel_prepare_ddi(struct drm_device *dev); |
| 788 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
| 789 | void intel_ddi_init(struct drm_device *dev, enum port port); |
| 790 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
| 791 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
| 792 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| 793 | void intel_ddi_pll_init(struct drm_device *dev); |
| 794 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| 795 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 796 | enum transcoder cpu_transcoder); |
| 797 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 798 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 799 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 800 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| 801 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| 802 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 803 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| 804 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 805 | struct intel_crtc_config *pipe_config); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 806 | |
Dave Airlie | 44905a2 | 2014-05-02 13:36:43 +1000 | [diff] [blame] | 807 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 808 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
| 809 | struct intel_crtc_config *pipe_config); |
| 810 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 811 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 812 | /* intel_frontbuffer.c */ |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 813 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| 814 | struct intel_engine_cs *ring); |
| 815 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| 816 | unsigned frontbuffer_bits); |
| 817 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| 818 | unsigned frontbuffer_bits); |
| 819 | void intel_frontbuffer_flush(struct drm_device *dev, |
| 820 | unsigned frontbuffer_bits); |
| 821 | /** |
Daniel Vetter | 5c323b2 | 2014-09-30 22:10:53 +0200 | [diff] [blame^] | 822 | * intel_frontbuffer_flip - synchronous frontbuffer flip |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 823 | * @dev: DRM device |
| 824 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 825 | * |
| 826 | * This function gets called after scheduling a flip on @obj. This is for |
| 827 | * synchronous plane updates which will happen on the next vblank and which will |
| 828 | * not get delayed by pending gpu rendering. |
| 829 | * |
| 830 | * Can be called without any locks held. |
| 831 | */ |
| 832 | static inline |
| 833 | void intel_frontbuffer_flip(struct drm_device *dev, |
| 834 | unsigned frontbuffer_bits) |
| 835 | { |
| 836 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
| 837 | } |
| 838 | |
| 839 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 840 | |
| 841 | |
| 842 | /* intel_display.c */ |
| 843 | const char *intel_output_name(int output); |
| 844 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
| 845 | int intel_pch_rawclk(struct drm_device *dev); |
| 846 | void intel_mark_busy(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 847 | void intel_mark_idle(struct drm_device *dev); |
| 848 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 849 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 850 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| 851 | void intel_encoder_destroy(struct drm_encoder *encoder); |
| 852 | void intel_connector_dpms(struct drm_connector *, int mode); |
| 853 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
| 854 | void intel_modeset_check_state(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 855 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 856 | struct intel_digital_port *port); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 857 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 858 | struct intel_encoder *encoder); |
| 859 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| 860 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 861 | struct drm_crtc *crtc); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 862 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 863 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 864 | struct drm_file *file_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 865 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 866 | enum pipe pipe); |
Daniel Vetter | 4f905cf9 | 2014-09-15 14:12:21 +0200 | [diff] [blame] | 867 | static inline void |
| 868 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
| 869 | { |
| 870 | drm_wait_one_vblank(dev, pipe); |
| 871 | } |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 872 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 873 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 874 | struct intel_digital_port *dport); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 875 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 876 | struct drm_display_mode *mode, |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 877 | struct intel_load_detect_pipe *old, |
| 878 | struct drm_modeset_acquire_ctx *ctx); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 879 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 880 | struct intel_load_detect_pipe *old); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 881 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| 882 | struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 883 | struct intel_engine_cs *pipelined); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 884 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 885 | struct drm_framebuffer * |
| 886 | __intel_framebuffer_create(struct drm_device *dev, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 887 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 888 | struct drm_i915_gem_object *obj); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 889 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| 890 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| 891 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 892 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 893 | |
| 894 | /* shared dpll functions */ |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 895 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
| 896 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 897 | struct intel_shared_dpll *pll, |
| 898 | bool state); |
| 899 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 900 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 901 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
| 902 | void intel_put_shared_dpll(struct intel_crtc *crtc); |
| 903 | |
| 904 | /* modesetting asserts */ |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 905 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 906 | enum pipe pipe); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 907 | void assert_pll(struct drm_i915_private *dev_priv, |
| 908 | enum pipe pipe, bool state); |
| 909 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 910 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 911 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 912 | enum pipe pipe, bool state); |
| 913 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
| 914 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 915 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 916 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 917 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 918 | void intel_write_eld(struct drm_encoder *encoder, |
| 919 | struct drm_display_mode *mode); |
| 920 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 921 | unsigned int tiling_mode, |
| 922 | unsigned int bpp, |
| 923 | unsigned int pitch); |
| 924 | void intel_display_handle_reset(struct drm_device *dev); |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 925 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
| 926 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 927 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 928 | struct intel_crtc_config *pipe_config); |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 929 | void intel_dp_set_m_n(struct intel_crtc *crtc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 930 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 931 | void |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 932 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
| 933 | int dotclock); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 934 | bool intel_crtc_active(struct drm_crtc *crtc); |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 935 | void hsw_enable_ips(struct intel_crtc *crtc); |
| 936 | void hsw_disable_ips(struct intel_crtc *crtc); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 937 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 938 | enum intel_display_power_domain |
| 939 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 940 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 941 | struct intel_crtc_config *pipe_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 942 | int intel_format_to_fourcc(int format); |
Ville Syrjälä | 46a55d3 | 2014-05-21 14:04:46 +0300 | [diff] [blame] | 943 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 944 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 945 | |
| 946 | /* intel_dp.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 947 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
| 948 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 949 | struct intel_connector *intel_connector); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 950 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 951 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| 952 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| 953 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 954 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 955 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 956 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 957 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
| 958 | struct intel_crtc_config *pipe_config); |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 959 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 960 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| 961 | bool long_hpd); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 962 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| 963 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 964 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 965 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 966 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
| 967 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 968 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
| 969 | void intel_edp_psr_disable(struct intel_dp *intel_dp); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 970 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
Daniel Vetter | 9ca1530 | 2014-07-11 10:30:16 -0700 | [diff] [blame] | 971 | void intel_edp_psr_invalidate(struct drm_device *dev, |
| 972 | unsigned frontbuffer_bits); |
| 973 | void intel_edp_psr_flush(struct drm_device *dev, |
| 974 | unsigned frontbuffer_bits); |
Rodrigo Vivi | 7c8f8a7 | 2014-06-13 05:10:03 -0700 | [diff] [blame] | 975 | void intel_edp_psr_init(struct drm_device *dev); |
| 976 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 977 | int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd); |
| 978 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
| 979 | void intel_dp_mst_suspend(struct drm_device *dev); |
| 980 | void intel_dp_mst_resume(struct drm_device *dev); |
| 981 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); |
| 982 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 983 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 984 | /* intel_dp_mst.c */ |
| 985 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
| 986 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 987 | /* intel_dsi.c */ |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 988 | void intel_dsi_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 989 | |
| 990 | |
| 991 | /* intel_dvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 992 | void intel_dvo_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 993 | |
| 994 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 995 | /* legacy fbdev emulation in intel_fbdev.c */ |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 996 | #ifdef CONFIG_DRM_I915_FBDEV |
| 997 | extern int intel_fbdev_init(struct drm_device *dev); |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 998 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 999 | extern void intel_fbdev_fini(struct drm_device *dev); |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 1000 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1001 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
| 1002 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1003 | #else |
| 1004 | static inline int intel_fbdev_init(struct drm_device *dev) |
| 1005 | { |
| 1006 | return 0; |
| 1007 | } |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1008 | |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 1009 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1010 | { |
| 1011 | } |
| 1012 | |
| 1013 | static inline void intel_fbdev_fini(struct drm_device *dev) |
| 1014 | { |
| 1015 | } |
| 1016 | |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 1017 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1018 | { |
| 1019 | } |
| 1020 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1021 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1022 | { |
| 1023 | } |
| 1024 | #endif |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1025 | |
| 1026 | /* intel_hdmi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1027 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
| 1028 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 1029 | struct intel_connector *intel_connector); |
| 1030 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 1031 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1032 | struct intel_crtc_config *pipe_config); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1033 | |
| 1034 | |
| 1035 | /* intel_lvds.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1036 | void intel_lvds_init(struct drm_device *dev); |
| 1037 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1038 | |
| 1039 | |
| 1040 | /* intel_modes.c */ |
| 1041 | int intel_connector_update_modes(struct drm_connector *connector, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1042 | struct edid *edid); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1043 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1044 | void intel_attach_force_audio_property(struct drm_connector *connector); |
| 1045 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1046 | |
| 1047 | |
| 1048 | /* intel_overlay.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1049 | void intel_setup_overlay(struct drm_device *dev); |
| 1050 | void intel_cleanup_overlay(struct drm_device *dev); |
| 1051 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
| 1052 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
| 1053 | struct drm_file *file_priv); |
| 1054 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
| 1055 | struct drm_file *file_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1056 | |
| 1057 | |
| 1058 | /* intel_panel.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1059 | int intel_panel_init(struct intel_panel *panel, |
Vandana Kannan | 4b6ed68 | 2014-02-11 14:26:36 +0530 | [diff] [blame] | 1060 | struct drm_display_mode *fixed_mode, |
| 1061 | struct drm_display_mode *downclock_mode); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1062 | void intel_panel_fini(struct intel_panel *panel); |
| 1063 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| 1064 | struct drm_display_mode *adjusted_mode); |
| 1065 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| 1066 | struct intel_crtc_config *pipe_config, |
| 1067 | int fitting_mode); |
| 1068 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| 1069 | struct intel_crtc_config *pipe_config, |
| 1070 | int fitting_mode); |
Jani Nikula | 6dda730 | 2014-06-24 18:27:40 +0300 | [diff] [blame] | 1071 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
| 1072 | u32 level, u32 max); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1073 | int intel_panel_setup_backlight(struct drm_connector *connector); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1074 | void intel_panel_enable_backlight(struct intel_connector *connector); |
| 1075 | void intel_panel_disable_backlight(struct intel_connector *connector); |
Jani Nikula | db31af1 | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 1076 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 1077 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1078 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 1079 | extern struct drm_display_mode *intel_find_panel_downclock( |
| 1080 | struct drm_device *dev, |
| 1081 | struct drm_display_mode *fixed_mode, |
| 1082 | struct drm_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1083 | |
| 1084 | /* intel_pm.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1085 | void intel_init_clock_gating(struct drm_device *dev); |
| 1086 | void intel_suspend_hw(struct drm_device *dev); |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 1087 | int ilk_wm_max_level(const struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1088 | void intel_update_watermarks(struct drm_crtc *crtc); |
| 1089 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 1090 | struct drm_crtc *crtc, |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 1091 | uint32_t sprite_width, |
| 1092 | uint32_t sprite_height, |
| 1093 | int pixel_size, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1094 | bool enabled, bool scaled); |
| 1095 | void intel_init_pm(struct drm_device *dev); |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 1096 | void intel_pm_setup(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1097 | bool intel_fbc_enabled(struct drm_device *dev); |
| 1098 | void intel_update_fbc(struct drm_device *dev); |
| 1099 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 1100 | void intel_gpu_ips_teardown(void); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1101 | int intel_power_domains_init(struct drm_i915_private *); |
| 1102 | void intel_power_domains_remove(struct drm_i915_private *); |
| 1103 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1104 | enum intel_display_power_domain domain); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 1105 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
| 1106 | enum intel_display_power_domain domain); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1107 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1108 | enum intel_display_power_domain domain); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1109 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1110 | enum intel_display_power_domain domain); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1111 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 1112 | void intel_init_gt_powersave(struct drm_device *dev); |
| 1113 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1114 | void intel_enable_gt_powersave(struct drm_device *dev); |
| 1115 | void intel_disable_gt_powersave(struct drm_device *dev); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 1116 | void intel_suspend_gt_powersave(struct drm_device *dev); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 1117 | void intel_reset_gt_powersave(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1118 | void ironlake_teardown_rc6(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1119 | void gen6_update_ring_freq(struct drm_device *dev); |
Daniel Vetter | 076e29f | 2013-10-08 19:39:29 +0200 | [diff] [blame] | 1120 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 1121 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1122 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
| 1123 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1124 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 1125 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1126 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| 1127 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); |
| 1128 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 1129 | void ilk_wm_get_hw_state(struct drm_device *dev); |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 1130 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1131 | |
| 1132 | /* intel_sdvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1133 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1134 | |
| 1135 | |
| 1136 | /* intel_sprite.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1137 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1138 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1139 | enum plane plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 1140 | int intel_plane_set_property(struct drm_plane *plane, |
| 1141 | struct drm_property *prop, |
| 1142 | uint64_t val); |
Ville Syrjälä | e57465f | 2014-08-05 11:26:53 +0530 | [diff] [blame] | 1143 | int intel_plane_restore(struct drm_plane *plane); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1144 | void intel_plane_disable(struct drm_plane *plane); |
| 1145 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 1146 | struct drm_file *file_priv); |
| 1147 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 1148 | struct drm_file *file_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1149 | |
| 1150 | |
| 1151 | /* intel_tv.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1152 | void intel_tv_init(struct drm_device *dev); |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1153 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1154 | #endif /* __INTEL_DRV_H__ */ |