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Bryan Wu2f351742008-04-30 00:52:12 -07001/*
sonic zhangccf68e52009-12-09 12:31:28 -08002 * Blackfin On-Chip Sport Emulated UART Driver
Bryan Wu2f351742008-04-30 00:52:12 -07003 *
sonic zhangccf68e52009-12-09 12:31:28 -08004 * Copyright 2006-2008 Analog Devices Inc.
Bryan Wu2f351742008-04-30 00:52:12 -07005 *
sonic zhangccf68e52009-12-09 12:31:28 -08006 * Enter bugs at http://blackfin.uclinux.org/
Bryan Wu2f351742008-04-30 00:52:12 -07007 *
sonic zhangccf68e52009-12-09 12:31:28 -08008 * Licensed under the GPL-2 or later.
Bryan Wu2f351742008-04-30 00:52:12 -07009 */
10
sonic zhangccf68e52009-12-09 12:31:28 -080011/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
Justin P. Mattock631dd1a2010-10-18 11:03:14 +020013 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
sonic zhangccf68e52009-12-09 12:31:28 -080014 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
17 */
18
19#ifndef _BFIN_SPORT_UART_H
20#define _BFIN_SPORT_UART_H
Bryan Wu2f351742008-04-30 00:52:12 -070021
22#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
23#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
24#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
25#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
26#define OFFSET_TX 0x10 /* Transmit Data Register */
27#define OFFSET_RX 0x18 /* Receive Data Register */
28#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
29#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
30#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
31#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
32#define OFFSET_STAT 0x30 /* Status Register */
33
34#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
35#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
36#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
37#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
38#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
39#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
Sonic Zhanga5a420d2010-03-09 12:25:28 -050040/*
41 * If another interrupt fires while doing a 32-bit read from RX FIFO,
42 * a fake RX underflow error will be generated. So disable interrupts
43 * to prevent interruption while reading the FIFO.
44 */
45#define SPORT_GET_RX32(sport) \
46({ \
47 unsigned int __ret; \
48 if (ANOMALY_05000473) \
49 local_irq_disable(); \
50 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
51 if (ANOMALY_05000473) \
52 local_irq_enable(); \
53 __ret; \
54})
Bryan Wu2f351742008-04-30 00:52:12 -070055#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
56#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
57#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
58#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
59#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
60
61#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
62#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
63#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
64#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
65#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
66#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
67#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
68#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
69#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
70#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
71#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
sonic zhangccf68e52009-12-09 12:31:28 -080072
73#define SPORT_TX_FIFO_SIZE 8
74
Sonic Zhang1f7d1c82010-03-09 12:25:33 -050075#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
76#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
77#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
78
79#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
80 || defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
81 || defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
82 || defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
83# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
84#endif
85
sonic zhangccf68e52009-12-09 12:31:28 -080086#endif /* _BFIN_SPORT_UART_H */