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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010038#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070039#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010040#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070041#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070042#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010043#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020044#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020045#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020046#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020047#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010048#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070049#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020050#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010051#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* General customization:
54 */
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#define DRIVER_NAME "i915"
57#define DRIVER_DESC "Intel Graphics"
Daniel Vetter0a0c0012015-01-17 10:43:04 +010058#define DRIVER_DATE "20150117"
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Mika Kuoppalac883ef12014-10-28 17:32:30 +020060#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010061/* Many gcc seem to no see through this and fall over :( */
62#if 0
63#define WARN_ON(x) ({ \
64 bool __i915_warn_cond = (x); \
65 if (__builtin_constant_p(__i915_warn_cond)) \
66 BUILD_BUG_ON(__i915_warn_cond); \
67 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
68#else
69#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
70#endif
71
72#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
73 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020074
Rob Clarke2c719b2014-12-15 13:56:32 -050075/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
76 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
77 * which may not necessarily be a user visible problem. This will either
78 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
79 * enable distros and users to tailor their preferred amount of i915 abrt
80 * spam.
81 */
82#define I915_STATE_WARN(condition, format...) ({ \
83 int __ret_warn_on = !!(condition); \
84 if (unlikely(__ret_warn_on)) { \
85 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +020086 WARN(1, format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050087 else \
88 DRM_ERROR(format); \
89 } \
90 unlikely(__ret_warn_on); \
91})
92
93#define I915_STATE_WARN_ON(condition) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) { \
96 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +020097 WARN(1, "WARN_ON(" #condition ")\n"); \
Rob Clarke2c719b2014-12-15 13:56:32 -050098 else \
99 DRM_ERROR("WARN_ON(" #condition ")\n"); \
100 } \
101 unlikely(__ret_warn_on); \
102})
103
Jesse Barnes317c35d2008-08-25 15:11:06 -0700104enum pipe {
Jesse Barnes752aa882013-10-31 18:55:49 +0200105 INVALID_PIPE = -1,
Jesse Barnes317c35d2008-08-25 15:11:06 -0700106 PIPE_A = 0,
107 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800108 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200109 _PIPE_EDP,
110 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -0700111};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800112#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -0700113
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200114enum transcoder {
115 TRANSCODER_A = 0,
116 TRANSCODER_B,
117 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200118 TRANSCODER_EDP,
119 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200120};
121#define transcoder_name(t) ((t) + 'A')
122
Damien Lespiau84139d12014-03-28 00:18:32 +0530123/*
124 * This is the maximum (across all platforms) number of planes (primary +
125 * sprites) that can be active at the same time on one pipe.
126 *
127 * This value doesn't count the cursor plane.
128 */
129#define I915_MAX_PLANES 3
130
Jesse Barnes80824002009-09-10 15:28:06 -0700131enum plane {
132 PLANE_A = 0,
133 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800134 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -0700135};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800136#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -0800137
Damien Lespiaud615a162014-03-03 17:31:48 +0000138#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300139
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300140enum port {
141 PORT_A = 0,
142 PORT_B,
143 PORT_C,
144 PORT_D,
145 PORT_E,
146 I915_MAX_PORTS
147};
148#define port_name(p) ((p) + 'A')
149
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300150#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800151
152enum dpio_channel {
153 DPIO_CH0,
154 DPIO_CH1
155};
156
157enum dpio_phy {
158 DPIO_PHY0,
159 DPIO_PHY1
160};
161
Paulo Zanonib97186f2013-05-03 12:15:36 -0300162enum intel_display_power_domain {
163 POWER_DOMAIN_PIPE_A,
164 POWER_DOMAIN_PIPE_B,
165 POWER_DOMAIN_PIPE_C,
166 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
167 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
168 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
169 POWER_DOMAIN_TRANSCODER_A,
170 POWER_DOMAIN_TRANSCODER_B,
171 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300172 POWER_DOMAIN_TRANSCODER_EDP,
Imre Deak319be8a2014-03-04 19:22:57 +0200173 POWER_DOMAIN_PORT_DDI_A_2_LANES,
174 POWER_DOMAIN_PORT_DDI_A_4_LANES,
175 POWER_DOMAIN_PORT_DDI_B_2_LANES,
176 POWER_DOMAIN_PORT_DDI_B_4_LANES,
177 POWER_DOMAIN_PORT_DDI_C_2_LANES,
178 POWER_DOMAIN_PORT_DDI_C_4_LANES,
179 POWER_DOMAIN_PORT_DDI_D_2_LANES,
180 POWER_DOMAIN_PORT_DDI_D_4_LANES,
181 POWER_DOMAIN_PORT_DSI,
182 POWER_DOMAIN_PORT_CRT,
183 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300184 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200185 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300186 POWER_DOMAIN_PLLS,
Imre Deakbaa70702013-10-25 17:36:48 +0300187 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300188
189 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300190};
191
192#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
193#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
194 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300195#define POWER_DOMAIN_TRANSCODER(tran) \
196 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
197 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300198
Egbert Eich1d843f92013-02-25 12:06:49 -0500199enum hpd_pin {
200 HPD_NONE = 0,
201 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
202 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
203 HPD_CRT,
204 HPD_SDVO_B,
205 HPD_SDVO_C,
206 HPD_PORT_B,
207 HPD_PORT_C,
208 HPD_PORT_D,
209 HPD_NUM_PINS
210};
211
Chris Wilson2a2d5482012-12-03 11:49:06 +0000212#define I915_GEM_GPU_DOMAINS \
213 (I915_GEM_DOMAIN_RENDER | \
214 I915_GEM_DOMAIN_SAMPLER | \
215 I915_GEM_DOMAIN_COMMAND | \
216 I915_GEM_DOMAIN_INSTRUCTION | \
217 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700218
Damien Lespiau055e3932014-08-18 13:49:10 +0100219#define for_each_pipe(__dev_priv, __p) \
220 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Damien Lespiau2d025a52014-09-04 12:27:43 +0100221#define for_each_plane(pipe, p) \
222 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
Damien Lespiaud615a162014-03-03 17:31:48 +0000223#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800224
Damien Lespiaud79b8142014-05-13 23:32:23 +0100225#define for_each_crtc(dev, crtc) \
226 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
227
Damien Lespiaud063ae42014-05-13 23:32:21 +0100228#define for_each_intel_crtc(dev, intel_crtc) \
229 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
230
Damien Lespiaub2784e12014-08-05 11:29:37 +0100231#define for_each_intel_encoder(dev, intel_encoder) \
232 list_for_each_entry(intel_encoder, \
233 &(dev)->mode_config.encoder_list, \
234 base.head)
235
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200236#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
237 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
238 if ((intel_encoder)->base.crtc == (__crtc))
239
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800240#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
241 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
242 if ((intel_connector)->base.encoder == (__encoder))
243
Borun Fub04c5bd2014-07-12 10:02:27 +0530244#define for_each_power_domain(domain, mask) \
245 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
246 if ((1 << (domain)) & (mask))
247
Daniel Vettere7b903d2013-06-05 13:34:14 +0200248struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100249struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100250struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200251
Daniel Vettere2b78262013-06-07 23:10:03 +0200252enum intel_dpll_id {
253 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
254 /* real shared dpll ids must be >= 0 */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300255 DPLL_ID_PCH_PLL_A = 0,
256 DPLL_ID_PCH_PLL_B = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000257 /* hsw/bdw */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300258 DPLL_ID_WRPLL1 = 0,
259 DPLL_ID_WRPLL2 = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000260 /* skl */
261 DPLL_ID_SKL_DPLL1 = 0,
262 DPLL_ID_SKL_DPLL2 = 1,
263 DPLL_ID_SKL_DPLL3 = 2,
Daniel Vettere2b78262013-06-07 23:10:03 +0200264};
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000265#define I915_NUM_PLLS 3
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100266
Daniel Vetter53589012013-06-05 13:34:16 +0200267struct intel_dpll_hw_state {
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100268 /* i9xx, pch plls */
Daniel Vetter66e985c2013-06-05 13:34:20 +0200269 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200270 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200271 uint32_t fp0;
272 uint32_t fp1;
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100273
274 /* hsw, bdw */
Daniel Vetterd452c5b2014-07-04 11:27:39 -0300275 uint32_t wrpll;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000276
277 /* skl */
278 /*
279 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
280 * lower part of crtl1 and they get shifted into position when writing
281 * the register. This allows us to easily compare the state to share
282 * the DPLL.
283 */
284 uint32_t ctrl1;
285 /* HDMI only, 0 when used for DP */
286 uint32_t cfgcr1, cfgcr2;
Daniel Vetter53589012013-06-05 13:34:16 +0200287};
288
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200289struct intel_shared_dpll_config {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +0200290 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200291 struct intel_dpll_hw_state hw_state;
292};
293
294struct intel_shared_dpll {
295 struct intel_shared_dpll_config config;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200296 struct intel_shared_dpll_config *new_config;
297
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 int active; /* count of number of active CRTCs (i.e. DPMS on) */
299 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200300 const char *name;
301 /* should match the index in the dev_priv->shared_dplls array */
302 enum intel_dpll_id id;
Daniel Vetter96f61282014-06-25 22:01:58 +0300303 /* The mode_set hook is optional and should be used together with the
304 * intel_prepare_shared_dpll function. */
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200305 void (*mode_set)(struct drm_i915_private *dev_priv,
306 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200307 void (*enable)(struct drm_i915_private *dev_priv,
308 struct intel_shared_dpll *pll);
309 void (*disable)(struct drm_i915_private *dev_priv,
310 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200311 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
312 struct intel_shared_dpll *pll,
313 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000316#define SKL_DPLL0 0
317#define SKL_DPLL1 1
318#define SKL_DPLL2 2
319#define SKL_DPLL3 3
320
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100321/* Used by dp and fdi links */
322struct intel_link_m_n {
323 uint32_t tu;
324 uint32_t gmch_m;
325 uint32_t gmch_n;
326 uint32_t link_m;
327 uint32_t link_n;
328};
329
330void intel_link_compute_m_n(int bpp, int nlanes,
331 int pixel_clock, int link_clock,
332 struct intel_link_m_n *m_n);
333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334/* Interface history:
335 *
336 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100337 * 1.2: Add Power Management
338 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100339 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000340 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000341 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
342 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 */
344#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000345#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346#define DRIVER_PATCHLEVEL 0
347
Chris Wilson23bc5982010-09-29 16:10:57 +0100348#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700349
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700350struct opregion_header;
351struct opregion_acpi;
352struct opregion_swsci;
353struct opregion_asle;
354
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100355struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700356 struct opregion_header __iomem *header;
357 struct opregion_acpi __iomem *acpi;
358 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300359 u32 swsci_gbda_sub_functions;
360 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700361 struct opregion_asle __iomem *asle;
362 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000363 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200364 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100365};
Chris Wilson44834a62010-08-19 16:09:23 +0100366#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100367
Chris Wilson6ef3d422010-08-04 20:26:07 +0100368struct intel_overlay;
369struct intel_overlay_error_state;
370
Jesse Barnesde151cf2008-11-12 10:03:55 -0800371#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300372#define I915_MAX_NUM_FENCES 32
373/* 32 fences + sign bit for FENCE_REG_NONE */
374#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800375
376struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200377 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000378 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100379 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800380};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000381
yakui_zhao9b9d1722009-05-31 17:17:17 +0800382struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100383 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800384 u8 dvo_port;
385 u8 slave_addr;
386 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100387 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400388 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800389};
390
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000391struct intel_display_error_state;
392
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700393struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200394 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800395 struct timeval time;
396
Mika Kuoppalacb383002014-02-25 17:11:25 +0200397 char error_msg[128];
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200398 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200399 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200400
Ben Widawsky585b0282014-01-30 00:19:37 -0800401 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700402 u32 eir;
403 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700404 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700405 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700406 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000407 u32 derrmr;
408 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800409 u32 error; /* gen6+ */
410 u32 err_int; /* gen7 */
411 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800412 u32 gac_eco;
413 u32 gam_ecochk;
414 u32 gab_ctl;
415 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800416 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800417 u64 fence[I915_MAX_NUM_FENCES];
418 struct intel_overlay_error_state *overlay;
419 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700420 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800421
Chris Wilson52d39a22012-02-15 11:25:37 +0000422 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000423 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800424 /* Software tracked state */
425 bool waiting;
426 int hangcheck_score;
427 enum intel_ring_hangcheck_action hangcheck_action;
428 int num_requests;
429
430 /* our own tracking of ring head and tail */
431 u32 cpu_ring_head;
432 u32 cpu_ring_tail;
433
434 u32 semaphore_seqno[I915_NUM_RINGS - 1];
435
436 /* Register state */
437 u32 tail;
438 u32 head;
439 u32 ctl;
440 u32 hws;
441 u32 ipeir;
442 u32 ipehr;
443 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800444 u32 bbstate;
445 u32 instpm;
446 u32 instps;
447 u32 seqno;
448 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000449 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800450 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700451 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800452 u32 rc_psmi; /* sleep state */
453 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
454
Chris Wilson52d39a22012-02-15 11:25:37 +0000455 struct drm_i915_error_object {
456 int page_count;
457 u32 gtt_offset;
458 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200459 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800460
Chris Wilson52d39a22012-02-15 11:25:37 +0000461 struct drm_i915_error_request {
462 long jiffies;
463 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000464 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000465 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800466
467 struct {
468 u32 gfx_mode;
469 union {
470 u64 pdp[4];
471 u32 pp_dir_base;
472 };
473 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200474
475 pid_t pid;
476 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000477 } ring[I915_NUM_RINGS];
Chris Wilson3a448732014-08-12 20:05:47 +0100478
Chris Wilson9df30792010-02-18 10:24:56 +0000479 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000480 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000481 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100482 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000483 u32 gtt_offset;
484 u32 read_domains;
485 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200486 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000487 s32 pinned:2;
488 u32 tiling:2;
489 u32 dirty:1;
490 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100491 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100492 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100493 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700494 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800495
Ben Widawsky95f53012013-07-31 17:00:15 -0700496 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100497 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700498};
499
Jani Nikula7bd688c2013-11-08 16:48:56 +0200500struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200501struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200502struct intel_crtc_state;
Jesse Barnes46f297f2014-03-07 08:57:48 -0800503struct intel_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100504struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200505struct intel_limit;
506struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100507
Jesse Barnese70236a2009-09-21 10:42:27 -0700508struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400509 bool (*fbc_enabled)(struct drm_device *dev);
Ville Syrjälä993495a2013-12-12 17:27:40 +0200510 void (*enable_fbc)(struct drm_crtc *crtc);
Jesse Barnese70236a2009-09-21 10:42:27 -0700511 void (*disable_fbc)(struct drm_device *dev);
512 int (*get_display_clock_speed)(struct drm_device *dev);
513 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200514 /**
515 * find_dpll() - Find the best values for the PLL
516 * @limit: limits for the PLL
517 * @crtc: current CRTC
518 * @target: target frequency in kHz
519 * @refclk: reference clock frequency in kHz
520 * @match_clock: if provided, @best_clock P divider must
521 * match the P divider from @match_clock
522 * used for LVDS downclocking
523 * @best_clock: best PLL values found
524 *
525 * Returns true on success, false on failure.
526 */
527 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300528 struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200529 int target, int refclk,
530 struct dpll *match_clock,
531 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300532 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300533 void (*update_sprite_wm)(struct drm_plane *plane,
534 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +0200535 uint32_t sprite_width, uint32_t sprite_height,
536 int pixel_size, bool enable, bool scaled);
Daniel Vetter47fab732012-10-26 10:58:18 +0200537 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100538 /* Returns the active state of the crtc, and if the crtc is active,
539 * fills out the pipe-config with the hw state. */
540 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200541 struct intel_crtc_state *);
Jesse Barnes46f297f2014-03-07 08:57:48 -0800542 void (*get_plane_config)(struct intel_crtc *,
543 struct intel_plane_config *);
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200544 int (*crtc_compute_clock)(struct intel_crtc *crtc);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200545 void (*crtc_enable)(struct drm_crtc *crtc);
546 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100547 void (*off)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200548 void (*audio_codec_enable)(struct drm_connector *connector,
549 struct intel_encoder *encoder,
550 struct drm_display_mode *mode);
551 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700552 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700553 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700554 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
555 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700556 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100557 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -0700558 uint32_t flags);
Daniel Vetter29b9bde2014-04-24 23:55:01 +0200559 void (*update_primary_plane)(struct drm_crtc *crtc,
560 struct drm_framebuffer *fb,
561 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100562 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700563 /* clock updates for mode set */
564 /* cursor updates */
565 /* render clock increase/decrease */
566 /* display clock increase/decrease */
567 /* pll clock increase/decrease */
Jani Nikula7bd688c2013-11-08 16:48:56 +0200568
Ville Syrjälä6517d272014-11-07 11:16:02 +0200569 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
Jani Nikula7bd688c2013-11-08 16:48:56 +0200570 uint32_t (*get_backlight)(struct intel_connector *connector);
571 void (*set_backlight)(struct intel_connector *connector,
572 uint32_t level);
573 void (*disable_backlight)(struct intel_connector *connector);
574 void (*enable_backlight)(struct intel_connector *connector);
Jesse Barnese70236a2009-09-21 10:42:27 -0700575};
576
Chris Wilson907b28c2013-07-19 20:36:52 +0100577struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530578 void (*force_wake_get)(struct drm_i915_private *dev_priv,
579 int fw_engine);
580 void (*force_wake_put)(struct drm_i915_private *dev_priv,
581 int fw_engine);
Ben Widawsky0b274482013-10-04 21:22:51 -0700582
583 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
584 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
585 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
586 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
587
588 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
589 uint8_t val, bool trace);
590 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
591 uint16_t val, bool trace);
592 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
593 uint32_t val, bool trace);
594 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
595 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300596};
597
Chris Wilson907b28c2013-07-19 20:36:52 +0100598struct intel_uncore {
599 spinlock_t lock; /** lock is also taken in irq contexts. */
600
601 struct intel_uncore_funcs funcs;
602
603 unsigned fifo_count;
604 unsigned forcewake_count;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100605
Deepak S940aece2013-11-23 14:55:43 +0530606 unsigned fw_rendercount;
607 unsigned fw_mediacount;
Zhe Wang38cff0b2014-11-04 17:07:04 +0000608 unsigned fw_blittercount;
Deepak S940aece2013-11-23 14:55:43 +0530609
Chris Wilson82326442014-03-05 12:00:39 +0000610 struct timer_list force_wake_timer;
Chris Wilson907b28c2013-07-19 20:36:52 +0100611};
612
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100613#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
614 func(is_mobile) sep \
615 func(is_i85x) sep \
616 func(is_i915g) sep \
617 func(is_i945gm) sep \
618 func(is_g33) sep \
619 func(need_gfx_hws) sep \
620 func(is_g4x) sep \
621 func(is_pineview) sep \
622 func(is_broadwater) sep \
623 func(is_crestline) sep \
624 func(is_ivybridge) sep \
625 func(is_valleyview) sep \
626 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530627 func(is_skylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700628 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100629 func(has_fbc) sep \
630 func(has_pipe_cxsr) sep \
631 func(has_hotplug) sep \
632 func(cursor_needs_physical) sep \
633 func(has_overlay) sep \
634 func(overlay_needs_physical) sep \
635 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100636 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100637 func(has_ddi) sep \
638 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200639
Damien Lespiaua587f772013-04-22 18:40:38 +0100640#define DEFINE_FLAG(name) u8 name:1
641#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200642
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500643struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200644 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100645 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700646 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000647 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000648 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700649 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100650 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200651 /* Register offsets for the various display pipes and transcoders */
652 int pipe_offsets[I915_MAX_TRANSCODERS];
653 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200654 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300655 int cursor_offsets[I915_MAX_PIPES];
Deepak S693d11c2015-01-16 20:42:16 +0530656 unsigned int eu_total;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500657};
658
Damien Lespiaua587f772013-04-22 18:40:38 +0100659#undef DEFINE_FLAG
660#undef SEP_SEMICOLON
661
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800662enum i915_cache_level {
663 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100664 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
665 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
666 caches, eg sampler/render caches, and the
667 large Last-Level-Cache. LLC is coherent with
668 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100669 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800670};
671
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300672struct i915_ctx_hang_stats {
673 /* This context had batch pending when hang was declared */
674 unsigned batch_pending;
675
676 /* This context had batch active when hang was declared */
677 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300678
679 /* Time when this context was last blamed for a GPU reset */
680 unsigned long guilty_ts;
681
Chris Wilson676fa572014-12-24 08:13:39 -0800682 /* If the contexts causes a second GPU hang within this time,
683 * it is permanently banned from submitting any more work.
684 */
685 unsigned long ban_period_seconds;
686
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300687 /* This context is banned to submit more work */
688 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300689};
Ben Widawsky40521052012-06-04 14:42:43 -0700690
691/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100692#define DEFAULT_CONTEXT_HANDLE 0
Oscar Mateo31b7a882014-07-03 16:28:01 +0100693/**
694 * struct intel_context - as the name implies, represents a context.
695 * @ref: reference count.
696 * @user_handle: userspace tracking identity for this context.
697 * @remap_slice: l3 row remapping information.
698 * @file_priv: filp associated with this context (NULL for global default
699 * context).
700 * @hang_stats: information about the role of this context in possible GPU
701 * hangs.
702 * @vm: virtual memory space used by this context.
703 * @legacy_hw_ctx: render context backing object and whether it is correctly
704 * initialized (legacy ring submission mechanism only).
705 * @link: link in the global list of contexts.
706 *
707 * Contexts are memory images used by the hardware to store copies of their
708 * internal state.
709 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100710struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300711 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100712 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700713 uint8_t remap_slice;
Ben Widawsky40521052012-06-04 14:42:43 -0700714 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300715 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200716 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700717
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100718 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100719 struct {
720 struct drm_i915_gem_object *rcs_state;
721 bool initialized;
722 } legacy_hw_ctx;
723
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100724 /* Execlists */
Oscar Mateo564ddb22014-08-21 11:40:54 +0100725 bool rcs_initialized;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100726 struct {
727 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100728 struct intel_ringbuffer *ringbuf;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000729 int unpin_count;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100730 } engine[I915_NUM_RINGS];
731
Ben Widawskya33afea2013-09-17 21:12:45 -0700732 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700733};
734
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700735struct i915_fbc {
736 unsigned long size;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700737 unsigned threshold;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700738 unsigned int fb_id;
739 enum plane plane;
740 int y;
741
Ben Widawskyc4213882014-06-19 12:06:10 -0700742 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700743 struct drm_mm_node *compressed_llb;
744
Rodrigo Vivida46f932014-08-01 02:04:45 -0700745 bool false_color;
746
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300747 /* Tracks whether the HW is actually enabled, not whether the feature is
748 * possible. */
749 bool enabled;
750
Rodrigo Vivi1d73c2a2014-09-24 19:50:59 -0400751 /* On gen8 some rings cannont perform fbc clean operation so for now
752 * we are doing this on SW with mmio.
753 * This variable works in the opposite information direction
754 * of ring->fbc_dirty telling software on frontbuffer tracking
755 * to perform the cache clean on sw side.
756 */
757 bool need_sw_cache_clean;
758
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700759 struct intel_fbc_work {
760 struct delayed_work work;
761 struct drm_crtc *crtc;
762 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700763 } *fbc_work;
764
Chris Wilson29ebf902013-07-27 17:23:55 +0100765 enum no_fbc_reason {
766 FBC_OK, /* FBC is enabled */
767 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700768 FBC_NO_OUTPUT, /* no outputs enabled to compress */
769 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
770 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
771 FBC_MODE_TOO_LARGE, /* mode too large for compression */
772 FBC_BAD_PLANE, /* fbc not supported on plane */
773 FBC_NOT_TILED, /* buffer not tiled */
774 FBC_MULTIPLE_PIPES, /* more than one pipe active */
775 FBC_MODULE_PARAM,
776 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
777 } no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800778};
779
Vandana Kannan96178ee2015-01-10 02:25:56 +0530780/**
781 * HIGH_RR is the highest eDP panel refresh rate read from EDID
782 * LOW_RR is the lowest eDP panel refresh rate found from EDID
783 * parsing for same resolution.
784 */
785enum drrs_refresh_rate_type {
786 DRRS_HIGH_RR,
787 DRRS_LOW_RR,
788 DRRS_MAX_RR, /* RR count */
789};
790
791enum drrs_support_type {
792 DRRS_NOT_SUPPORTED = 0,
793 STATIC_DRRS_SUPPORT = 1,
794 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530795};
796
Daniel Vetter2807cf62014-07-11 10:30:11 -0700797struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530798struct i915_drrs {
799 struct mutex mutex;
800 struct delayed_work work;
801 struct intel_dp *dp;
802 unsigned busy_frontbuffer_bits;
803 enum drrs_refresh_rate_type refresh_rate_type;
804 enum drrs_support_type type;
805};
806
Rodrigo Vivia031d702013-10-03 16:15:06 -0300807struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700808 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300809 bool sink_support;
810 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700811 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700812 bool active;
813 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700814 unsigned busy_frontbuffer_bits;
Rodrigo Vivi0243f7b2015-01-12 10:14:32 -0800815 bool link_standby;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300816};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700817
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800818enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300819 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800820 PCH_IBX, /* Ibexpeak PCH */
821 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300822 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530823 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700824 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800825};
826
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200827enum intel_sbi_destination {
828 SBI_ICLK,
829 SBI_MPHY,
830};
831
Jesse Barnesb690e962010-07-19 13:53:12 -0700832#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700833#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100834#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000835#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +0300836#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100837#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -0700838
Dave Airlie8be48d92010-03-30 05:34:14 +0000839struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100840struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000841
Daniel Vetterc2b91522012-02-14 22:37:19 +0100842struct intel_gmbus {
843 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000844 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100845 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100846 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100847 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100848 struct drm_i915_private *dev_priv;
849};
850
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100851struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000852 u8 saveLBB;
853 u32 saveDSPACNTR;
854 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000855 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000856 u32 savePIPEACONF;
857 u32 savePIPEBCONF;
858 u32 savePIPEASRC;
859 u32 savePIPEBSRC;
860 u32 saveFPA0;
861 u32 saveFPA1;
862 u32 saveDPLL_A;
863 u32 saveDPLL_A_MD;
864 u32 saveHTOTAL_A;
865 u32 saveHBLANK_A;
866 u32 saveHSYNC_A;
867 u32 saveVTOTAL_A;
868 u32 saveVBLANK_A;
869 u32 saveVSYNC_A;
870 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000871 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800872 u32 saveTRANS_HTOTAL_A;
873 u32 saveTRANS_HBLANK_A;
874 u32 saveTRANS_HSYNC_A;
875 u32 saveTRANS_VTOTAL_A;
876 u32 saveTRANS_VBLANK_A;
877 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000878 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000879 u32 saveDSPASTRIDE;
880 u32 saveDSPASIZE;
881 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700882 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000883 u32 saveDSPASURF;
884 u32 saveDSPATILEOFF;
885 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700886 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000887 u32 saveBLC_PWM_CTL;
888 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800889 u32 saveBLC_CPU_PWM_CTL;
890 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000891 u32 saveFPB0;
892 u32 saveFPB1;
893 u32 saveDPLL_B;
894 u32 saveDPLL_B_MD;
895 u32 saveHTOTAL_B;
896 u32 saveHBLANK_B;
897 u32 saveHSYNC_B;
898 u32 saveVTOTAL_B;
899 u32 saveVBLANK_B;
900 u32 saveVSYNC_B;
901 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000902 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800903 u32 saveTRANS_HTOTAL_B;
904 u32 saveTRANS_HBLANK_B;
905 u32 saveTRANS_HSYNC_B;
906 u32 saveTRANS_VTOTAL_B;
907 u32 saveTRANS_VBLANK_B;
908 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000909 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000910 u32 saveDSPBSTRIDE;
911 u32 saveDSPBSIZE;
912 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700913 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000914 u32 saveDSPBSURF;
915 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700916 u32 saveVGA0;
917 u32 saveVGA1;
918 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000919 u32 saveVGACNTRL;
920 u32 saveADPA;
921 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700922 u32 savePP_ON_DELAYS;
923 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000924 u32 saveDVOA;
925 u32 saveDVOB;
926 u32 saveDVOC;
927 u32 savePP_ON;
928 u32 savePP_OFF;
929 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700930 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000931 u32 savePFIT_CONTROL;
932 u32 save_palette_a[256];
933 u32 save_palette_b[256];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000934 u32 saveFBC_CONTROL;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000935 u32 saveIER;
936 u32 saveIIR;
937 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800938 u32 saveDEIER;
939 u32 saveDEIMR;
940 u32 saveGTIER;
941 u32 saveGTIMR;
942 u32 saveFDI_RXA_IMR;
943 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800944 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800945 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000946 u32 saveSWF0[16];
947 u32 saveSWF1[16];
948 u32 saveSWF2[3];
949 u8 saveMSR;
950 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800951 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000952 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000953 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000954 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000955 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200956 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000957 u32 saveCURACNTR;
958 u32 saveCURAPOS;
959 u32 saveCURABASE;
960 u32 saveCURBCNTR;
961 u32 saveCURBPOS;
962 u32 saveCURBBASE;
963 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700964 u32 saveDP_B;
965 u32 saveDP_C;
966 u32 saveDP_D;
967 u32 savePIPEA_GMCH_DATA_M;
968 u32 savePIPEB_GMCH_DATA_M;
969 u32 savePIPEA_GMCH_DATA_N;
970 u32 savePIPEB_GMCH_DATA_N;
971 u32 savePIPEA_DP_LINK_M;
972 u32 savePIPEB_DP_LINK_M;
973 u32 savePIPEA_DP_LINK_N;
974 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800975 u32 saveFDI_RXA_CTL;
976 u32 saveFDI_TXA_CTL;
977 u32 saveFDI_RXB_CTL;
978 u32 saveFDI_TXB_CTL;
979 u32 savePFA_CTL_1;
980 u32 savePFB_CTL_1;
981 u32 savePFA_WIN_SZ;
982 u32 savePFB_WIN_SZ;
983 u32 savePFA_WIN_POS;
984 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000985 u32 savePCH_DREF_CONTROL;
986 u32 saveDISP_ARB_CTL;
987 u32 savePIPEA_DATA_M1;
988 u32 savePIPEA_DATA_N1;
989 u32 savePIPEA_LINK_M1;
990 u32 savePIPEA_LINK_N1;
991 u32 savePIPEB_DATA_M1;
992 u32 savePIPEB_DATA_N1;
993 u32 savePIPEB_LINK_M1;
994 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000995 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400996 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -0800997 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100998};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100999
Imre Deakddeea5b2014-05-05 15:19:56 +03001000struct vlv_s0ix_state {
1001 /* GAM */
1002 u32 wr_watermark;
1003 u32 gfx_prio_ctrl;
1004 u32 arb_mode;
1005 u32 gfx_pend_tlb0;
1006 u32 gfx_pend_tlb1;
1007 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1008 u32 media_max_req_count;
1009 u32 gfx_max_req_count;
1010 u32 render_hwsp;
1011 u32 ecochk;
1012 u32 bsd_hwsp;
1013 u32 blt_hwsp;
1014 u32 tlb_rd_addr;
1015
1016 /* MBC */
1017 u32 g3dctl;
1018 u32 gsckgctl;
1019 u32 mbctl;
1020
1021 /* GCP */
1022 u32 ucgctl1;
1023 u32 ucgctl3;
1024 u32 rcgctl1;
1025 u32 rcgctl2;
1026 u32 rstctl;
1027 u32 misccpctl;
1028
1029 /* GPM */
1030 u32 gfxpause;
1031 u32 rpdeuhwtc;
1032 u32 rpdeuc;
1033 u32 ecobus;
1034 u32 pwrdwnupctl;
1035 u32 rp_down_timeout;
1036 u32 rp_deucsw;
1037 u32 rcubmabdtmr;
1038 u32 rcedata;
1039 u32 spare2gh;
1040
1041 /* Display 1 CZ domain */
1042 u32 gt_imr;
1043 u32 gt_ier;
1044 u32 pm_imr;
1045 u32 pm_ier;
1046 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1047
1048 /* GT SA CZ domain */
1049 u32 tilectl;
1050 u32 gt_fifoctl;
1051 u32 gtlc_wake_ctrl;
1052 u32 gtlc_survive;
1053 u32 pmwgicz;
1054
1055 /* Display 2 CZ domain */
1056 u32 gu_ctl0;
1057 u32 gu_ctl1;
1058 u32 clock_gate_dis2;
1059};
1060
Chris Wilsonbf225f22014-07-10 20:31:18 +01001061struct intel_rps_ei {
1062 u32 cz_clock;
1063 u32 render_c0;
1064 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001065};
1066
Daniel Vetterc85aa882012-11-02 19:55:03 +01001067struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001068 /*
1069 * work, interrupts_enabled and pm_iir are protected by
1070 * dev_priv->irq_lock
1071 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001072 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001073 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001074 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001075
Ben Widawskyb39fb292014-03-19 18:31:11 -07001076 /* Frequencies are stored in potentially platform dependent multiples.
1077 * In other words, *_freq needs to be multiplied by X to be interesting.
1078 * Soft limits are those which are used for the dynamic reclocking done
1079 * by the driver (raise frequencies under heavy loads, and lower for
1080 * lighter loads). Hard limits are those imposed by the hardware.
1081 *
1082 * A distinction is made for overclocking, which is never enabled by
1083 * default, and is considered to be above the hard limit if it's
1084 * possible at all.
1085 */
1086 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1087 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1088 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1089 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1090 u8 min_freq; /* AKA RPn. Minimum frequency */
1091 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1092 u8 rp1_freq; /* "less than" RP0 power/freqency */
1093 u8 rp0_freq; /* Non-overclocked max frequency. */
Deepak S67c3bf62014-07-10 13:16:24 +05301094 u32 cz_freq;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001095
Deepak S31685c22014-07-03 17:33:01 -04001096 u32 ei_interrupt_count;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001097
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001098 int last_adj;
1099 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1100
Chris Wilsonc0951f02013-10-10 21:58:50 +01001101 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001102 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001103
Chris Wilsonbf225f22014-07-10 20:31:18 +01001104 /* manual wa residency calculations */
1105 struct intel_rps_ei up_ei, down_ei;
1106
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001107 /*
1108 * Protects RPS/RC6 register access and PCU communication.
1109 * Must be taken after struct_mutex if nested.
1110 */
1111 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001112};
1113
Daniel Vetter1a240d42012-11-29 22:18:51 +01001114/* defined intel_pm.c */
1115extern spinlock_t mchdev_lock;
1116
Daniel Vetterc85aa882012-11-02 19:55:03 +01001117struct intel_ilk_power_mgmt {
1118 u8 cur_delay;
1119 u8 min_delay;
1120 u8 max_delay;
1121 u8 fmax;
1122 u8 fstart;
1123
1124 u64 last_count1;
1125 unsigned long last_time1;
1126 unsigned long chipset_power;
1127 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001128 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001129 unsigned long gfx_power;
1130 u8 corr;
1131
1132 int c_m;
1133 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +01001134
1135 struct drm_i915_gem_object *pwrctx;
1136 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001137};
1138
Imre Deakc6cb5822014-03-04 19:22:55 +02001139struct drm_i915_private;
1140struct i915_power_well;
1141
1142struct i915_power_well_ops {
1143 /*
1144 * Synchronize the well's hw state to match the current sw state, for
1145 * example enable/disable it based on the current refcount. Called
1146 * during driver init and resume time, possibly after first calling
1147 * the enable/disable handlers.
1148 */
1149 void (*sync_hw)(struct drm_i915_private *dev_priv,
1150 struct i915_power_well *power_well);
1151 /*
1152 * Enable the well and resources that depend on it (for example
1153 * interrupts located on the well). Called after the 0->1 refcount
1154 * transition.
1155 */
1156 void (*enable)(struct drm_i915_private *dev_priv,
1157 struct i915_power_well *power_well);
1158 /*
1159 * Disable the well and resources that depend on it. Called after
1160 * the 1->0 refcount transition.
1161 */
1162 void (*disable)(struct drm_i915_private *dev_priv,
1163 struct i915_power_well *power_well);
1164 /* Returns the hw enabled state. */
1165 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1166 struct i915_power_well *power_well);
1167};
1168
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001169/* Power well structure for haswell */
1170struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001171 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001172 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001173 /* power well enable/disable usage count */
1174 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001175 /* cached hw enabled state */
1176 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001177 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001178 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001179 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001180};
1181
Imre Deak83c00f552013-10-25 17:36:47 +03001182struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001183 /*
1184 * Power wells needed for initialization at driver init and suspend
1185 * time are on. They are kept on until after the first modeset.
1186 */
1187 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001188 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001189 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001190
Imre Deak83c00f552013-10-25 17:36:47 +03001191 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001192 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001193 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +03001194};
1195
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001196#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001197struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001198 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001199 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001200 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001201};
1202
Brad Volkin493018d2014-12-11 12:13:08 -08001203struct i915_gem_batch_pool {
1204 struct drm_device *dev;
1205 struct list_head cache_list;
1206};
1207
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001208struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001209 /** Memory allocator for GTT stolen memory */
1210 struct drm_mm stolen;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001211 /** List of all objects in gtt_space. Used to restore gtt
1212 * mappings on resume */
1213 struct list_head bound_list;
1214 /**
1215 * List of objects which are not bound to the GTT (thus
1216 * are idle and not used by the GPU) but still have
1217 * (presumably uncached) pages still attached.
1218 */
1219 struct list_head unbound_list;
1220
Brad Volkin493018d2014-12-11 12:13:08 -08001221 /*
1222 * A pool of objects to use as shadow copies of client batch buffers
1223 * when the command parser is enabled. Prevents the client from
1224 * modifying the batch contents after software parsing.
1225 */
1226 struct i915_gem_batch_pool batch_pool;
1227
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001228 /** Usable portion of the GTT for GEM */
1229 unsigned long stolen_base; /* limited to low memory (32-bit) */
1230
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001231 /** PPGTT used for aliasing the PPGTT with the GTT */
1232 struct i915_hw_ppgtt *aliasing_ppgtt;
1233
Chris Wilson2cfcd322014-05-20 08:28:43 +01001234 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001235 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001236 bool shrinker_no_lock_stealing;
1237
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001238 /** LRU list of objects with fence regs on them. */
1239 struct list_head fence_list;
1240
1241 /**
1242 * We leave the user IRQ off as much as possible,
1243 * but this means that requests will finish and never
1244 * be retired once the system goes idle. Set a timer to
1245 * fire periodically while the ring is running. When it
1246 * fires, go retire requests.
1247 */
1248 struct delayed_work retire_work;
1249
1250 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001251 * When we detect an idle GPU, we want to turn on
1252 * powersaving features. So once we see that there
1253 * are no more requests outstanding and no more
1254 * arrive within a small period of time, we fire
1255 * off the idle_work.
1256 */
1257 struct delayed_work idle_work;
1258
1259 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001260 * Are we in a non-interruptible section of code like
1261 * modesetting?
1262 */
1263 bool interruptible;
1264
Chris Wilsonf62a0072014-02-21 17:55:39 +00001265 /**
1266 * Is the GPU currently considered idle, or busy executing userspace
1267 * requests? Whilst idle, we attempt to power down the hardware and
1268 * display clocks. In order to reduce the effect on performance, there
1269 * is a slight delay before we do so.
1270 */
1271 bool busy;
1272
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001273 /* the indicator for dispatch video commands on two BSD rings */
1274 int bsd_ring_dispatch_index;
1275
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001276 /** Bit 6 swizzling required for X tiling */
1277 uint32_t bit_6_swizzle_x;
1278 /** Bit 6 swizzling required for Y tiling */
1279 uint32_t bit_6_swizzle_y;
1280
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001281 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001282 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001283 size_t object_memory;
1284 u32 object_count;
1285};
1286
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001287struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001288 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001289 unsigned bytes;
1290 unsigned size;
1291 int err;
1292 u8 *buf;
1293 loff_t start;
1294 loff_t pos;
1295};
1296
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001297struct i915_error_state_file_priv {
1298 struct drm_device *dev;
1299 struct drm_i915_error_state *error;
1300};
1301
Daniel Vetter99584db2012-11-14 17:14:04 +01001302struct i915_gpu_error {
1303 /* For hangcheck timer */
1304#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1305#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001306 /* Hang gpu twice in this window and your context gets banned */
1307#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1308
Daniel Vetter99584db2012-11-14 17:14:04 +01001309 struct timer_list hangcheck_timer;
Daniel Vetter99584db2012-11-14 17:14:04 +01001310
1311 /* For reset and error_state handling. */
1312 spinlock_t lock;
1313 /* Protected by the above dev->gpu_error.lock. */
1314 struct drm_i915_error_state *first_error;
1315 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001316
Chris Wilson094f9a52013-09-25 17:34:55 +01001317
1318 unsigned long missed_irq_rings;
1319
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001320 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001321 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001322 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001323 * This is a counter which gets incremented when reset is triggered,
1324 * and again when reset has been handled. So odd values (lowest bit set)
1325 * means that reset is in progress and even values that
1326 * (reset_counter >> 1):th reset was successfully completed.
1327 *
1328 * If reset is not completed succesfully, the I915_WEDGE bit is
1329 * set meaning that hardware is terminally sour and there is no
1330 * recovery. All waiters on the reset_queue will be woken when
1331 * that happens.
1332 *
1333 * This counter is used by the wait_seqno code to notice that reset
1334 * event happened and it needs to restart the entire ioctl (since most
1335 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001336 *
1337 * This is important for lock-free wait paths, where no contended lock
1338 * naturally enforces the correct ordering between the bail-out of the
1339 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001340 */
1341 atomic_t reset_counter;
1342
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001343#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001344#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001345
1346 /**
1347 * Waitqueue to signal when the reset has completed. Used by clients
1348 * that wait for dev_priv->mm.wedged to settle.
1349 */
1350 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001351
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001352 /* Userspace knobs for gpu hang simulation;
1353 * combines both a ring mask, and extra flags
1354 */
1355 u32 stop_rings;
1356#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1357#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001358
1359 /* For missed irq/seqno simulation. */
1360 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001361
1362 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1363 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001364};
1365
Zhang Ruib8efb172013-02-05 15:41:53 +08001366enum modeset_restore {
1367 MODESET_ON_LID_OPEN,
1368 MODESET_DONE,
1369 MODESET_SUSPENDED,
1370};
1371
Paulo Zanoni6acab152013-09-12 17:06:24 -03001372struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001373 /*
1374 * This is an index in the HDMI/DVI DDI buffer translation table.
1375 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1376 * populate this field.
1377 */
1378#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001379 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001380
1381 uint8_t supports_dvi:1;
1382 uint8_t supports_hdmi:1;
1383 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001384};
1385
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001386enum psr_lines_to_wait {
1387 PSR_0_LINES_TO_WAIT = 0,
1388 PSR_1_LINE_TO_WAIT,
1389 PSR_4_LINES_TO_WAIT,
1390 PSR_8_LINES_TO_WAIT
1391};
1392
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001393struct intel_vbt_data {
1394 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1395 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1396
1397 /* Feature bits */
1398 unsigned int int_tv_support:1;
1399 unsigned int lvds_dither:1;
1400 unsigned int lvds_vbt:1;
1401 unsigned int int_crt_support:1;
1402 unsigned int lvds_use_ssc:1;
1403 unsigned int display_clock_mode:1;
1404 unsigned int fdi_rx_polarity_inverted:1;
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301405 unsigned int has_mipi:1;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001406 int lvds_ssc_freq;
1407 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1408
Pradeep Bhat83a72802014-03-28 10:14:57 +05301409 enum drrs_support_type drrs_type;
1410
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001411 /* eDP */
1412 int edp_rate;
1413 int edp_lanes;
1414 int edp_preemphasis;
1415 int edp_vswing;
1416 bool edp_initialized;
1417 bool edp_support;
1418 int edp_bpp;
1419 struct edp_power_seq edp_pps;
1420
Jani Nikulaf00076d2013-12-14 20:38:29 -02001421 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001422 bool full_link;
1423 bool require_aux_wakeup;
1424 int idle_frames;
1425 enum psr_lines_to_wait lines_to_wait;
1426 int tp1_wakeup_time;
1427 int tp2_tp3_wakeup_time;
1428 } psr;
1429
1430 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001431 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001432 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001433 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001434 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001435 } backlight;
1436
Shobhit Kumard17c5442013-08-27 15:12:25 +03001437 /* MIPI DSI */
1438 struct {
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301439 u16 port;
Shobhit Kumard17c5442013-08-27 15:12:25 +03001440 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301441 struct mipi_config *config;
1442 struct mipi_pps_data *pps;
1443 u8 seq_version;
1444 u32 size;
1445 u8 *data;
1446 u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001447 } dsi;
1448
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001449 int crt_ddc_pin;
1450
1451 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001452 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001453
1454 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001455};
1456
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001457enum intel_ddb_partitioning {
1458 INTEL_DDB_PART_1_2,
1459 INTEL_DDB_PART_5_6, /* IVB+ */
1460};
1461
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001462struct intel_wm_level {
1463 bool enable;
1464 uint32_t pri_val;
1465 uint32_t spr_val;
1466 uint32_t cur_val;
1467 uint32_t fbc_val;
1468};
1469
Imre Deak820c1982013-12-17 14:46:36 +02001470struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001471 uint32_t wm_pipe[3];
1472 uint32_t wm_lp[3];
1473 uint32_t wm_lp_spr[3];
1474 uint32_t wm_linetime[3];
1475 bool enable_fbc_wm;
1476 enum intel_ddb_partitioning partitioning;
1477};
1478
Damien Lespiauc1939242014-11-04 17:06:41 +00001479struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001480 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001481};
1482
1483static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1484{
Damien Lespiau16160e32014-11-04 17:06:53 +00001485 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001486}
1487
Damien Lespiau08db6652014-11-04 17:06:52 +00001488static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1489 const struct skl_ddb_entry *e2)
1490{
1491 if (e1->start == e2->start && e1->end == e2->end)
1492 return true;
1493
1494 return false;
1495}
1496
Damien Lespiauc1939242014-11-04 17:06:41 +00001497struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001498 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001499 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1500 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1501};
1502
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001503struct skl_wm_values {
1504 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001505 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001506 uint32_t wm_linetime[I915_MAX_PIPES];
1507 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1508 uint32_t cursor[I915_MAX_PIPES][8];
1509 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1510 uint32_t cursor_trans[I915_MAX_PIPES];
1511};
1512
1513struct skl_wm_level {
1514 bool plane_en[I915_MAX_PLANES];
Damien Lespiaub99f58d2014-11-04 17:06:56 +00001515 bool cursor_en;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001516 uint16_t plane_res_b[I915_MAX_PLANES];
1517 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001518 uint16_t cursor_res_b;
1519 uint8_t cursor_res_l;
1520};
1521
Paulo Zanonic67a4702013-08-19 13:18:09 -03001522/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001523 * This struct helps tracking the state needed for runtime PM, which puts the
1524 * device in PCI D3 state. Notice that when this happens, nothing on the
1525 * graphics device works, even register access, so we don't get interrupts nor
1526 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001527 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001528 * Every piece of our code that needs to actually touch the hardware needs to
1529 * either call intel_runtime_pm_get or call intel_display_power_get with the
1530 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001531 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001532 * Our driver uses the autosuspend delay feature, which means we'll only really
1533 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001534 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab62014-03-07 20:08:18 -03001535 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001536 *
1537 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1538 * goes back to false exactly before we reenable the IRQs. We use this variable
1539 * to check if someone is trying to enable/disable IRQs while they're supposed
1540 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001541 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001542 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001543 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001544 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001545struct i915_runtime_pm {
1546 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001547 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001548};
1549
Daniel Vetter926321d2013-10-16 13:30:34 +02001550enum intel_pipe_crc_source {
1551 INTEL_PIPE_CRC_SOURCE_NONE,
1552 INTEL_PIPE_CRC_SOURCE_PLANE1,
1553 INTEL_PIPE_CRC_SOURCE_PLANE2,
1554 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001555 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001556 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1557 INTEL_PIPE_CRC_SOURCE_TV,
1558 INTEL_PIPE_CRC_SOURCE_DP_B,
1559 INTEL_PIPE_CRC_SOURCE_DP_C,
1560 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001561 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001562 INTEL_PIPE_CRC_SOURCE_MAX,
1563};
1564
Shuang He8bf1e9f2013-10-15 18:55:27 +01001565struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001566 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001567 uint32_t crc[5];
1568};
1569
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001570#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001571struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001572 spinlock_t lock;
1573 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001574 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001575 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001576 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001577 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001578};
1579
Daniel Vetterf99d7062014-06-19 16:01:59 +02001580struct i915_frontbuffer_tracking {
1581 struct mutex lock;
1582
1583 /*
1584 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1585 * scheduled flips.
1586 */
1587 unsigned busy_bits;
1588 unsigned flip_bits;
1589};
1590
Mika Kuoppala72253422014-10-07 17:21:26 +03001591struct i915_wa_reg {
1592 u32 addr;
1593 u32 value;
1594 /* bitmask representing WA bits */
1595 u32 mask;
1596};
1597
1598#define I915_MAX_WA_REGS 16
1599
1600struct i915_workarounds {
1601 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1602 u32 count;
1603};
1604
Jani Nikula77fec552014-03-31 14:27:22 +03001605struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001606 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +00001607 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001608
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001609 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001610
1611 int relative_constants_mode;
1612
1613 void __iomem *regs;
1614
Chris Wilson907b28c2013-07-19 20:36:52 +01001615 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001616
1617 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1618
Daniel Vetter28c70f12012-12-01 13:53:45 +01001619
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001620 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1621 * controller on different i2c buses. */
1622 struct mutex gmbus_mutex;
1623
1624 /**
1625 * Base address of the gmbus and gpio block.
1626 */
1627 uint32_t gpio_mmio_base;
1628
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301629 /* MMIO base address for MIPI regs */
1630 uint32_t mipi_mmio_base;
1631
Daniel Vetter28c70f12012-12-01 13:53:45 +01001632 wait_queue_head_t gmbus_wait_queue;
1633
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001634 struct pci_dev *bridge_dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001635 struct intel_engine_cs ring[I915_NUM_RINGS];
Ben Widawsky3e789982014-06-30 09:53:37 -07001636 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001637 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001638
Daniel Vetterba8286f2014-09-11 07:43:25 +02001639 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001640 struct resource mch_res;
1641
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001642 /* protects the irq masks */
1643 spinlock_t irq_lock;
1644
Sourab Gupta84c33a62014-06-02 16:47:17 +05301645 /* protects the mmio flip data */
1646 spinlock_t mmio_flip_lock;
1647
Imre Deakf8b79e52014-03-04 19:23:07 +02001648 bool display_irqs_enabled;
1649
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001650 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1651 struct pm_qos_request pm_qos;
1652
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001653 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001654 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001655
1656 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001657 union {
1658 u32 irq_mask;
1659 u32 de_irq_mask[I915_MAX_PIPES];
1660 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001661 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001662 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301663 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001664 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001665
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001666 struct work_struct hotplug_work;
Egbert Eichb543fb02013-04-16 13:36:54 +02001667 struct {
1668 unsigned long hpd_last_jiffies;
1669 int hpd_cnt;
1670 enum {
1671 HPD_ENABLED = 0,
1672 HPD_DISABLED = 1,
1673 HPD_MARK_DISABLED = 2
1674 } hpd_mark;
1675 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001676 u32 hpd_event_bits;
Imre Deak63237512014-08-18 15:37:02 +03001677 struct delayed_work hotplug_reenable_work;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001678
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001679 struct i915_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301680 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001681 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001682 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001683
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001684 bool preserve_bios_swizzle;
1685
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001686 /* overlay */
1687 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001688
Jani Nikula58c68772013-11-08 16:48:54 +02001689 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001690 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001691
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001692 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001693 bool no_aux_handshake;
1694
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001695 /* protects panel power sequencer state */
1696 struct mutex pps_mutex;
1697
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001698 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1699 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1700 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1701
1702 unsigned int fsb_freq, mem_freq, is_ddr3;
Imre Deakd60c4472014-03-27 17:45:10 +02001703 unsigned int vlv_cdclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001704 unsigned int hpll_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001705
Daniel Vetter645416f2013-09-02 16:22:25 +02001706 /**
1707 * wq - Driver workqueue for GEM.
1708 *
1709 * NOTE: Work items scheduled here are not allowed to grab any modeset
1710 * locks, for otherwise the flushing done in the pageflip code will
1711 * result in deadlocks.
1712 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001713 struct workqueue_struct *wq;
1714
1715 /* Display functions */
1716 struct drm_i915_display_funcs display;
1717
1718 /* PCH chipset type */
1719 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001720 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001721
1722 unsigned long quirks;
1723
Zhang Ruib8efb172013-02-05 15:41:53 +08001724 enum modeset_restore modeset_restore;
1725 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001726
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001727 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001728 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001729
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001730 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001731 DECLARE_HASHTABLE(mm_structs, 7);
1732 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001733
Daniel Vetter87813422012-05-02 11:49:32 +02001734 /* Kernel Modesetting */
1735
yakui_zhao9b9d1722009-05-31 17:17:17 +08001736 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001737
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001738 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1739 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001740 wait_queue_head_t pending_flip_queue;
1741
Daniel Vetterc4597872013-10-21 21:04:07 +02001742#ifdef CONFIG_DEBUG_FS
1743 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1744#endif
1745
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001746 int num_shared_dpll;
1747 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001748 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001749
Mika Kuoppala72253422014-10-07 17:21:26 +03001750 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001751
Jesse Barnes652c3932009-08-17 13:31:43 -07001752 /* Reclocking support */
1753 bool render_reclock_avail;
1754 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001755 /* indicates the reduced downclock for LVDS*/
1756 int lvds_downclock;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001757
1758 struct i915_frontbuffer_tracking fb_tracking;
1759
Jesse Barnes652c3932009-08-17 13:31:43 -07001760 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001761
Zhenyu Wangc48044112009-12-17 14:48:43 +08001762 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001763
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001764 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001765
Ben Widawsky59124502013-07-04 11:02:05 -07001766 /* Cannot be determined by PCIID. You must always read a register. */
1767 size_t ellc_size;
1768
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001769 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001770 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001771
Daniel Vetter20e4d402012-08-08 23:35:39 +02001772 /* ilk-only ips/rps state. Everything in here is protected by the global
1773 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001774 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001775
Imre Deak83c00f552013-10-25 17:36:47 +03001776 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001777
Rodrigo Vivia031d702013-10-03 16:15:06 -03001778 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001779
Daniel Vetter99584db2012-11-14 17:14:04 +01001780 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001781
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001782 struct drm_i915_gem_object *vlv_pctx;
1783
Daniel Vetter4520f532013-10-09 09:18:51 +02001784#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001785 /* list of fbdev register on this device */
1786 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001787 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001788#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001789
1790 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001791 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001792
Imre Deak58fddc22015-01-08 17:54:14 +02001793 /* hda/i915 audio component */
1794 bool audio_component_registered;
1795
Ben Widawsky254f9652012-06-04 14:42:42 -07001796 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001797 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001798
Damien Lespiau3e683202012-12-11 18:48:29 +00001799 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001800
Daniel Vetter842f1c82014-03-10 10:01:44 +01001801 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001802 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001803 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001804
Ville Syrjälä53615a52013-08-01 16:18:50 +03001805 struct {
1806 /*
1807 * Raw watermark latency values:
1808 * in 0.1us units for WM0,
1809 * in 0.5us units for WM1+.
1810 */
1811 /* primary */
1812 uint16_t pri_latency[5];
1813 /* sprite */
1814 uint16_t spr_latency[5];
1815 /* cursor */
1816 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001817 /*
1818 * Raw watermark memory latency values
1819 * for SKL for all 8 levels
1820 * in 1us units.
1821 */
1822 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001823
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001824 /*
1825 * The skl_wm_values structure is a bit too big for stack
1826 * allocation, so we keep the staging struct where we store
1827 * intermediate results here instead.
1828 */
1829 struct skl_wm_values skl_results;
1830
Ville Syrjälä609cede2013-10-09 19:18:03 +03001831 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001832 union {
1833 struct ilk_wm_values hw;
1834 struct skl_wm_values skl_hw;
1835 };
Ville Syrjälä53615a52013-08-01 16:18:50 +03001836 } wm;
1837
Paulo Zanoni8a187452013-12-06 20:32:13 -02001838 struct i915_runtime_pm pm;
1839
Dave Airlie13cf5502014-06-18 11:29:35 +10001840 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1841 u32 long_hpd_port_mask;
1842 u32 short_hpd_port_mask;
1843 struct work_struct dig_port_work;
1844
Dave Airlie0e32b392014-05-02 14:02:48 +10001845 /*
1846 * if we get a HPD irq from DP and a HPD irq from non-DP
1847 * the non-DP HPD could block the workqueue on a mode config
1848 * mutex getting, that userspace may have taken. However
1849 * userspace is waiting on the DP workqueue to run which is
1850 * blocked behind the non-DP one.
1851 */
1852 struct workqueue_struct *dp_wq;
1853
Oscar Mateoa83014d2014-07-24 17:04:21 +01001854 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1855 struct {
1856 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1857 struct intel_engine_cs *ring,
1858 struct intel_context *ctx,
1859 struct drm_i915_gem_execbuffer2 *args,
1860 struct list_head *vmas,
1861 struct drm_i915_gem_object *batch_obj,
1862 u64 exec_start, u32 flags);
1863 int (*init_rings)(struct drm_device *dev);
1864 void (*cleanup_ring)(struct intel_engine_cs *ring);
1865 void (*stop_ring)(struct intel_engine_cs *ring);
1866 } gt;
1867
John Harrison67e29372014-12-05 13:49:35 +00001868 uint32_t request_uniq;
1869
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001870 /*
1871 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1872 * will be rejected. Instead look for a better place.
1873 */
Jani Nikula77fec552014-03-31 14:27:22 +03001874};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875
Chris Wilson2c1792a2013-08-01 18:39:55 +01001876static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1877{
1878 return dev->dev_private;
1879}
1880
Imre Deak888d0d42015-01-08 17:54:13 +02001881static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1882{
1883 return to_i915(dev_get_drvdata(dev));
1884}
1885
Chris Wilsonb4519512012-05-11 14:29:30 +01001886/* Iterate over initialised rings */
1887#define for_each_ring(ring__, dev_priv__, i__) \
1888 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1889 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1890
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001891enum hdmi_force_audio {
1892 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1893 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1894 HDMI_AUDIO_AUTO, /* trust EDID */
1895 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1896};
1897
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001898#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001899
Chris Wilson37e680a2012-06-07 15:38:42 +01001900struct drm_i915_gem_object_ops {
1901 /* Interface between the GEM object and its backing storage.
1902 * get_pages() is called once prior to the use of the associated set
1903 * of pages before to binding them into the GTT, and put_pages() is
1904 * called after we no longer need them. As we expect there to be
1905 * associated cost with migrating pages between the backing storage
1906 * and making them available for the GPU (e.g. clflush), we may hold
1907 * onto the pages after they are no longer referenced by the GPU
1908 * in case they may be used again shortly (for example migrating the
1909 * pages to a different memory domain within the GTT). put_pages()
1910 * will therefore most likely be called when the object itself is
1911 * being released or under memory pressure (where we attempt to
1912 * reap pages for the shrinker).
1913 */
1914 int (*get_pages)(struct drm_i915_gem_object *);
1915 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001916 int (*dmabuf_export)(struct drm_i915_gem_object *);
1917 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01001918};
1919
Daniel Vettera071fa02014-06-18 23:28:09 +02001920/*
1921 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1922 * considered to be the frontbuffer for the given plane interface-vise. This
1923 * doesn't mean that the hw necessarily already scans it out, but that any
1924 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1925 *
1926 * We have one bit per pipe and per scanout plane type.
1927 */
1928#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1929#define INTEL_FRONTBUFFER_BITS \
1930 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1931#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1932 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1933#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1934 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1935#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1936 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1937#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1938 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02001939#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1940 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02001941
Eric Anholt673a3942008-07-30 12:06:12 -07001942struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001943 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001944
Chris Wilson37e680a2012-06-07 15:38:42 +01001945 const struct drm_i915_gem_object_ops *ops;
1946
Ben Widawsky2f633152013-07-17 12:19:03 -07001947 /** List of VMAs backed by this object */
1948 struct list_head vma_list;
1949
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001950 /** Stolen memory for this object, instead of being backed by shmem. */
1951 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001952 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001953
Chris Wilson69dc4982010-10-19 10:36:51 +01001954 struct list_head ring_list;
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02001955 /** Used in execbuf to temporarily hold a ref */
1956 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07001957
Brad Volkin493018d2014-12-11 12:13:08 -08001958 struct list_head batch_pool_list;
1959
Eric Anholt673a3942008-07-30 12:06:12 -07001960 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001961 * This is set if the object is on the active lists (has pending
1962 * rendering and so a non-zero seqno), and is not set if it i s on
1963 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001964 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001965 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001966
1967 /**
1968 * This is set if the object has been written to since last bound
1969 * to the GTT
1970 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001971 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001972
1973 /**
1974 * Fence register bits (if any) for this object. Will be set
1975 * as needed when mapped into the GTT.
1976 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001977 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001978 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001979
1980 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001981 * Advice: are the backing pages purgeable?
1982 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001983 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001984
1985 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001986 * Current tiling mode for the object.
1987 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001988 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001989 /**
1990 * Whether the tiling parameters for the currently associated fence
1991 * register have changed. Note that for the purposes of tracking
1992 * tiling changes we also treat the unfenced register, the register
1993 * slot that the object occupies whilst it executes a fenced
1994 * command (such as BLT on gen2/3), as a "fence".
1995 */
1996 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001997
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001998 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001999 * Is the object at the current location in the gtt mappable and
2000 * fenceable? Used to avoid costly recalculations.
2001 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002002 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002003
2004 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002005 * Whether the current gtt mapping needs to be mappable (and isn't just
2006 * mappable by accident). Track pin and fault separate for a more
2007 * accurate mappable working set.
2008 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002009 unsigned int fault_mappable:1;
2010 unsigned int pin_mappable:1;
Chris Wilsoncc98b412013-08-09 12:25:09 +01002011 unsigned int pin_display:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002012
Chris Wilsoncaea7472010-11-12 13:53:37 +00002013 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05302014 * Is the object to be mapped as read-only to the GPU
2015 * Only honoured if hardware has relevant pte bit
2016 */
2017 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01002018 unsigned int cache_level:3;
Chris Wilson93dfb402011-03-29 16:59:50 -07002019
Chris Wilson9da3da62012-06-01 15:20:22 +01002020 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01002021
Daniel Vettera071fa02014-06-18 23:28:09 +02002022 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2023
Chris Wilson9da3da62012-06-01 15:20:22 +01002024 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01002025 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07002026
Daniel Vetter1286ff72012-05-10 15:25:09 +02002027 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01002028 void *dma_buf_vmapping;
2029 int vmapping_count;
2030
Chris Wilson1c293ea2012-04-17 15:31:27 +01002031 /** Breadcrumb of last rendering to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00002032 struct drm_i915_gem_request *last_read_req;
2033 struct drm_i915_gem_request *last_write_req;
Chris Wilsoncaea7472010-11-12 13:53:37 +00002034 /** Breadcrumb of last fenced GPU access to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00002035 struct drm_i915_gem_request *last_fenced_req;
Eric Anholt673a3942008-07-30 12:06:12 -07002036
Daniel Vetter778c3542010-05-13 11:49:44 +02002037 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08002038 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07002039
Daniel Vetter80075d42013-10-09 21:23:52 +02002040 /** References from framebuffers, locks out tiling changes. */
2041 unsigned long framebuffer_references;
2042
Eric Anholt280b7132009-03-12 16:56:27 -07002043 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002044 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002045
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002046 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002047 /** for phy allocated objects */
2048 struct drm_dma_handle *phys_handle;
2049
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002050 struct i915_gem_userptr {
2051 uintptr_t ptr;
2052 unsigned read_only :1;
2053 unsigned workers :4;
2054#define I915_GEM_USERPTR_MAX_WORKERS 15
2055
Chris Wilsonad46cb52014-08-07 14:20:40 +01002056 struct i915_mm_struct *mm;
2057 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002058 struct work_struct *work;
2059 } userptr;
2060 };
2061};
Daniel Vetter62b8b212010-04-09 19:05:08 +00002062#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01002063
Daniel Vettera071fa02014-06-18 23:28:09 +02002064void i915_gem_track_fb(struct drm_i915_gem_object *old,
2065 struct drm_i915_gem_object *new,
2066 unsigned frontbuffer_bits);
2067
Eric Anholt673a3942008-07-30 12:06:12 -07002068/**
2069 * Request queue structure.
2070 *
2071 * The request queue allows us to note sequence numbers that have been emitted
2072 * and may be associated with active buffers to be retired.
2073 *
John Harrison97b2a6a2014-11-24 18:49:26 +00002074 * By keeping this list, we can avoid having to do questionable sequence
2075 * number comparisons on buffer last_read|write_seqno. It also allows an
2076 * emission time to be associated with the request for tracking how far ahead
2077 * of the GPU the submission is.
Eric Anholt673a3942008-07-30 12:06:12 -07002078 */
2079struct drm_i915_gem_request {
John Harrisonabfe2622014-11-24 18:49:24 +00002080 struct kref ref;
2081
Zou Nan hai852835f2010-05-21 09:08:56 +08002082 /** On Which ring this request was generated */
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002083 struct intel_engine_cs *ring;
Zou Nan hai852835f2010-05-21 09:08:56 +08002084
Eric Anholt673a3942008-07-30 12:06:12 -07002085 /** GEM sequence number associated with this request. */
2086 uint32_t seqno;
2087
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002088 /** Position in the ringbuffer of the start of the request */
2089 u32 head;
2090
2091 /** Position in the ringbuffer of the end of the request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00002092 u32 tail;
2093
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002094 /** Context related to this request */
Oscar Mateo273497e2014-05-22 14:13:37 +01002095 struct intel_context *ctx;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002096
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002097 /** Batch buffer related to this request if any */
2098 struct drm_i915_gem_object *batch_obj;
2099
Eric Anholt673a3942008-07-30 12:06:12 -07002100 /** Time at which this request was emitted, in jiffies. */
2101 unsigned long emitted_jiffies;
2102
Eric Anholtb9624422009-06-03 07:27:35 +00002103 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002104 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002105
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002106 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002107 /** file_priv list entry for this request */
2108 struct list_head client_list;
John Harrison67e29372014-12-05 13:49:35 +00002109
2110 uint32_t uniq;
Eric Anholt673a3942008-07-30 12:06:12 -07002111};
2112
John Harrisonabfe2622014-11-24 18:49:24 +00002113void i915_gem_request_free(struct kref *req_ref);
2114
John Harrisonb793a002014-11-24 18:49:25 +00002115static inline uint32_t
2116i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2117{
2118 return req ? req->seqno : 0;
2119}
2120
2121static inline struct intel_engine_cs *
2122i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2123{
2124 return req ? req->ring : NULL;
2125}
2126
John Harrisonabfe2622014-11-24 18:49:24 +00002127static inline void
2128i915_gem_request_reference(struct drm_i915_gem_request *req)
2129{
2130 kref_get(&req->ref);
2131}
2132
2133static inline void
2134i915_gem_request_unreference(struct drm_i915_gem_request *req)
2135{
Daniel Vetterf2458602014-11-26 10:26:05 +01002136 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
John Harrisonabfe2622014-11-24 18:49:24 +00002137 kref_put(&req->ref, i915_gem_request_free);
2138}
2139
2140static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2141 struct drm_i915_gem_request *src)
2142{
2143 if (src)
2144 i915_gem_request_reference(src);
2145
2146 if (*pdst)
2147 i915_gem_request_unreference(*pdst);
2148
2149 *pdst = src;
2150}
2151
John Harrison1b5a4332014-11-24 18:49:42 +00002152/*
2153 * XXX: i915_gem_request_completed should be here but currently needs the
2154 * definition of i915_seqno_passed() which is below. It will be moved in
2155 * a later patch when the call to i915_seqno_passed() is obsoleted...
2156 */
2157
Eric Anholt673a3942008-07-30 12:06:12 -07002158struct drm_i915_file_private {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002159 struct drm_i915_private *dev_priv;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +02002160 struct drm_file *file;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002161
Eric Anholt673a3942008-07-30 12:06:12 -07002162 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08002163 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00002164 struct list_head request_list;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002165 struct delayed_work idle_work;
Eric Anholt673a3942008-07-30 12:06:12 -07002166 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07002167 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03002168
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002169 atomic_t rps_wait_boost;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002170 struct intel_engine_cs *bsd_ring;
Eric Anholt673a3942008-07-30 12:06:12 -07002171};
2172
Brad Volkin351e3db2014-02-18 10:15:46 -08002173/*
2174 * A command that requires special handling by the command parser.
2175 */
2176struct drm_i915_cmd_descriptor {
2177 /*
2178 * Flags describing how the command parser processes the command.
2179 *
2180 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2181 * a length mask if not set
2182 * CMD_DESC_SKIP: The command is allowed but does not follow the
2183 * standard length encoding for the opcode range in
2184 * which it falls
2185 * CMD_DESC_REJECT: The command is never allowed
2186 * CMD_DESC_REGISTER: The command should be checked against the
2187 * register whitelist for the appropriate ring
2188 * CMD_DESC_MASTER: The command is allowed if the submitting process
2189 * is the DRM master
2190 */
2191 u32 flags;
2192#define CMD_DESC_FIXED (1<<0)
2193#define CMD_DESC_SKIP (1<<1)
2194#define CMD_DESC_REJECT (1<<2)
2195#define CMD_DESC_REGISTER (1<<3)
2196#define CMD_DESC_BITMASK (1<<4)
2197#define CMD_DESC_MASTER (1<<5)
2198
2199 /*
2200 * The command's unique identification bits and the bitmask to get them.
2201 * This isn't strictly the opcode field as defined in the spec and may
2202 * also include type, subtype, and/or subop fields.
2203 */
2204 struct {
2205 u32 value;
2206 u32 mask;
2207 } cmd;
2208
2209 /*
2210 * The command's length. The command is either fixed length (i.e. does
2211 * not include a length field) or has a length field mask. The flag
2212 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2213 * a length mask. All command entries in a command table must include
2214 * length information.
2215 */
2216 union {
2217 u32 fixed;
2218 u32 mask;
2219 } length;
2220
2221 /*
2222 * Describes where to find a register address in the command to check
2223 * against the ring's register whitelist. Only valid if flags has the
2224 * CMD_DESC_REGISTER bit set.
2225 */
2226 struct {
2227 u32 offset;
2228 u32 mask;
2229 } reg;
2230
2231#define MAX_CMD_DESC_BITMASKS 3
2232 /*
2233 * Describes command checks where a particular dword is masked and
2234 * compared against an expected value. If the command does not match
2235 * the expected value, the parser rejects it. Only valid if flags has
2236 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2237 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002238 *
2239 * If the check specifies a non-zero condition_mask then the parser
2240 * only performs the check when the bits specified by condition_mask
2241 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002242 */
2243 struct {
2244 u32 offset;
2245 u32 mask;
2246 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002247 u32 condition_offset;
2248 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002249 } bits[MAX_CMD_DESC_BITMASKS];
2250};
2251
2252/*
2253 * A table of commands requiring special handling by the command parser.
2254 *
2255 * Each ring has an array of tables. Each table consists of an array of command
2256 * descriptors, which must be sorted with command opcodes in ascending order.
2257 */
2258struct drm_i915_cmd_table {
2259 const struct drm_i915_cmd_descriptor *table;
2260 int count;
2261};
2262
Chris Wilsondbbe9122014-08-09 19:18:43 +01002263/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002264#define __I915__(p) ({ \
2265 struct drm_i915_private *__p; \
2266 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2267 __p = (struct drm_i915_private *)p; \
2268 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2269 __p = to_i915((struct drm_device *)p); \
2270 else \
2271 BUILD_BUG(); \
2272 __p; \
2273})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002274#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002275#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Zou Nan haicae58522010-11-09 17:17:32 +08002276
Chris Wilson87f1f462014-08-09 19:18:42 +01002277#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2278#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002279#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002280#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002281#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002282#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2283#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002284#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2285#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2286#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002287#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002288#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002289#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2290#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002291#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2292#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002293#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002294#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002295#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2296 INTEL_DEVID(dev) == 0x0152 || \
2297 INTEL_DEVID(dev) == 0x015a)
2298#define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2299 INTEL_DEVID(dev) == 0x0106 || \
2300 INTEL_DEVID(dev) == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002301#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Ville Syrjälä6df40272014-04-09 13:28:00 +03002302#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002303#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Ville Syrjälä8179f1f2014-04-09 13:27:59 +03002304#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302305#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002306#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002307#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002308 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002309#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002310 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2311 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2312 (INTEL_DEVID(dev) & 0xf) == 0xe))
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002313#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2314 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002315#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002316 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002317#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002318 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002319/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002320#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2321 INTEL_DEVID(dev) == 0x0A1E)
Ben Widawskyb833d682013-08-23 16:00:07 -07002322#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002323
Jesse Barnes85436692011-04-06 12:11:14 -07002324/*
2325 * The genX designation typically refers to the render engine, so render
2326 * capability related checks should use IS_GEN, while display and other checks
2327 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2328 * chips, etc.).
2329 */
Zou Nan haicae58522010-11-09 17:17:32 +08002330#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2331#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2332#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2333#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2334#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002335#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002336#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002337#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002338
Ben Widawsky73ae4782013-10-15 10:02:57 -07002339#define RENDER_RING (1<<RCS)
2340#define BSD_RING (1<<VCS)
2341#define BLT_RING (1<<BCS)
2342#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002343#define BSD2_RING (1<<VCS2)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002344#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002345#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002346#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2347#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2348#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2349#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002350 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002351#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2352
Ben Widawsky254f9652012-06-04 14:42:42 -07002353#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002354#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002355#define USES_PPGTT(dev) (i915.enable_ppgtt)
2356#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002357
Chris Wilson05394f32010-11-08 19:18:58 +00002358#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002359#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2360
Daniel Vetterb45305f2012-12-17 16:21:27 +01002361/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2362#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002363/*
2364 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2365 * even when in MSI mode. This results in spurious interrupt warnings if the
2366 * legacy irq no. is shared with another device. The kernel then disables that
2367 * interrupt source and so prevents the other device from working properly.
2368 */
2369#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2370#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002371
Zou Nan haicae58522010-11-09 17:17:32 +08002372/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2373 * rows, which changed the alignment requirements and fence programming.
2374 */
2375#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2376 IS_I915GM(dev)))
2377#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2378#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2379#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08002380#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2381#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002382
2383#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2384#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002385#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002386
Damien Lespiaudbf77862014-10-01 20:04:14 +01002387#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002388
Damien Lespiaudd93be52013-04-22 18:40:39 +01002389#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002390#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002391#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2392 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002393#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Imre Deakfd7f8cc2014-04-14 20:41:30 +03002394 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002395#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2396#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002397
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002398#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2399#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2400#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2401#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2402#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2403#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302404#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2405#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002406
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002407#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302408#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002409#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08002410#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2411#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002412#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002413#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002414
Sonika Jindal5fafe292014-07-21 15:23:38 +05302415#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2416
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002417/* DPF == dynamic parity feature */
2418#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2419#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002420
Ben Widawskyc8735b02012-09-07 19:43:39 -07002421#define GT_FREQUENCY_MULTIPLIER 50
2422
Chris Wilson05394f32010-11-08 19:18:58 +00002423#include "i915_trace.h"
2424
Rob Clarkbaa70942013-08-02 13:27:49 -04002425extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002426extern int i915_max_ioctl;
2427
Imre Deakfc49b3d2014-10-23 19:23:27 +03002428extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2429extern int i915_resume_legacy(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002430extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2431extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2432
Jani Nikulad330a952014-01-21 11:24:25 +02002433/* i915_params.c */
2434struct i915_params {
2435 int modeset;
2436 int panel_ignore_lid;
2437 unsigned int powersave;
2438 int semaphores;
2439 unsigned int lvds_downclock;
2440 int lvds_channel_mode;
2441 int panel_use_ssc;
2442 int vbt_sdvo_panel_type;
2443 int enable_rc6;
2444 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02002445 int enable_ppgtt;
Oscar Mateo127f1002014-07-24 17:04:11 +01002446 int enable_execlists;
Jani Nikulad330a952014-01-21 11:24:25 +02002447 int enable_psr;
2448 unsigned int preliminary_hw_support;
2449 int disable_power_well;
2450 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002451 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08002452 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002453 /* leave bools at the end to not create holes */
2454 bool enable_hangcheck;
2455 bool fastboot;
Jani Nikulad330a952014-01-21 11:24:25 +02002456 bool prefault_disable;
2457 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00002458 bool disable_display;
Daniel Vetter7a10dfa2014-04-01 09:33:47 +02002459 bool disable_vtd_wa;
Sourab Gupta84c33a62014-06-02 16:47:17 +05302460 int use_mmio_flip;
Paulo Zanoni59781182014-07-16 17:49:29 -03002461 bool mmio_debug;
Rob Clarke2c719b2014-12-15 13:56:32 -05002462 bool verbose_state_checks;
Jani Nikulad330a952014-01-21 11:24:25 +02002463};
2464extern struct i915_params i915 __read_mostly;
2465
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466 /* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002467extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002468extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002469extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002470extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002471extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002472 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002473extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002474 struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002475extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002476#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002477extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2478 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002479#endif
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07002480extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002481extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002482extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2483extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2484extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2485extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002486int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Imre Deak1d0d3432014-08-18 14:42:44 +03002487void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002488
Linus Torvalds1da177e2005-04-16 15:20:36 -07002489/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002490void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002491__printf(3, 4)
2492void i915_handle_error(struct drm_device *dev, bool wedged,
2493 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002494
Daniel Vetterb9632912014-09-30 10:56:44 +02002495extern void intel_irq_init(struct drm_i915_private *dev_priv);
2496extern void intel_hpd_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002497int intel_irq_install(struct drm_i915_private *dev_priv);
2498void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002499
2500extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002501extern void intel_uncore_early_sanitize(struct drm_device *dev,
2502 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002503extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01002504extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002505extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002506extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002507
Keith Packard7c463582008-11-04 02:03:27 -08002508void
Jani Nikula50227e12014-03-31 14:27:21 +03002509i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002510 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002511
2512void
Jani Nikula50227e12014-03-31 14:27:21 +03002513i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002514 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002515
Imre Deakf8b79e52014-03-04 19:23:07 +02002516void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2517void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +02002518void
2519ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2520void
2521ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2522void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2523 uint32_t interrupt_mask,
2524 uint32_t enabled_irq_mask);
2525#define ibx_enable_display_interrupt(dev_priv, bits) \
2526 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2527#define ibx_disable_display_interrupt(dev_priv, bits) \
2528 ibx_display_interrupt_update((dev_priv), (bits), 0)
Imre Deakf8b79e52014-03-04 19:23:07 +02002529
Eric Anholt673a3942008-07-30 12:06:12 -07002530/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002531int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2532 struct drm_file *file_priv);
2533int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2534 struct drm_file *file_priv);
2535int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2536 struct drm_file *file_priv);
2537int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2538 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002539int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2540 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002541int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2542 struct drm_file *file_priv);
2543int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2544 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002545void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2546 struct intel_engine_cs *ring);
2547void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2548 struct drm_file *file,
2549 struct intel_engine_cs *ring,
2550 struct drm_i915_gem_object *obj);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002551int i915_gem_ringbuffer_submission(struct drm_device *dev,
2552 struct drm_file *file,
2553 struct intel_engine_cs *ring,
2554 struct intel_context *ctx,
2555 struct drm_i915_gem_execbuffer2 *args,
2556 struct list_head *vmas,
2557 struct drm_i915_gem_object *batch_obj,
2558 u64 exec_start, u32 flags);
Eric Anholt673a3942008-07-30 12:06:12 -07002559int i915_gem_execbuffer(struct drm_device *dev, void *data,
2560 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002561int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2562 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002563int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2564 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002565int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2566 struct drm_file *file);
2567int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2568 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002569int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2570 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002571int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2572 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002573int i915_gem_set_tiling(struct drm_device *dev, void *data,
2574 struct drm_file *file_priv);
2575int i915_gem_get_tiling(struct drm_device *dev, void *data,
2576 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002577int i915_gem_init_userptr(struct drm_device *dev);
2578int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2579 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002580int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2581 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002582int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2583 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002584void i915_gem_load(struct drm_device *dev);
Chris Wilson21ab4e72014-09-09 11:16:08 +01002585unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2586 long target,
2587 unsigned flags);
2588#define I915_SHRINK_PURGEABLE 0x1
2589#define I915_SHRINK_UNBOUND 0x2
2590#define I915_SHRINK_BOUND 0x4
Chris Wilson42dcedd2012-11-15 11:32:30 +00002591void *i915_gem_object_alloc(struct drm_device *dev);
2592void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002593void i915_gem_object_init(struct drm_i915_gem_object *obj,
2594 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002595struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2596 size_t size);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002597void i915_init_vm(struct drm_i915_private *dev_priv,
2598 struct i915_address_space *vm);
Eric Anholt673a3942008-07-30 12:06:12 -07002599void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002600void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002601
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002602#define PIN_MAPPABLE 0x1
2603#define PIN_NONBLOCK 0x2
Daniel Vetterbf3d1492014-02-14 14:01:12 +01002604#define PIN_GLOBAL 0x4
Chris Wilsond23db882014-05-23 08:48:08 +02002605#define PIN_OFFSET_BIAS 0x8
2606#define PIN_OFFSET_MASK (~4095)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002607int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
2608 struct i915_address_space *vm,
2609 uint32_t alignment,
2610 uint64_t flags,
2611 const struct i915_ggtt_view *view);
2612static inline
Chris Wilson20217462010-11-23 15:26:33 +00002613int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
Ben Widawskyc37e2202013-07-31 16:59:58 -07002614 struct i915_address_space *vm,
Chris Wilson20217462010-11-23 15:26:33 +00002615 uint32_t alignment,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002616 uint64_t flags)
2617{
2618 return i915_gem_object_pin_view(obj, vm, alignment, flags,
2619 &i915_ggtt_view_normal);
2620}
2621
2622int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2623 u32 flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002624int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002625int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002626void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002627void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002628
Brad Volkin4c914c02014-02-18 10:15:45 -08002629int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2630 int *needs_clflush);
2631
Chris Wilson37e680a2012-06-07 15:38:42 +01002632int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01002633static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2634{
Imre Deak67d5a502013-02-18 19:28:02 +02002635 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01002636
Imre Deak67d5a502013-02-18 19:28:02 +02002637 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02002638 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02002639
2640 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01002641}
Chris Wilsona5570172012-09-04 21:02:54 +01002642static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2643{
2644 BUG_ON(obj->pages == NULL);
2645 obj->pages_pin_count++;
2646}
2647static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2648{
2649 BUG_ON(obj->pages_pin_count == 0);
2650 obj->pages_pin_count--;
2651}
2652
Chris Wilson54cf91d2010-11-25 18:00:26 +00002653int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002654int i915_gem_object_sync(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002655 struct intel_engine_cs *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002656void i915_vma_move_to_active(struct i915_vma *vma,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002657 struct intel_engine_cs *ring);
Dave Airlieff72145b2011-02-07 12:16:14 +10002658int i915_gem_dumb_create(struct drm_file *file_priv,
2659 struct drm_device *dev,
2660 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002661int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2662 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002663/**
2664 * Returns true if seq1 is later than seq2.
2665 */
2666static inline bool
2667i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2668{
2669 return (int32_t)(seq1 - seq2) >= 0;
2670}
2671
John Harrison1b5a4332014-11-24 18:49:42 +00002672static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2673 bool lazy_coherency)
2674{
2675 u32 seqno;
2676
2677 BUG_ON(req == NULL);
2678
2679 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2680
2681 return i915_seqno_passed(seqno, req->seqno);
2682}
2683
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002684int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2685int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002686int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002687int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002688
Daniel Vetterd8ffa602014-05-13 12:11:26 +02002689bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2690void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002691
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002692struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002693i915_gem_find_active_request(struct intel_engine_cs *ring);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002694
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002695bool i915_gem_retire_requests(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002696void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002697int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002698 bool interruptible);
John Harrisonb6660d52014-11-24 18:49:30 +00002699int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
Sourab Gupta84c33a62014-06-02 16:47:17 +05302700
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002701static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2702{
2703 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002704 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002705}
2706
2707static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2708{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002709 return atomic_read(&error->reset_counter) & I915_WEDGED;
2710}
2711
2712static inline u32 i915_reset_count(struct i915_gpu_error *error)
2713{
2714 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002715}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002716
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002717static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2718{
2719 return dev_priv->gpu_error.stop_rings == 0 ||
2720 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2721}
2722
2723static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2724{
2725 return dev_priv->gpu_error.stop_rings == 0 ||
2726 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2727}
2728
Chris Wilson069efc12010-09-30 16:53:18 +01002729void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002730bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilsona8198ee2011-04-13 22:04:09 +01002731int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01002732int __must_check i915_gem_init(struct drm_device *dev);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002733int i915_gem_init_rings(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002734int __must_check i915_gem_init_hw(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002735int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002736void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002737void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002738int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002739int __must_check i915_gem_suspend(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002740int __i915_add_request(struct intel_engine_cs *ring,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002741 struct drm_file *file,
John Harrison9400ae52014-11-24 18:49:36 +00002742 struct drm_i915_gem_object *batch_obj);
2743#define i915_add_request(ring) \
2744 __i915_add_request(ring, NULL, NULL)
John Harrison9c654812014-11-24 18:49:35 +00002745int __i915_wait_request(struct drm_i915_gem_request *req,
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02002746 unsigned reset_counter,
2747 bool interruptible,
2748 s64 *timeout,
2749 struct drm_i915_file_private *file_priv);
Daniel Vettera4b3a572014-11-26 14:17:05 +01002750int __must_check i915_wait_request(struct drm_i915_gem_request *req);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002751int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002752int __must_check
2753i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2754 bool write);
2755int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002756i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2757int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002758i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2759 u32 alignment,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002760 struct intel_engine_cs *pipelined);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002761void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
Chris Wilson00731152014-05-21 12:42:56 +01002762int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002763 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002764int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002765void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002766
Chris Wilson467cffb2011-03-07 10:42:03 +00002767uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002768i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2769uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02002770i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2771 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002772
Chris Wilsone4ffd172011-04-04 09:44:39 +01002773int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2774 enum i915_cache_level cache_level);
2775
Daniel Vetter1286ff72012-05-10 15:25:09 +02002776struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2777 struct dma_buf *dma_buf);
2778
2779struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2780 struct drm_gem_object *gem_obj, int flags);
2781
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002782void i915_gem_restore_fences(struct drm_device *dev);
2783
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002784unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
2785 struct i915_address_space *vm,
2786 enum i915_ggtt_view_type view);
2787static inline
Ben Widawskya70a3142013-07-31 16:59:56 -07002788unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002789 struct i915_address_space *vm)
2790{
2791 return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL);
2792}
Ben Widawskya70a3142013-07-31 16:59:56 -07002793bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002794bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
2795 struct i915_address_space *vm,
2796 enum i915_ggtt_view_type view);
2797static inline
Ben Widawskya70a3142013-07-31 16:59:56 -07002798bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002799 struct i915_address_space *vm)
2800{
2801 return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL);
2802}
2803
Ben Widawskya70a3142013-07-31 16:59:56 -07002804unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2805 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002806struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
2807 struct i915_address_space *vm,
2808 const struct i915_ggtt_view *view);
2809static inline
Ben Widawskya70a3142013-07-31 16:59:56 -07002810struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002811 struct i915_address_space *vm)
2812{
2813 return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal);
2814}
2815
2816struct i915_vma *
2817i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2818 struct i915_address_space *vm,
2819 const struct i915_ggtt_view *view);
2820
2821static inline
Ben Widawskyaccfef22013-08-14 11:38:35 +02002822struct i915_vma *
2823i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002824 struct i915_address_space *vm)
2825{
2826 return i915_gem_obj_lookup_or_create_vma_view(obj, vm,
2827 &i915_ggtt_view_normal);
2828}
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002829
2830struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08002831static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2832 struct i915_vma *vma;
2833 list_for_each_entry(vma, &obj->vma_list, vma_link)
2834 if (vma->pin_count > 0)
2835 return true;
2836 return false;
2837}
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002838
Ben Widawskya70a3142013-07-31 16:59:56 -07002839/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002840#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07002841 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2842static inline bool i915_is_ggtt(struct i915_address_space *vm)
2843{
2844 struct i915_address_space *ggtt =
2845 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2846 return vm == ggtt;
2847}
2848
Daniel Vetter841cd772014-08-06 15:04:48 +02002849static inline struct i915_hw_ppgtt *
2850i915_vm_to_ppgtt(struct i915_address_space *vm)
2851{
2852 WARN_ON(i915_is_ggtt(vm));
2853
2854 return container_of(vm, struct i915_hw_ppgtt, base);
2855}
2856
2857
Ben Widawskya70a3142013-07-31 16:59:56 -07002858static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2859{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002860 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002861}
2862
2863static inline unsigned long
2864i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2865{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002866 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002867}
2868
2869static inline unsigned long
2870i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2871{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002872 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002873}
Ben Widawskyc37e2202013-07-31 16:59:58 -07002874
2875static inline int __must_check
2876i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2877 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002878 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07002879{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002880 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2881 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07002882}
Ben Widawskya70a3142013-07-31 16:59:56 -07002883
Daniel Vetterb2871102014-02-14 14:01:19 +01002884static inline int
2885i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2886{
2887 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2888}
2889
2890void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2891
Ben Widawsky254f9652012-06-04 14:42:42 -07002892/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02002893int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07002894void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08002895void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08002896int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
Ben Widawsky2fa48d82013-12-06 14:11:04 -08002897int i915_gem_context_enable(struct drm_i915_private *dev_priv);
Ben Widawsky254f9652012-06-04 14:42:42 -07002898void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002899int i915_switch_context(struct intel_engine_cs *ring,
Oscar Mateo273497e2014-05-22 14:13:37 +01002900 struct intel_context *to);
2901struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08002902i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002903void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01002904struct drm_i915_gem_object *
2905i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01002906static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002907{
Chris Wilson691e6412014-04-09 09:07:36 +01002908 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002909}
2910
Oscar Mateo273497e2014-05-22 14:13:37 +01002911static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002912{
Chris Wilson691e6412014-04-09 09:07:36 +01002913 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002914}
2915
Oscar Mateo273497e2014-05-22 14:13:37 +01002916static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002917{
Oscar Mateo821d66d2014-07-03 16:28:00 +01002918 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002919}
2920
Ben Widawsky84624812012-06-04 14:42:54 -07002921int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2922 struct drm_file *file);
2923int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2924 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08002925int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2926 struct drm_file *file_priv);
2927int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2928 struct drm_file *file_priv);
Daniel Vetter1286ff72012-05-10 15:25:09 +02002929
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002930/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07002931int __must_check i915_gem_evict_something(struct drm_device *dev,
2932 struct i915_address_space *vm,
2933 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01002934 unsigned alignment,
2935 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02002936 unsigned long start,
2937 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002938 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07002939int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02002940int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002941
Ben Widawsky0260c422014-03-22 22:47:21 -07002942/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07002943static inline void i915_gem_chipset_flush(struct drm_device *dev)
2944{
Chris Wilson05394f32010-11-08 19:18:58 +00002945 if (INTEL_INFO(dev)->gen < 6)
2946 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01002947}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08002948
Chris Wilson9797fbf2012-04-24 15:47:39 +01002949/* i915_gem_stolen.c */
2950int i915_gem_init_stolen(struct drm_device *dev);
Ben Widawsky5e59f712014-06-30 10:41:24 -07002951int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
Chris Wilson11be49e2012-11-15 11:32:20 +00002952void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002953void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002954struct drm_i915_gem_object *
2955i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08002956struct drm_i915_gem_object *
2957i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2958 u32 stolen_offset,
2959 u32 gtt_offset,
2960 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002961
Eric Anholt673a3942008-07-30 12:06:12 -07002962/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01002963static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00002964{
Jani Nikula50227e12014-03-31 14:27:21 +03002965 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00002966
2967 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2968 obj->tiling_mode != I915_TILING_NONE;
2969}
2970
Eric Anholt673a3942008-07-30 12:06:12 -07002971void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -07002972void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2973void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002974
2975/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01002976#if WATCH_LISTS
2977int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002978#else
Chris Wilson23bc5982010-09-29 16:10:57 +01002979#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07002980#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002981
Ben Gamari20172632009-02-17 20:08:50 -05002982/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04002983int i915_debugfs_init(struct drm_minor *minor);
2984void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002985#ifdef CONFIG_DEBUG_FS
Damien Lespiau07144422013-10-15 18:55:40 +01002986void intel_display_crc_init(struct drm_device *dev);
2987#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002988static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01002989#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03002990
2991/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002992__printf(2, 3)
2993void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03002994int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2995 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002996int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01002997 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002998 size_t count, loff_t pos);
2999static inline void i915_error_state_buf_release(
3000 struct drm_i915_error_state_buf *eb)
3001{
3002 kfree(eb->buf);
3003}
Mika Kuoppala58174462014-02-25 17:11:26 +02003004void i915_capture_error_state(struct drm_device *dev, bool wedge,
3005 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003006void i915_error_state_get(struct drm_device *dev,
3007 struct i915_error_state_file_priv *error_priv);
3008void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3009void i915_destroy_error_state(struct drm_device *dev);
3010
3011void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003012const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003013
Brad Volkin493018d2014-12-11 12:13:08 -08003014/* i915_gem_batch_pool.c */
3015void i915_gem_batch_pool_init(struct drm_device *dev,
3016 struct i915_gem_batch_pool *pool);
3017void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
3018struct drm_i915_gem_object*
3019i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
3020
Brad Volkin351e3db2014-02-18 10:15:46 -08003021/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08003022int i915_cmd_parser_get_version(void);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003023int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3024void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3025bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3026int i915_parse_cmds(struct intel_engine_cs *ring,
Brad Volkin351e3db2014-02-18 10:15:46 -08003027 struct drm_i915_gem_object *batch_obj,
Brad Volkin78a42372014-12-11 12:13:09 -08003028 struct drm_i915_gem_object *shadow_batch_obj,
Brad Volkin351e3db2014-02-18 10:15:46 -08003029 u32 batch_start_offset,
Brad Volkinb9ffd802014-12-11 12:13:10 -08003030 u32 batch_len,
Brad Volkin351e3db2014-02-18 10:15:46 -08003031 bool is_master);
3032
Jesse Barnes317c35d2008-08-25 15:11:06 -07003033/* i915_suspend.c */
3034extern int i915_save_state(struct drm_device *dev);
3035extern int i915_restore_state(struct drm_device *dev);
3036
Daniel Vetterd8157a32013-01-25 17:53:20 +01003037/* i915_ums.c */
3038void i915_save_display_reg(struct drm_device *dev);
3039void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07003040
Ben Widawsky0136db582012-04-10 21:17:01 -07003041/* i915_sysfs.c */
3042void i915_setup_sysfs(struct drm_device *dev_priv);
3043void i915_teardown_sysfs(struct drm_device *dev_priv);
3044
Chris Wilsonf899fc62010-07-20 15:44:45 -07003045/* intel_i2c.c */
3046extern int intel_setup_gmbus(struct drm_device *dev);
3047extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003048static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003049{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08003050 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003051}
3052
3053extern struct i2c_adapter *intel_gmbus_get_adapter(
3054 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01003055extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3056extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003057static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003058{
3059 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3060}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003061extern void intel_i2c_reset(struct drm_device *dev);
3062
Chris Wilson3b617962010-08-24 09:02:58 +01003063/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003064#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08003065extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01003066extern void intel_opregion_init(struct drm_device *dev);
3067extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01003068extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003069extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3070 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003071extern int intel_opregion_notify_adapter(struct drm_device *dev,
3072 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04003073#else
Lv Zheng27d50c82013-12-06 16:52:05 +08003074static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01003075static inline void intel_opregion_init(struct drm_device *dev) { return; }
3076static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01003077static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003078static inline int
3079intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3080{
3081 return 0;
3082}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003083static inline int
3084intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3085{
3086 return 0;
3087}
Len Brown65e082c2008-10-24 17:18:10 -04003088#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003089
Jesse Barnes723bfd72010-10-07 16:01:13 -07003090/* intel_acpi.c */
3091#ifdef CONFIG_ACPI
3092extern void intel_register_dsm_handler(void);
3093extern void intel_unregister_dsm_handler(void);
3094#else
3095static inline void intel_register_dsm_handler(void) { return; }
3096static inline void intel_unregister_dsm_handler(void) { return; }
3097#endif /* CONFIG_ACPI */
3098
Jesse Barnes79e53942008-11-07 14:24:08 -08003099/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003100extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003101extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003102extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003103extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02003104extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003105extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01003106extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3107 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01003108extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003109extern void i915_redisable_vga_power_on(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003110extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003111extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08003112extern void gen6_set_rps(struct drm_device *dev, u8 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003113extern void valleyview_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003114extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3115 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04003116extern void intel_detect_pch(struct drm_device *dev);
3117extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07003118extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003119
Ben Widawsky2911a352012-04-05 14:47:36 -07003120extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003121int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3122 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02003123int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3124 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003125
Sourab Gupta84c33a62014-06-02 16:47:17 +05303126void intel_notify_mmio_flip(struct intel_engine_cs *ring);
3127
Chris Wilson6ef3d422010-08-04 20:26:07 +01003128/* overlay */
3129extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003130extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3131 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003132
3133extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003134extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003135 struct drm_device *dev,
3136 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003137
Ben Widawskyb7287d82011-04-25 11:22:22 -07003138/* On SNB platform, before reading ring registers forcewake bit
3139 * must be set to prevent GT core from power down and stale values being
3140 * returned.
3141 */
Deepak Sc8d9a592013-11-23 14:55:42 +05303142void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
3143void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
Paulo Zanonie998c402014-02-21 13:52:26 -03003144void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07003145
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003146int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3147int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003148
3149/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303150u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3151void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003152u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003153u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3154void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3155u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3156void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3157u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3158void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003159u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3160void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003161u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3162void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003163u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3164void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003165u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3166 enum intel_sbi_destination destination);
3167void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3168 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303169u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3170void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003171
Ville Syrjälä2ec38152013-11-05 22:42:29 +02003172int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
3173int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
Ben Widawsky42c05262012-09-26 10:34:00 -07003174
Deepak Sc8d9a592013-11-23 14:55:42 +05303175#define FORCEWAKE_RENDER (1 << 0)
3176#define FORCEWAKE_MEDIA (1 << 1)
Zhe Wang38cff0b2014-11-04 17:07:04 +00003177#define FORCEWAKE_BLITTER (1 << 2)
3178#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
3179 FORCEWAKE_BLITTER)
Deepak Sc8d9a592013-11-23 14:55:42 +05303180
3181
Ben Widawsky0b274482013-10-04 21:22:51 -07003182#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3183#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003184
Ben Widawsky0b274482013-10-04 21:22:51 -07003185#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3186#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3187#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3188#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003189
Ben Widawsky0b274482013-10-04 21:22:51 -07003190#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3191#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3192#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3193#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003194
Chris Wilson698b3132014-03-21 13:16:43 +00003195/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3196 * will be implemented using 2 32-bit writes in an arbitrary order with
3197 * an arbitrary delay between them. This can cause the hardware to
3198 * act upon the intermediate value, possibly leading to corruption and
3199 * machine death. You have been warned.
3200 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003201#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3202#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003203
Chris Wilson50877442014-03-21 12:41:53 +00003204#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3205 u32 upper = I915_READ(upper_reg); \
3206 u32 lower = I915_READ(lower_reg); \
3207 u32 tmp = I915_READ(upper_reg); \
3208 if (upper != tmp) { \
3209 upper = tmp; \
3210 lower = I915_READ(lower_reg); \
3211 WARN_ON(I915_READ(upper_reg) != upper); \
3212 } \
3213 (u64)upper << 32 | lower; })
3214
Zou Nan haicae58522010-11-09 17:17:32 +08003215#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3216#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3217
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003218/* "Broadcast RGB" property */
3219#define INTEL_BROADCAST_RGB_AUTO 0
3220#define INTEL_BROADCAST_RGB_FULL 1
3221#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003222
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003223static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3224{
Sonika Jindal92e23b92014-07-21 15:23:40 +05303225 if (IS_VALLEYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003226 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303227 else if (INTEL_INFO(dev)->gen >= 5)
3228 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003229 else
3230 return VGACNTRL;
3231}
3232
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003233static inline void __user *to_user_ptr(u64 address)
3234{
3235 return (void __user *)(uintptr_t)address;
3236}
3237
Imre Deakdf977292013-05-21 20:03:17 +03003238static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3239{
3240 unsigned long j = msecs_to_jiffies(m);
3241
3242 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3243}
3244
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003245static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3246{
3247 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3248}
3249
Imre Deakdf977292013-05-21 20:03:17 +03003250static inline unsigned long
3251timespec_to_jiffies_timeout(const struct timespec *value)
3252{
3253 unsigned long j = timespec_to_jiffies(value);
3254
3255 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3256}
3257
Paulo Zanonidce56b32013-12-19 14:29:40 -02003258/*
3259 * If you need to wait X milliseconds between events A and B, but event B
3260 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3261 * when event A happened, then just before event B you call this function and
3262 * pass the timestamp as the first argument, and X as the second argument.
3263 */
3264static inline void
3265wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3266{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003267 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003268
3269 /*
3270 * Don't re-read the value of "jiffies" every time since it may change
3271 * behind our back and break the math.
3272 */
3273 tmp_jiffies = jiffies;
3274 target_jiffies = timestamp_jiffies +
3275 msecs_to_jiffies_timeout(to_wait_ms);
3276
3277 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003278 remaining_jiffies = target_jiffies - tmp_jiffies;
3279 while (remaining_jiffies)
3280 remaining_jiffies =
3281 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003282 }
3283}
3284
John Harrison581c26e82014-11-24 18:49:39 +00003285static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3286 struct drm_i915_gem_request *req)
3287{
3288 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3289 i915_gem_request_assign(&ring->trace_irq_req, req);
3290}
3291
Linus Torvalds1da177e2005-04-16 15:20:36 -07003292#endif