Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Linux MegaRAID driver for SAS based RAID controllers |
| 4 | * |
| 5 | * Copyright (c) 2003-2005 LSI Logic Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * FILE : megaraid_sas.h |
| 13 | */ |
| 14 | |
| 15 | #ifndef LSI_MEGARAID_SAS_H |
| 16 | #define LSI_MEGARAID_SAS_H |
| 17 | |
| 18 | /** |
| 19 | * MegaRAID SAS Driver meta data |
| 20 | */ |
Sumant Patro | 0e98936 | 2006-06-20 15:32:37 -0700 | [diff] [blame] | 21 | #define MEGASAS_VERSION "00.00.03.01" |
| 22 | #define MEGASAS_RELDATE "May 14, 2006" |
| 23 | #define MEGASAS_EXT_VERSION "Sun May 14 22:49:52 PDT 2006" |
| 24 | |
| 25 | /* |
| 26 | * Device IDs |
| 27 | */ |
| 28 | #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 |
| 29 | #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 |
| 30 | |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 31 | /* |
| 32 | * ===================================== |
| 33 | * MegaRAID SAS MFI firmware definitions |
| 34 | * ===================================== |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for |
| 39 | * protocol between the software and firmware. Commands are issued using |
| 40 | * "message frames" |
| 41 | */ |
| 42 | |
| 43 | /** |
| 44 | * FW posts its state in upper 4 bits of outbound_msg_0 register |
| 45 | */ |
| 46 | #define MFI_STATE_MASK 0xF0000000 |
| 47 | #define MFI_STATE_UNDEFINED 0x00000000 |
| 48 | #define MFI_STATE_BB_INIT 0x10000000 |
| 49 | #define MFI_STATE_FW_INIT 0x40000000 |
| 50 | #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 |
| 51 | #define MFI_STATE_FW_INIT_2 0x70000000 |
| 52 | #define MFI_STATE_DEVICE_SCAN 0x80000000 |
Sumant Patro | e3bbff9 | 2006-10-03 12:28:49 -0700 | [diff] [blame] | 53 | #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 54 | #define MFI_STATE_FLUSH_CACHE 0xA0000000 |
| 55 | #define MFI_STATE_READY 0xB0000000 |
| 56 | #define MFI_STATE_OPERATIONAL 0xC0000000 |
| 57 | #define MFI_STATE_FAULT 0xF0000000 |
| 58 | |
| 59 | #define MEGAMFI_FRAME_SIZE 64 |
| 60 | |
| 61 | /** |
| 62 | * During FW init, clear pending cmds & reset state using inbound_msg_0 |
| 63 | * |
| 64 | * ABORT : Abort all pending cmds |
| 65 | * READY : Move from OPERATIONAL to READY state; discard queue info |
| 66 | * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) |
| 67 | * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver |
Sumant Patro | e3bbff9 | 2006-10-03 12:28:49 -0700 | [diff] [blame] | 68 | * HOTPLUG : Resume from Hotplug |
| 69 | * MFI_STOP_ADP : Send signal to FW to stop processing |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 70 | */ |
Sumant Patro | e3bbff9 | 2006-10-03 12:28:49 -0700 | [diff] [blame] | 71 | #define MFI_INIT_ABORT 0x00000001 |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 72 | #define MFI_INIT_READY 0x00000002 |
| 73 | #define MFI_INIT_MFIMODE 0x00000004 |
| 74 | #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 |
Sumant Patro | e3bbff9 | 2006-10-03 12:28:49 -0700 | [diff] [blame] | 75 | #define MFI_INIT_HOTPLUG 0x00000010 |
| 76 | #define MFI_STOP_ADP 0x00000020 |
| 77 | #define MFI_RESET_FLAGS MFI_INIT_READY| \ |
| 78 | MFI_INIT_MFIMODE| \ |
| 79 | MFI_INIT_ABORT |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 80 | |
| 81 | /** |
| 82 | * MFI frame flags |
| 83 | */ |
| 84 | #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 |
| 85 | #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 |
| 86 | #define MFI_FRAME_SGL32 0x0000 |
| 87 | #define MFI_FRAME_SGL64 0x0002 |
| 88 | #define MFI_FRAME_SENSE32 0x0000 |
| 89 | #define MFI_FRAME_SENSE64 0x0004 |
| 90 | #define MFI_FRAME_DIR_NONE 0x0000 |
| 91 | #define MFI_FRAME_DIR_WRITE 0x0008 |
| 92 | #define MFI_FRAME_DIR_READ 0x0010 |
| 93 | #define MFI_FRAME_DIR_BOTH 0x0018 |
| 94 | |
| 95 | /** |
| 96 | * Definition for cmd_status |
| 97 | */ |
| 98 | #define MFI_CMD_STATUS_POLL_MODE 0xFF |
| 99 | |
| 100 | /** |
| 101 | * MFI command opcodes |
| 102 | */ |
| 103 | #define MFI_CMD_INIT 0x00 |
| 104 | #define MFI_CMD_LD_READ 0x01 |
| 105 | #define MFI_CMD_LD_WRITE 0x02 |
| 106 | #define MFI_CMD_LD_SCSI_IO 0x03 |
| 107 | #define MFI_CMD_PD_SCSI_IO 0x04 |
| 108 | #define MFI_CMD_DCMD 0x05 |
| 109 | #define MFI_CMD_ABORT 0x06 |
| 110 | #define MFI_CMD_SMP 0x07 |
| 111 | #define MFI_CMD_STP 0x08 |
| 112 | |
| 113 | #define MR_DCMD_CTRL_GET_INFO 0x01010000 |
| 114 | |
| 115 | #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 |
| 116 | #define MR_FLUSH_CTRL_CACHE 0x01 |
| 117 | #define MR_FLUSH_DISK_CACHE 0x02 |
| 118 | |
| 119 | #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 |
| 120 | #define MR_ENABLE_DRIVE_SPINDOWN 0x01 |
| 121 | |
| 122 | #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 |
| 123 | #define MR_DCMD_CTRL_EVENT_GET 0x01040300 |
| 124 | #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 |
| 125 | #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 |
| 126 | |
| 127 | #define MR_DCMD_CLUSTER 0x08000000 |
| 128 | #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 |
| 129 | #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 |
| 130 | |
| 131 | /** |
| 132 | * MFI command completion codes |
| 133 | */ |
| 134 | enum MFI_STAT { |
| 135 | MFI_STAT_OK = 0x00, |
| 136 | MFI_STAT_INVALID_CMD = 0x01, |
| 137 | MFI_STAT_INVALID_DCMD = 0x02, |
| 138 | MFI_STAT_INVALID_PARAMETER = 0x03, |
| 139 | MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, |
| 140 | MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, |
| 141 | MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, |
| 142 | MFI_STAT_APP_IN_USE = 0x07, |
| 143 | MFI_STAT_APP_NOT_INITIALIZED = 0x08, |
| 144 | MFI_STAT_ARRAY_INDEX_INVALID = 0x09, |
| 145 | MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, |
| 146 | MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, |
| 147 | MFI_STAT_DEVICE_NOT_FOUND = 0x0c, |
| 148 | MFI_STAT_DRIVE_TOO_SMALL = 0x0d, |
| 149 | MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, |
| 150 | MFI_STAT_FLASH_BUSY = 0x0f, |
| 151 | MFI_STAT_FLASH_ERROR = 0x10, |
| 152 | MFI_STAT_FLASH_IMAGE_BAD = 0x11, |
| 153 | MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, |
| 154 | MFI_STAT_FLASH_NOT_OPEN = 0x13, |
| 155 | MFI_STAT_FLASH_NOT_STARTED = 0x14, |
| 156 | MFI_STAT_FLUSH_FAILED = 0x15, |
| 157 | MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, |
| 158 | MFI_STAT_LD_CC_IN_PROGRESS = 0x17, |
| 159 | MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, |
| 160 | MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, |
| 161 | MFI_STAT_LD_MAX_CONFIGURED = 0x1a, |
| 162 | MFI_STAT_LD_NOT_OPTIMAL = 0x1b, |
| 163 | MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, |
| 164 | MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, |
| 165 | MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, |
| 166 | MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, |
| 167 | MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, |
| 168 | MFI_STAT_MFC_HW_ERROR = 0x21, |
| 169 | MFI_STAT_NO_HW_PRESENT = 0x22, |
| 170 | MFI_STAT_NOT_FOUND = 0x23, |
| 171 | MFI_STAT_NOT_IN_ENCL = 0x24, |
| 172 | MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, |
| 173 | MFI_STAT_PD_TYPE_WRONG = 0x26, |
| 174 | MFI_STAT_PR_DISABLED = 0x27, |
| 175 | MFI_STAT_ROW_INDEX_INVALID = 0x28, |
| 176 | MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, |
| 177 | MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, |
| 178 | MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, |
| 179 | MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, |
| 180 | MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, |
| 181 | MFI_STAT_SCSI_IO_FAILED = 0x2e, |
| 182 | MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, |
| 183 | MFI_STAT_SHUTDOWN_FAILED = 0x30, |
| 184 | MFI_STAT_TIME_NOT_SET = 0x31, |
| 185 | MFI_STAT_WRONG_STATE = 0x32, |
| 186 | MFI_STAT_LD_OFFLINE = 0x33, |
| 187 | MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, |
| 188 | MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, |
| 189 | MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, |
| 190 | MFI_STAT_I2C_ERRORS_DETECTED = 0x37, |
| 191 | MFI_STAT_PCI_ERRORS_DETECTED = 0x38, |
| 192 | |
| 193 | MFI_STAT_INVALID_STATUS = 0xFF |
| 194 | }; |
| 195 | |
| 196 | /* |
| 197 | * Number of mailbox bytes in DCMD message frame |
| 198 | */ |
| 199 | #define MFI_MBOX_SIZE 12 |
| 200 | |
| 201 | enum MR_EVT_CLASS { |
| 202 | |
| 203 | MR_EVT_CLASS_DEBUG = -2, |
| 204 | MR_EVT_CLASS_PROGRESS = -1, |
| 205 | MR_EVT_CLASS_INFO = 0, |
| 206 | MR_EVT_CLASS_WARNING = 1, |
| 207 | MR_EVT_CLASS_CRITICAL = 2, |
| 208 | MR_EVT_CLASS_FATAL = 3, |
| 209 | MR_EVT_CLASS_DEAD = 4, |
| 210 | |
| 211 | }; |
| 212 | |
| 213 | enum MR_EVT_LOCALE { |
| 214 | |
| 215 | MR_EVT_LOCALE_LD = 0x0001, |
| 216 | MR_EVT_LOCALE_PD = 0x0002, |
| 217 | MR_EVT_LOCALE_ENCL = 0x0004, |
| 218 | MR_EVT_LOCALE_BBU = 0x0008, |
| 219 | MR_EVT_LOCALE_SAS = 0x0010, |
| 220 | MR_EVT_LOCALE_CTRL = 0x0020, |
| 221 | MR_EVT_LOCALE_CONFIG = 0x0040, |
| 222 | MR_EVT_LOCALE_CLUSTER = 0x0080, |
| 223 | MR_EVT_LOCALE_ALL = 0xffff, |
| 224 | |
| 225 | }; |
| 226 | |
| 227 | enum MR_EVT_ARGS { |
| 228 | |
| 229 | MR_EVT_ARGS_NONE, |
| 230 | MR_EVT_ARGS_CDB_SENSE, |
| 231 | MR_EVT_ARGS_LD, |
| 232 | MR_EVT_ARGS_LD_COUNT, |
| 233 | MR_EVT_ARGS_LD_LBA, |
| 234 | MR_EVT_ARGS_LD_OWNER, |
| 235 | MR_EVT_ARGS_LD_LBA_PD_LBA, |
| 236 | MR_EVT_ARGS_LD_PROG, |
| 237 | MR_EVT_ARGS_LD_STATE, |
| 238 | MR_EVT_ARGS_LD_STRIP, |
| 239 | MR_EVT_ARGS_PD, |
| 240 | MR_EVT_ARGS_PD_ERR, |
| 241 | MR_EVT_ARGS_PD_LBA, |
| 242 | MR_EVT_ARGS_PD_LBA_LD, |
| 243 | MR_EVT_ARGS_PD_PROG, |
| 244 | MR_EVT_ARGS_PD_STATE, |
| 245 | MR_EVT_ARGS_PCI, |
| 246 | MR_EVT_ARGS_RATE, |
| 247 | MR_EVT_ARGS_STR, |
| 248 | MR_EVT_ARGS_TIME, |
| 249 | MR_EVT_ARGS_ECC, |
| 250 | |
| 251 | }; |
| 252 | |
| 253 | /* |
| 254 | * SAS controller properties |
| 255 | */ |
| 256 | struct megasas_ctrl_prop { |
| 257 | |
| 258 | u16 seq_num; |
| 259 | u16 pred_fail_poll_interval; |
| 260 | u16 intr_throttle_count; |
| 261 | u16 intr_throttle_timeouts; |
| 262 | u8 rebuild_rate; |
| 263 | u8 patrol_read_rate; |
| 264 | u8 bgi_rate; |
| 265 | u8 cc_rate; |
| 266 | u8 recon_rate; |
| 267 | u8 cache_flush_interval; |
| 268 | u8 spinup_drv_count; |
| 269 | u8 spinup_delay; |
| 270 | u8 cluster_enable; |
| 271 | u8 coercion_mode; |
| 272 | u8 alarm_enable; |
| 273 | u8 disable_auto_rebuild; |
| 274 | u8 disable_battery_warn; |
| 275 | u8 ecc_bucket_size; |
| 276 | u16 ecc_bucket_leak_rate; |
| 277 | u8 restore_hotspare_on_insertion; |
| 278 | u8 expose_encl_devices; |
| 279 | u8 reserved[38]; |
| 280 | |
| 281 | } __attribute__ ((packed)); |
| 282 | |
| 283 | /* |
| 284 | * SAS controller information |
| 285 | */ |
| 286 | struct megasas_ctrl_info { |
| 287 | |
| 288 | /* |
| 289 | * PCI device information |
| 290 | */ |
| 291 | struct { |
| 292 | |
| 293 | u16 vendor_id; |
| 294 | u16 device_id; |
| 295 | u16 sub_vendor_id; |
| 296 | u16 sub_device_id; |
| 297 | u8 reserved[24]; |
| 298 | |
| 299 | } __attribute__ ((packed)) pci; |
| 300 | |
| 301 | /* |
| 302 | * Host interface information |
| 303 | */ |
| 304 | struct { |
| 305 | |
| 306 | u8 PCIX:1; |
| 307 | u8 PCIE:1; |
| 308 | u8 iSCSI:1; |
| 309 | u8 SAS_3G:1; |
| 310 | u8 reserved_0:4; |
| 311 | u8 reserved_1[6]; |
| 312 | u8 port_count; |
| 313 | u64 port_addr[8]; |
| 314 | |
| 315 | } __attribute__ ((packed)) host_interface; |
| 316 | |
| 317 | /* |
| 318 | * Device (backend) interface information |
| 319 | */ |
| 320 | struct { |
| 321 | |
| 322 | u8 SPI:1; |
| 323 | u8 SAS_3G:1; |
| 324 | u8 SATA_1_5G:1; |
| 325 | u8 SATA_3G:1; |
| 326 | u8 reserved_0:4; |
| 327 | u8 reserved_1[6]; |
| 328 | u8 port_count; |
| 329 | u64 port_addr[8]; |
| 330 | |
| 331 | } __attribute__ ((packed)) device_interface; |
| 332 | |
| 333 | /* |
| 334 | * List of components residing in flash. All str are null terminated |
| 335 | */ |
| 336 | u32 image_check_word; |
| 337 | u32 image_component_count; |
| 338 | |
| 339 | struct { |
| 340 | |
| 341 | char name[8]; |
| 342 | char version[32]; |
| 343 | char build_date[16]; |
| 344 | char built_time[16]; |
| 345 | |
| 346 | } __attribute__ ((packed)) image_component[8]; |
| 347 | |
| 348 | /* |
| 349 | * List of flash components that have been flashed on the card, but |
| 350 | * are not in use, pending reset of the adapter. This list will be |
| 351 | * empty if a flash operation has not occurred. All stings are null |
| 352 | * terminated |
| 353 | */ |
| 354 | u32 pending_image_component_count; |
| 355 | |
| 356 | struct { |
| 357 | |
| 358 | char name[8]; |
| 359 | char version[32]; |
| 360 | char build_date[16]; |
| 361 | char build_time[16]; |
| 362 | |
| 363 | } __attribute__ ((packed)) pending_image_component[8]; |
| 364 | |
| 365 | u8 max_arms; |
| 366 | u8 max_spans; |
| 367 | u8 max_arrays; |
| 368 | u8 max_lds; |
| 369 | |
| 370 | char product_name[80]; |
| 371 | char serial_no[32]; |
| 372 | |
| 373 | /* |
| 374 | * Other physical/controller/operation information. Indicates the |
| 375 | * presence of the hardware |
| 376 | */ |
| 377 | struct { |
| 378 | |
| 379 | u32 bbu:1; |
| 380 | u32 alarm:1; |
| 381 | u32 nvram:1; |
| 382 | u32 uart:1; |
| 383 | u32 reserved:28; |
| 384 | |
| 385 | } __attribute__ ((packed)) hw_present; |
| 386 | |
| 387 | u32 current_fw_time; |
| 388 | |
| 389 | /* |
| 390 | * Maximum data transfer sizes |
| 391 | */ |
| 392 | u16 max_concurrent_cmds; |
| 393 | u16 max_sge_count; |
| 394 | u32 max_request_size; |
| 395 | |
| 396 | /* |
| 397 | * Logical and physical device counts |
| 398 | */ |
| 399 | u16 ld_present_count; |
| 400 | u16 ld_degraded_count; |
| 401 | u16 ld_offline_count; |
| 402 | |
| 403 | u16 pd_present_count; |
| 404 | u16 pd_disk_present_count; |
| 405 | u16 pd_disk_pred_failure_count; |
| 406 | u16 pd_disk_failed_count; |
| 407 | |
| 408 | /* |
| 409 | * Memory size information |
| 410 | */ |
| 411 | u16 nvram_size; |
| 412 | u16 memory_size; |
| 413 | u16 flash_size; |
| 414 | |
| 415 | /* |
| 416 | * Error counters |
| 417 | */ |
| 418 | u16 mem_correctable_error_count; |
| 419 | u16 mem_uncorrectable_error_count; |
| 420 | |
| 421 | /* |
| 422 | * Cluster information |
| 423 | */ |
| 424 | u8 cluster_permitted; |
| 425 | u8 cluster_active; |
| 426 | |
| 427 | /* |
| 428 | * Additional max data transfer sizes |
| 429 | */ |
| 430 | u16 max_strips_per_io; |
| 431 | |
| 432 | /* |
| 433 | * Controller capabilities structures |
| 434 | */ |
| 435 | struct { |
| 436 | |
| 437 | u32 raid_level_0:1; |
| 438 | u32 raid_level_1:1; |
| 439 | u32 raid_level_5:1; |
| 440 | u32 raid_level_1E:1; |
| 441 | u32 raid_level_6:1; |
| 442 | u32 reserved:27; |
| 443 | |
| 444 | } __attribute__ ((packed)) raid_levels; |
| 445 | |
| 446 | struct { |
| 447 | |
| 448 | u32 rbld_rate:1; |
| 449 | u32 cc_rate:1; |
| 450 | u32 bgi_rate:1; |
| 451 | u32 recon_rate:1; |
| 452 | u32 patrol_rate:1; |
| 453 | u32 alarm_control:1; |
| 454 | u32 cluster_supported:1; |
| 455 | u32 bbu:1; |
| 456 | u32 spanning_allowed:1; |
| 457 | u32 dedicated_hotspares:1; |
| 458 | u32 revertible_hotspares:1; |
| 459 | u32 foreign_config_import:1; |
| 460 | u32 self_diagnostic:1; |
| 461 | u32 mixed_redundancy_arr:1; |
| 462 | u32 global_hot_spares:1; |
| 463 | u32 reserved:17; |
| 464 | |
| 465 | } __attribute__ ((packed)) adapter_operations; |
| 466 | |
| 467 | struct { |
| 468 | |
| 469 | u32 read_policy:1; |
| 470 | u32 write_policy:1; |
| 471 | u32 io_policy:1; |
| 472 | u32 access_policy:1; |
| 473 | u32 disk_cache_policy:1; |
| 474 | u32 reserved:27; |
| 475 | |
| 476 | } __attribute__ ((packed)) ld_operations; |
| 477 | |
| 478 | struct { |
| 479 | |
| 480 | u8 min; |
| 481 | u8 max; |
| 482 | u8 reserved[2]; |
| 483 | |
| 484 | } __attribute__ ((packed)) stripe_sz_ops; |
| 485 | |
| 486 | struct { |
| 487 | |
| 488 | u32 force_online:1; |
| 489 | u32 force_offline:1; |
| 490 | u32 force_rebuild:1; |
| 491 | u32 reserved:29; |
| 492 | |
| 493 | } __attribute__ ((packed)) pd_operations; |
| 494 | |
| 495 | struct { |
| 496 | |
| 497 | u32 ctrl_supports_sas:1; |
| 498 | u32 ctrl_supports_sata:1; |
| 499 | u32 allow_mix_in_encl:1; |
| 500 | u32 allow_mix_in_ld:1; |
| 501 | u32 allow_sata_in_cluster:1; |
| 502 | u32 reserved:27; |
| 503 | |
| 504 | } __attribute__ ((packed)) pd_mix_support; |
| 505 | |
| 506 | /* |
| 507 | * Define ECC single-bit-error bucket information |
| 508 | */ |
| 509 | u8 ecc_bucket_count; |
| 510 | u8 reserved_2[11]; |
| 511 | |
| 512 | /* |
| 513 | * Include the controller properties (changeable items) |
| 514 | */ |
| 515 | struct megasas_ctrl_prop properties; |
| 516 | |
| 517 | /* |
| 518 | * Define FW pkg version (set in envt v'bles on OEM basis) |
| 519 | */ |
| 520 | char package_version[0x60]; |
| 521 | |
| 522 | u8 pad[0x800 - 0x6a0]; |
| 523 | |
| 524 | } __attribute__ ((packed)); |
| 525 | |
| 526 | /* |
| 527 | * =============================== |
| 528 | * MegaRAID SAS driver definitions |
| 529 | * =============================== |
| 530 | */ |
| 531 | #define MEGASAS_MAX_PD_CHANNELS 2 |
| 532 | #define MEGASAS_MAX_LD_CHANNELS 2 |
| 533 | #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ |
| 534 | MEGASAS_MAX_LD_CHANNELS) |
| 535 | #define MEGASAS_MAX_DEV_PER_CHANNEL 128 |
| 536 | #define MEGASAS_DEFAULT_INIT_ID -1 |
| 537 | #define MEGASAS_MAX_LUN 8 |
| 538 | #define MEGASAS_MAX_LD 64 |
| 539 | |
Sumant Patro | 658dced | 2006-10-03 13:09:14 -0700 | [diff] [blame] | 540 | #define MEGASAS_DBG_LVL 1 |
| 541 | |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 542 | /* |
| 543 | * When SCSI mid-layer calls driver's reset routine, driver waits for |
| 544 | * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note |
| 545 | * that the driver cannot _actually_ abort or reset pending commands. While |
| 546 | * it is waiting for the commands to complete, it prints a diagnostic message |
| 547 | * every MEGASAS_RESET_NOTICE_INTERVAL seconds |
| 548 | */ |
| 549 | #define MEGASAS_RESET_WAIT_TIME 180 |
| 550 | #define MEGASAS_RESET_NOTICE_INTERVAL 5 |
| 551 | |
| 552 | #define MEGASAS_IOCTL_CMD 0 |
| 553 | |
| 554 | /* |
| 555 | * FW reports the maximum of number of commands that it can accept (maximum |
| 556 | * commands that can be outstanding) at any time. The driver must report a |
| 557 | * lower number to the mid layer because it can issue a few internal commands |
| 558 | * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs |
| 559 | * is shown below |
| 560 | */ |
| 561 | #define MEGASAS_INT_CMDS 32 |
| 562 | |
| 563 | /* |
| 564 | * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit |
| 565 | * SGLs based on the size of dma_addr_t |
| 566 | */ |
| 567 | #define IS_DMA64 (sizeof(dma_addr_t) == 8) |
| 568 | |
| 569 | #define MFI_OB_INTR_STATUS_MASK 0x00000002 |
| 570 | #define MFI_POLL_TIMEOUT_SECS 10 |
| 571 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 572 | #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 |
Sumant Patro | 0e98936 | 2006-06-20 15:32:37 -0700 | [diff] [blame] | 573 | |
| 574 | /* |
| 575 | * register set for both 1068 and 1078 controllers |
| 576 | * structure extended for 1078 registers |
| 577 | */ |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 578 | |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 579 | struct megasas_register_set { |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 580 | u32 reserved_0[4]; /*0000h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 581 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 582 | u32 inbound_msg_0; /*0010h*/ |
| 583 | u32 inbound_msg_1; /*0014h*/ |
| 584 | u32 outbound_msg_0; /*0018h*/ |
| 585 | u32 outbound_msg_1; /*001Ch*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 586 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 587 | u32 inbound_doorbell; /*0020h*/ |
| 588 | u32 inbound_intr_status; /*0024h*/ |
| 589 | u32 inbound_intr_mask; /*0028h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 590 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 591 | u32 outbound_doorbell; /*002Ch*/ |
| 592 | u32 outbound_intr_status; /*0030h*/ |
| 593 | u32 outbound_intr_mask; /*0034h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 594 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 595 | u32 reserved_1[2]; /*0038h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 596 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 597 | u32 inbound_queue_port; /*0040h*/ |
| 598 | u32 outbound_queue_port; /*0044h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 599 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 600 | u32 reserved_2[22]; /*0048h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 601 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 602 | u32 outbound_doorbell_clear; /*00A0h*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 603 | |
Sumant Patro | f9876f0 | 2006-02-03 15:34:35 -0800 | [diff] [blame] | 604 | u32 reserved_3[3]; /*00A4h*/ |
| 605 | |
| 606 | u32 outbound_scratch_pad ; /*00B0h*/ |
| 607 | |
| 608 | u32 reserved_4[3]; /*00B4h*/ |
| 609 | |
| 610 | u32 inbound_low_queue_port ; /*00C0h*/ |
| 611 | |
| 612 | u32 inbound_high_queue_port ; /*00C4h*/ |
| 613 | |
| 614 | u32 reserved_5; /*00C8h*/ |
| 615 | u32 index_registers[820]; /*00CCh*/ |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 616 | |
| 617 | } __attribute__ ((packed)); |
| 618 | |
| 619 | struct megasas_sge32 { |
| 620 | |
| 621 | u32 phys_addr; |
| 622 | u32 length; |
| 623 | |
| 624 | } __attribute__ ((packed)); |
| 625 | |
| 626 | struct megasas_sge64 { |
| 627 | |
| 628 | u64 phys_addr; |
| 629 | u32 length; |
| 630 | |
| 631 | } __attribute__ ((packed)); |
| 632 | |
| 633 | union megasas_sgl { |
| 634 | |
| 635 | struct megasas_sge32 sge32[1]; |
| 636 | struct megasas_sge64 sge64[1]; |
| 637 | |
| 638 | } __attribute__ ((packed)); |
| 639 | |
| 640 | struct megasas_header { |
| 641 | |
| 642 | u8 cmd; /*00h */ |
| 643 | u8 sense_len; /*01h */ |
| 644 | u8 cmd_status; /*02h */ |
| 645 | u8 scsi_status; /*03h */ |
| 646 | |
| 647 | u8 target_id; /*04h */ |
| 648 | u8 lun; /*05h */ |
| 649 | u8 cdb_len; /*06h */ |
| 650 | u8 sge_count; /*07h */ |
| 651 | |
| 652 | u32 context; /*08h */ |
| 653 | u32 pad_0; /*0Ch */ |
| 654 | |
| 655 | u16 flags; /*10h */ |
| 656 | u16 timeout; /*12h */ |
| 657 | u32 data_xferlen; /*14h */ |
| 658 | |
| 659 | } __attribute__ ((packed)); |
| 660 | |
| 661 | union megasas_sgl_frame { |
| 662 | |
| 663 | struct megasas_sge32 sge32[8]; |
| 664 | struct megasas_sge64 sge64[5]; |
| 665 | |
| 666 | } __attribute__ ((packed)); |
| 667 | |
| 668 | struct megasas_init_frame { |
| 669 | |
| 670 | u8 cmd; /*00h */ |
| 671 | u8 reserved_0; /*01h */ |
| 672 | u8 cmd_status; /*02h */ |
| 673 | |
| 674 | u8 reserved_1; /*03h */ |
| 675 | u32 reserved_2; /*04h */ |
| 676 | |
| 677 | u32 context; /*08h */ |
| 678 | u32 pad_0; /*0Ch */ |
| 679 | |
| 680 | u16 flags; /*10h */ |
| 681 | u16 reserved_3; /*12h */ |
| 682 | u32 data_xfer_len; /*14h */ |
| 683 | |
| 684 | u32 queue_info_new_phys_addr_lo; /*18h */ |
| 685 | u32 queue_info_new_phys_addr_hi; /*1Ch */ |
| 686 | u32 queue_info_old_phys_addr_lo; /*20h */ |
| 687 | u32 queue_info_old_phys_addr_hi; /*24h */ |
| 688 | |
| 689 | u32 reserved_4[6]; /*28h */ |
| 690 | |
| 691 | } __attribute__ ((packed)); |
| 692 | |
| 693 | struct megasas_init_queue_info { |
| 694 | |
| 695 | u32 init_flags; /*00h */ |
| 696 | u32 reply_queue_entries; /*04h */ |
| 697 | |
| 698 | u32 reply_queue_start_phys_addr_lo; /*08h */ |
| 699 | u32 reply_queue_start_phys_addr_hi; /*0Ch */ |
| 700 | u32 producer_index_phys_addr_lo; /*10h */ |
| 701 | u32 producer_index_phys_addr_hi; /*14h */ |
| 702 | u32 consumer_index_phys_addr_lo; /*18h */ |
| 703 | u32 consumer_index_phys_addr_hi; /*1Ch */ |
| 704 | |
| 705 | } __attribute__ ((packed)); |
| 706 | |
| 707 | struct megasas_io_frame { |
| 708 | |
| 709 | u8 cmd; /*00h */ |
| 710 | u8 sense_len; /*01h */ |
| 711 | u8 cmd_status; /*02h */ |
| 712 | u8 scsi_status; /*03h */ |
| 713 | |
| 714 | u8 target_id; /*04h */ |
| 715 | u8 access_byte; /*05h */ |
| 716 | u8 reserved_0; /*06h */ |
| 717 | u8 sge_count; /*07h */ |
| 718 | |
| 719 | u32 context; /*08h */ |
| 720 | u32 pad_0; /*0Ch */ |
| 721 | |
| 722 | u16 flags; /*10h */ |
| 723 | u16 timeout; /*12h */ |
| 724 | u32 lba_count; /*14h */ |
| 725 | |
| 726 | u32 sense_buf_phys_addr_lo; /*18h */ |
| 727 | u32 sense_buf_phys_addr_hi; /*1Ch */ |
| 728 | |
| 729 | u32 start_lba_lo; /*20h */ |
| 730 | u32 start_lba_hi; /*24h */ |
| 731 | |
| 732 | union megasas_sgl sgl; /*28h */ |
| 733 | |
| 734 | } __attribute__ ((packed)); |
| 735 | |
| 736 | struct megasas_pthru_frame { |
| 737 | |
| 738 | u8 cmd; /*00h */ |
| 739 | u8 sense_len; /*01h */ |
| 740 | u8 cmd_status; /*02h */ |
| 741 | u8 scsi_status; /*03h */ |
| 742 | |
| 743 | u8 target_id; /*04h */ |
| 744 | u8 lun; /*05h */ |
| 745 | u8 cdb_len; /*06h */ |
| 746 | u8 sge_count; /*07h */ |
| 747 | |
| 748 | u32 context; /*08h */ |
| 749 | u32 pad_0; /*0Ch */ |
| 750 | |
| 751 | u16 flags; /*10h */ |
| 752 | u16 timeout; /*12h */ |
| 753 | u32 data_xfer_len; /*14h */ |
| 754 | |
| 755 | u32 sense_buf_phys_addr_lo; /*18h */ |
| 756 | u32 sense_buf_phys_addr_hi; /*1Ch */ |
| 757 | |
| 758 | u8 cdb[16]; /*20h */ |
| 759 | union megasas_sgl sgl; /*30h */ |
| 760 | |
| 761 | } __attribute__ ((packed)); |
| 762 | |
| 763 | struct megasas_dcmd_frame { |
| 764 | |
| 765 | u8 cmd; /*00h */ |
| 766 | u8 reserved_0; /*01h */ |
| 767 | u8 cmd_status; /*02h */ |
| 768 | u8 reserved_1[4]; /*03h */ |
| 769 | u8 sge_count; /*07h */ |
| 770 | |
| 771 | u32 context; /*08h */ |
| 772 | u32 pad_0; /*0Ch */ |
| 773 | |
| 774 | u16 flags; /*10h */ |
| 775 | u16 timeout; /*12h */ |
| 776 | |
| 777 | u32 data_xfer_len; /*14h */ |
| 778 | u32 opcode; /*18h */ |
| 779 | |
| 780 | union { /*1Ch */ |
| 781 | u8 b[12]; |
| 782 | u16 s[6]; |
| 783 | u32 w[3]; |
| 784 | } mbox; |
| 785 | |
| 786 | union megasas_sgl sgl; /*28h */ |
| 787 | |
| 788 | } __attribute__ ((packed)); |
| 789 | |
| 790 | struct megasas_abort_frame { |
| 791 | |
| 792 | u8 cmd; /*00h */ |
| 793 | u8 reserved_0; /*01h */ |
| 794 | u8 cmd_status; /*02h */ |
| 795 | |
| 796 | u8 reserved_1; /*03h */ |
| 797 | u32 reserved_2; /*04h */ |
| 798 | |
| 799 | u32 context; /*08h */ |
| 800 | u32 pad_0; /*0Ch */ |
| 801 | |
| 802 | u16 flags; /*10h */ |
| 803 | u16 reserved_3; /*12h */ |
| 804 | u32 reserved_4; /*14h */ |
| 805 | |
| 806 | u32 abort_context; /*18h */ |
| 807 | u32 pad_1; /*1Ch */ |
| 808 | |
| 809 | u32 abort_mfi_phys_addr_lo; /*20h */ |
| 810 | u32 abort_mfi_phys_addr_hi; /*24h */ |
| 811 | |
| 812 | u32 reserved_5[6]; /*28h */ |
| 813 | |
| 814 | } __attribute__ ((packed)); |
| 815 | |
| 816 | struct megasas_smp_frame { |
| 817 | |
| 818 | u8 cmd; /*00h */ |
| 819 | u8 reserved_1; /*01h */ |
| 820 | u8 cmd_status; /*02h */ |
| 821 | u8 connection_status; /*03h */ |
| 822 | |
| 823 | u8 reserved_2[3]; /*04h */ |
| 824 | u8 sge_count; /*07h */ |
| 825 | |
| 826 | u32 context; /*08h */ |
| 827 | u32 pad_0; /*0Ch */ |
| 828 | |
| 829 | u16 flags; /*10h */ |
| 830 | u16 timeout; /*12h */ |
| 831 | |
| 832 | u32 data_xfer_len; /*14h */ |
| 833 | u64 sas_addr; /*18h */ |
| 834 | |
| 835 | union { |
| 836 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ |
| 837 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ |
| 838 | } sgl; |
| 839 | |
| 840 | } __attribute__ ((packed)); |
| 841 | |
| 842 | struct megasas_stp_frame { |
| 843 | |
| 844 | u8 cmd; /*00h */ |
| 845 | u8 reserved_1; /*01h */ |
| 846 | u8 cmd_status; /*02h */ |
| 847 | u8 reserved_2; /*03h */ |
| 848 | |
| 849 | u8 target_id; /*04h */ |
| 850 | u8 reserved_3[2]; /*05h */ |
| 851 | u8 sge_count; /*07h */ |
| 852 | |
| 853 | u32 context; /*08h */ |
| 854 | u32 pad_0; /*0Ch */ |
| 855 | |
| 856 | u16 flags; /*10h */ |
| 857 | u16 timeout; /*12h */ |
| 858 | |
| 859 | u32 data_xfer_len; /*14h */ |
| 860 | |
| 861 | u16 fis[10]; /*18h */ |
| 862 | u32 stp_flags; |
| 863 | |
| 864 | union { |
| 865 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ |
| 866 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ |
| 867 | } sgl; |
| 868 | |
| 869 | } __attribute__ ((packed)); |
| 870 | |
| 871 | union megasas_frame { |
| 872 | |
| 873 | struct megasas_header hdr; |
| 874 | struct megasas_init_frame init; |
| 875 | struct megasas_io_frame io; |
| 876 | struct megasas_pthru_frame pthru; |
| 877 | struct megasas_dcmd_frame dcmd; |
| 878 | struct megasas_abort_frame abort; |
| 879 | struct megasas_smp_frame smp; |
| 880 | struct megasas_stp_frame stp; |
| 881 | |
| 882 | u8 raw_bytes[64]; |
| 883 | }; |
| 884 | |
| 885 | struct megasas_cmd; |
| 886 | |
| 887 | union megasas_evt_class_locale { |
| 888 | |
| 889 | struct { |
| 890 | u16 locale; |
| 891 | u8 reserved; |
| 892 | s8 class; |
| 893 | } __attribute__ ((packed)) members; |
| 894 | |
| 895 | u32 word; |
| 896 | |
| 897 | } __attribute__ ((packed)); |
| 898 | |
| 899 | struct megasas_evt_log_info { |
| 900 | u32 newest_seq_num; |
| 901 | u32 oldest_seq_num; |
| 902 | u32 clear_seq_num; |
| 903 | u32 shutdown_seq_num; |
| 904 | u32 boot_seq_num; |
| 905 | |
| 906 | } __attribute__ ((packed)); |
| 907 | |
| 908 | struct megasas_progress { |
| 909 | |
| 910 | u16 progress; |
| 911 | u16 elapsed_seconds; |
| 912 | |
| 913 | } __attribute__ ((packed)); |
| 914 | |
| 915 | struct megasas_evtarg_ld { |
| 916 | |
| 917 | u16 target_id; |
| 918 | u8 ld_index; |
| 919 | u8 reserved; |
| 920 | |
| 921 | } __attribute__ ((packed)); |
| 922 | |
| 923 | struct megasas_evtarg_pd { |
| 924 | u16 device_id; |
| 925 | u8 encl_index; |
| 926 | u8 slot_number; |
| 927 | |
| 928 | } __attribute__ ((packed)); |
| 929 | |
| 930 | struct megasas_evt_detail { |
| 931 | |
| 932 | u32 seq_num; |
| 933 | u32 time_stamp; |
| 934 | u32 code; |
| 935 | union megasas_evt_class_locale cl; |
| 936 | u8 arg_type; |
| 937 | u8 reserved1[15]; |
| 938 | |
| 939 | union { |
| 940 | struct { |
| 941 | struct megasas_evtarg_pd pd; |
| 942 | u8 cdb_length; |
| 943 | u8 sense_length; |
| 944 | u8 reserved[2]; |
| 945 | u8 cdb[16]; |
| 946 | u8 sense[64]; |
| 947 | } __attribute__ ((packed)) cdbSense; |
| 948 | |
| 949 | struct megasas_evtarg_ld ld; |
| 950 | |
| 951 | struct { |
| 952 | struct megasas_evtarg_ld ld; |
| 953 | u64 count; |
| 954 | } __attribute__ ((packed)) ld_count; |
| 955 | |
| 956 | struct { |
| 957 | u64 lba; |
| 958 | struct megasas_evtarg_ld ld; |
| 959 | } __attribute__ ((packed)) ld_lba; |
| 960 | |
| 961 | struct { |
| 962 | struct megasas_evtarg_ld ld; |
| 963 | u32 prevOwner; |
| 964 | u32 newOwner; |
| 965 | } __attribute__ ((packed)) ld_owner; |
| 966 | |
| 967 | struct { |
| 968 | u64 ld_lba; |
| 969 | u64 pd_lba; |
| 970 | struct megasas_evtarg_ld ld; |
| 971 | struct megasas_evtarg_pd pd; |
| 972 | } __attribute__ ((packed)) ld_lba_pd_lba; |
| 973 | |
| 974 | struct { |
| 975 | struct megasas_evtarg_ld ld; |
| 976 | struct megasas_progress prog; |
| 977 | } __attribute__ ((packed)) ld_prog; |
| 978 | |
| 979 | struct { |
| 980 | struct megasas_evtarg_ld ld; |
| 981 | u32 prev_state; |
| 982 | u32 new_state; |
| 983 | } __attribute__ ((packed)) ld_state; |
| 984 | |
| 985 | struct { |
| 986 | u64 strip; |
| 987 | struct megasas_evtarg_ld ld; |
| 988 | } __attribute__ ((packed)) ld_strip; |
| 989 | |
| 990 | struct megasas_evtarg_pd pd; |
| 991 | |
| 992 | struct { |
| 993 | struct megasas_evtarg_pd pd; |
| 994 | u32 err; |
| 995 | } __attribute__ ((packed)) pd_err; |
| 996 | |
| 997 | struct { |
| 998 | u64 lba; |
| 999 | struct megasas_evtarg_pd pd; |
| 1000 | } __attribute__ ((packed)) pd_lba; |
| 1001 | |
| 1002 | struct { |
| 1003 | u64 lba; |
| 1004 | struct megasas_evtarg_pd pd; |
| 1005 | struct megasas_evtarg_ld ld; |
| 1006 | } __attribute__ ((packed)) pd_lba_ld; |
| 1007 | |
| 1008 | struct { |
| 1009 | struct megasas_evtarg_pd pd; |
| 1010 | struct megasas_progress prog; |
| 1011 | } __attribute__ ((packed)) pd_prog; |
| 1012 | |
| 1013 | struct { |
| 1014 | struct megasas_evtarg_pd pd; |
| 1015 | u32 prevState; |
| 1016 | u32 newState; |
| 1017 | } __attribute__ ((packed)) pd_state; |
| 1018 | |
| 1019 | struct { |
| 1020 | u16 vendorId; |
| 1021 | u16 deviceId; |
| 1022 | u16 subVendorId; |
| 1023 | u16 subDeviceId; |
| 1024 | } __attribute__ ((packed)) pci; |
| 1025 | |
| 1026 | u32 rate; |
| 1027 | char str[96]; |
| 1028 | |
| 1029 | struct { |
| 1030 | u32 rtc; |
| 1031 | u32 elapsedSeconds; |
| 1032 | } __attribute__ ((packed)) time; |
| 1033 | |
| 1034 | struct { |
| 1035 | u32 ecar; |
| 1036 | u32 elog; |
| 1037 | char str[64]; |
| 1038 | } __attribute__ ((packed)) ecc; |
| 1039 | |
| 1040 | u8 b[96]; |
| 1041 | u16 s[48]; |
| 1042 | u32 w[24]; |
| 1043 | u64 d[12]; |
| 1044 | } args; |
| 1045 | |
| 1046 | char description[128]; |
| 1047 | |
| 1048 | } __attribute__ ((packed)); |
| 1049 | |
Sumant Patro | 1341c93 | 2006-01-25 12:02:40 -0800 | [diff] [blame] | 1050 | struct megasas_instance_template { |
| 1051 | void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *); |
| 1052 | |
| 1053 | void (*enable_intr)(struct megasas_register_set __iomem *) ; |
Sumant Patro | b274cab | 2006-10-03 12:52:12 -0700 | [diff] [blame] | 1054 | void (*disable_intr)(struct megasas_register_set __iomem *); |
Sumant Patro | 1341c93 | 2006-01-25 12:02:40 -0800 | [diff] [blame] | 1055 | |
| 1056 | int (*clear_intr)(struct megasas_register_set __iomem *); |
| 1057 | |
| 1058 | u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); |
| 1059 | }; |
| 1060 | |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1061 | struct megasas_instance { |
| 1062 | |
| 1063 | u32 *producer; |
| 1064 | dma_addr_t producer_h; |
| 1065 | u32 *consumer; |
| 1066 | dma_addr_t consumer_h; |
| 1067 | |
| 1068 | u32 *reply_queue; |
| 1069 | dma_addr_t reply_queue_h; |
| 1070 | |
| 1071 | unsigned long base_addr; |
| 1072 | struct megasas_register_set __iomem *reg_set; |
| 1073 | |
| 1074 | s8 init_id; |
| 1075 | u8 reserved[3]; |
| 1076 | |
| 1077 | u16 max_num_sge; |
| 1078 | u16 max_fw_cmds; |
| 1079 | u32 max_sectors_per_req; |
| 1080 | |
| 1081 | struct megasas_cmd **cmd_list; |
| 1082 | struct list_head cmd_pool; |
| 1083 | spinlock_t cmd_pool_lock; |
| 1084 | struct dma_pool *frame_dma_pool; |
| 1085 | struct dma_pool *sense_dma_pool; |
| 1086 | |
| 1087 | struct megasas_evt_detail *evt_detail; |
| 1088 | dma_addr_t evt_detail_h; |
| 1089 | struct megasas_cmd *aen_cmd; |
| 1090 | struct semaphore aen_mutex; |
| 1091 | struct semaphore ioctl_sem; |
| 1092 | |
| 1093 | struct Scsi_Host *host; |
| 1094 | |
| 1095 | wait_queue_head_t int_cmd_wait_q; |
| 1096 | wait_queue_head_t abort_cmd_wait_q; |
| 1097 | |
| 1098 | struct pci_dev *pdev; |
| 1099 | u32 unique_id; |
| 1100 | |
Sumant Patro | e4a082c | 2006-05-30 12:03:37 -0700 | [diff] [blame] | 1101 | atomic_t fw_outstanding; |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1102 | u32 hw_crit_error; |
Sumant Patro | 1341c93 | 2006-01-25 12:02:40 -0800 | [diff] [blame] | 1103 | |
| 1104 | struct megasas_instance_template *instancet; |
Sumant Patro | 5d018ad | 2006-10-03 13:13:18 -0700 | [diff] [blame^] | 1105 | struct tasklet_struct isr_tasklet; |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1106 | }; |
| 1107 | |
| 1108 | #define MEGASAS_IS_LOGICAL(scp) \ |
| 1109 | (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 |
| 1110 | |
| 1111 | #define MEGASAS_DEV_INDEX(inst, scp) \ |
| 1112 | ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ |
| 1113 | scp->device->id |
| 1114 | |
| 1115 | struct megasas_cmd { |
| 1116 | |
| 1117 | union megasas_frame *frame; |
| 1118 | dma_addr_t frame_phys_addr; |
| 1119 | u8 *sense; |
| 1120 | dma_addr_t sense_phys_addr; |
| 1121 | |
| 1122 | u32 index; |
| 1123 | u8 sync_cmd; |
| 1124 | u8 cmd_status; |
| 1125 | u16 abort_aen; |
| 1126 | |
| 1127 | struct list_head list; |
| 1128 | struct scsi_cmnd *scmd; |
| 1129 | struct megasas_instance *instance; |
| 1130 | u32 frame_count; |
| 1131 | }; |
| 1132 | |
| 1133 | #define MAX_MGMT_ADAPTERS 1024 |
| 1134 | #define MAX_IOCTL_SGE 16 |
| 1135 | |
| 1136 | struct megasas_iocpacket { |
| 1137 | |
| 1138 | u16 host_no; |
| 1139 | u16 __pad1; |
| 1140 | u32 sgl_off; |
| 1141 | u32 sge_count; |
| 1142 | u32 sense_off; |
| 1143 | u32 sense_len; |
| 1144 | union { |
| 1145 | u8 raw[128]; |
| 1146 | struct megasas_header hdr; |
| 1147 | } frame; |
| 1148 | |
| 1149 | struct iovec sgl[MAX_IOCTL_SGE]; |
| 1150 | |
| 1151 | } __attribute__ ((packed)); |
| 1152 | |
| 1153 | struct megasas_aen { |
| 1154 | u16 host_no; |
| 1155 | u16 __pad1; |
| 1156 | u32 seq_num; |
| 1157 | u32 class_locale_word; |
| 1158 | } __attribute__ ((packed)); |
| 1159 | |
| 1160 | #ifdef CONFIG_COMPAT |
| 1161 | struct compat_megasas_iocpacket { |
| 1162 | u16 host_no; |
| 1163 | u16 __pad1; |
| 1164 | u32 sgl_off; |
| 1165 | u32 sge_count; |
| 1166 | u32 sense_off; |
| 1167 | u32 sense_len; |
| 1168 | union { |
| 1169 | u8 raw[128]; |
| 1170 | struct megasas_header hdr; |
| 1171 | } frame; |
| 1172 | struct compat_iovec sgl[MAX_IOCTL_SGE]; |
| 1173 | } __attribute__ ((packed)); |
| 1174 | |
Sumant Patro | 0e98936 | 2006-06-20 15:32:37 -0700 | [diff] [blame] | 1175 | #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1176 | #endif |
| 1177 | |
Sumant Patro | cb59aa6 | 2006-01-25 11:53:25 -0800 | [diff] [blame] | 1178 | #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) |
Bagalkote, Sreenivas | c4a3e0a | 2005-09-20 17:46:58 -0400 | [diff] [blame] | 1179 | #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) |
| 1180 | |
| 1181 | struct megasas_mgmt_info { |
| 1182 | |
| 1183 | u16 count; |
| 1184 | struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; |
| 1185 | int max_index; |
| 1186 | }; |
| 1187 | |
| 1188 | #endif /*LSI_MEGARAID_SAS_H */ |