Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 37 | /* |
| 38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 39 | * over cache flushing. |
| 40 | */ |
| 41 | struct pipe_control { |
| 42 | struct drm_i915_gem_object *obj; |
| 43 | volatile u32 *cpu_page; |
| 44 | u32 gtt_offset; |
| 45 | }; |
| 46 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 47 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 48 | { |
| 49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
| 50 | if (space < 0) |
| 51 | space += ring->size; |
| 52 | return space; |
| 53 | } |
| 54 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 55 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
| 56 | { |
| 57 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 58 | u32 seqno; |
| 59 | |
| 60 | seqno = dev_priv->next_seqno; |
| 61 | |
| 62 | /* reserve 0 for non-seqno */ |
| 63 | if (++dev_priv->next_seqno == 0) |
| 64 | dev_priv->next_seqno = 1; |
| 65 | |
| 66 | return seqno; |
| 67 | } |
| 68 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 69 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 70 | render_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 71 | u32 invalidate_domains, |
| 72 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 73 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 74 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 75 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 76 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 77 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 78 | /* |
| 79 | * read/write caches: |
| 80 | * |
| 81 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 82 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 83 | * also flushed at 2d versus 3d pipeline switches. |
| 84 | * |
| 85 | * read-only caches: |
| 86 | * |
| 87 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 88 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 89 | * |
| 90 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 91 | * |
| 92 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 93 | * invalidated when MI_EXE_FLUSH is set. |
| 94 | * |
| 95 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 96 | * invalidated with every MI_FLUSH. |
| 97 | * |
| 98 | * TLBs: |
| 99 | * |
| 100 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 101 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 102 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 103 | * are flushed at any MI_FLUSH. |
| 104 | */ |
| 105 | |
| 106 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 107 | if ((invalidate_domains|flush_domains) & |
| 108 | I915_GEM_DOMAIN_RENDER) |
| 109 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 110 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 111 | /* |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 112 | * On the 965, the sampler cache always gets flushed |
| 113 | * and this bit is reserved. |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 114 | */ |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 115 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 116 | cmd |= MI_READ_FLUSH; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 117 | } |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 118 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 119 | cmd |= MI_EXE_FLUSH; |
| 120 | |
| 121 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 122 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 123 | cmd |= MI_INVALIDATE_ISP; |
| 124 | |
| 125 | ret = intel_ring_begin(ring, 2); |
| 126 | if (ret) |
| 127 | return ret; |
| 128 | |
| 129 | intel_ring_emit(ring, cmd); |
| 130 | intel_ring_emit(ring, MI_NOOP); |
| 131 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 132 | |
| 133 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 134 | } |
| 135 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 136 | /** |
| 137 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 138 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 139 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 140 | * |
| 141 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 142 | * produced by non-pipelined state commands), software needs to first |
| 143 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 144 | * 0. |
| 145 | * |
| 146 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 147 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 148 | * |
| 149 | * And the workaround for these two requires this workaround first: |
| 150 | * |
| 151 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 152 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 153 | * flushes. |
| 154 | * |
| 155 | * And this last workaround is tricky because of the requirements on |
| 156 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 157 | * volume 2 part 1: |
| 158 | * |
| 159 | * "1 of the following must also be set: |
| 160 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 161 | * - Depth Cache Flush Enable ([0] of DW1) |
| 162 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 163 | * - Depth Stall ([13] of DW1) |
| 164 | * - Post-Sync Operation ([13] of DW1) |
| 165 | * - Notify Enable ([8] of DW1)" |
| 166 | * |
| 167 | * The cache flushes require the workaround flush that triggered this |
| 168 | * one, so we can't use it. Depth stall would trigger the same. |
| 169 | * Post-sync nonzero is what triggered this second workaround, so we |
| 170 | * can't use that one either. Notify enable is IRQs, which aren't |
| 171 | * really our business. That leaves only stall at scoreboard. |
| 172 | */ |
| 173 | static int |
| 174 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 175 | { |
| 176 | struct pipe_control *pc = ring->private; |
| 177 | u32 scratch_addr = pc->gtt_offset + 128; |
| 178 | int ret; |
| 179 | |
| 180 | |
| 181 | ret = intel_ring_begin(ring, 6); |
| 182 | if (ret) |
| 183 | return ret; |
| 184 | |
| 185 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 186 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 187 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 188 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 189 | intel_ring_emit(ring, 0); /* low dword */ |
| 190 | intel_ring_emit(ring, 0); /* high dword */ |
| 191 | intel_ring_emit(ring, MI_NOOP); |
| 192 | intel_ring_advance(ring); |
| 193 | |
| 194 | ret = intel_ring_begin(ring, 6); |
| 195 | if (ret) |
| 196 | return ret; |
| 197 | |
| 198 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 199 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 200 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 201 | intel_ring_emit(ring, 0); |
| 202 | intel_ring_emit(ring, 0); |
| 203 | intel_ring_emit(ring, MI_NOOP); |
| 204 | intel_ring_advance(ring); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static int |
| 210 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 211 | u32 invalidate_domains, u32 flush_domains) |
| 212 | { |
| 213 | u32 flags = 0; |
| 214 | struct pipe_control *pc = ring->private; |
| 215 | u32 scratch_addr = pc->gtt_offset + 128; |
| 216 | int ret; |
| 217 | |
| 218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 219 | intel_emit_post_sync_nonzero_flush(ring); |
| 220 | |
| 221 | /* Just flush everything. Experiments have shown that reducing the |
| 222 | * number of bits based on the write domains has little performance |
| 223 | * impact. |
| 224 | */ |
| 225 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 226 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 227 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 228 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 229 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 230 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 231 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 232 | |
| 233 | ret = intel_ring_begin(ring, 6); |
| 234 | if (ret) |
| 235 | return ret; |
| 236 | |
| 237 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 238 | intel_ring_emit(ring, flags); |
| 239 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 240 | intel_ring_emit(ring, 0); /* lower dword */ |
| 241 | intel_ring_emit(ring, 0); /* uppwer dword */ |
| 242 | intel_ring_emit(ring, MI_NOOP); |
| 243 | intel_ring_advance(ring); |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 248 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 249 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 250 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 251 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 252 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 253 | } |
| 254 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 255 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 256 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 257 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 258 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 259 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 260 | |
| 261 | return I915_READ(acthd_reg); |
| 262 | } |
| 263 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 264 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 265 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 266 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 267 | struct drm_i915_gem_object *obj = ring->obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 268 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 269 | |
| 270 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 271 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 272 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 273 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 274 | |
| 275 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 276 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 277 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 278 | |
| 279 | /* G45 ring initialization fails to reset head to zero */ |
| 280 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 281 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 282 | "ctl %08x head %08x tail %08x start %08x\n", |
| 283 | ring->name, |
| 284 | I915_READ_CTL(ring), |
| 285 | I915_READ_HEAD(ring), |
| 286 | I915_READ_TAIL(ring), |
| 287 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 288 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 289 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 290 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 291 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 292 | DRM_ERROR("failed to set %s head to zero " |
| 293 | "ctl %08x head %08x tail %08x start %08x\n", |
| 294 | ring->name, |
| 295 | I915_READ_CTL(ring), |
| 296 | I915_READ_HEAD(ring), |
| 297 | I915_READ_TAIL(ring), |
| 298 | I915_READ_START(ring)); |
| 299 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 300 | } |
| 301 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 302 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 303 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame^] | 304 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 305 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 306 | /* If the head is still not zero, the ring is dead */ |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 307 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 308 | I915_READ_START(ring) != obj->gtt_offset || |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 309 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 310 | DRM_ERROR("%s initialization failed " |
| 311 | "ctl %08x head %08x tail %08x start %08x\n", |
| 312 | ring->name, |
| 313 | I915_READ_CTL(ring), |
| 314 | I915_READ_HEAD(ring), |
| 315 | I915_READ_TAIL(ring), |
| 316 | I915_READ_START(ring)); |
| 317 | return -EIO; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 318 | } |
| 319 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 320 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 321 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 322 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 323 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 324 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 325 | ring->space = ring_space(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 326 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 327 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 328 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 329 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 330 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 331 | static int |
| 332 | init_pipe_control(struct intel_ring_buffer *ring) |
| 333 | { |
| 334 | struct pipe_control *pc; |
| 335 | struct drm_i915_gem_object *obj; |
| 336 | int ret; |
| 337 | |
| 338 | if (ring->private) |
| 339 | return 0; |
| 340 | |
| 341 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 342 | if (!pc) |
| 343 | return -ENOMEM; |
| 344 | |
| 345 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 346 | if (obj == NULL) { |
| 347 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 348 | ret = -ENOMEM; |
| 349 | goto err; |
| 350 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 351 | |
| 352 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 353 | |
| 354 | ret = i915_gem_object_pin(obj, 4096, true); |
| 355 | if (ret) |
| 356 | goto err_unref; |
| 357 | |
| 358 | pc->gtt_offset = obj->gtt_offset; |
| 359 | pc->cpu_page = kmap(obj->pages[0]); |
| 360 | if (pc->cpu_page == NULL) |
| 361 | goto err_unpin; |
| 362 | |
| 363 | pc->obj = obj; |
| 364 | ring->private = pc; |
| 365 | return 0; |
| 366 | |
| 367 | err_unpin: |
| 368 | i915_gem_object_unpin(obj); |
| 369 | err_unref: |
| 370 | drm_gem_object_unreference(&obj->base); |
| 371 | err: |
| 372 | kfree(pc); |
| 373 | return ret; |
| 374 | } |
| 375 | |
| 376 | static void |
| 377 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 378 | { |
| 379 | struct pipe_control *pc = ring->private; |
| 380 | struct drm_i915_gem_object *obj; |
| 381 | |
| 382 | if (!ring->private) |
| 383 | return; |
| 384 | |
| 385 | obj = pc->obj; |
| 386 | kunmap(obj->pages[0]); |
| 387 | i915_gem_object_unpin(obj); |
| 388 | drm_gem_object_unreference(&obj->base); |
| 389 | |
| 390 | kfree(pc); |
| 391 | ring->private = NULL; |
| 392 | } |
| 393 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 394 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 395 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 396 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 397 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 398 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 399 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 400 | if (INTEL_INFO(dev)->gen > 3) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 401 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
Jesse Barnes | 65d3eb1 | 2011-04-06 14:54:44 -0700 | [diff] [blame] | 402 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 403 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
| 404 | I915_WRITE(MI_MODE, mode); |
Jesse Barnes | b095cd0 | 2011-08-12 15:28:32 -0700 | [diff] [blame] | 405 | if (IS_GEN7(dev)) |
| 406 | I915_WRITE(GFX_MODE_GEN7, |
| 407 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 408 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 409 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 410 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 411 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 412 | ret = init_pipe_control(ring); |
| 413 | if (ret) |
| 414 | return ret; |
| 415 | } |
| 416 | |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 417 | if (INTEL_INFO(dev)->gen >= 6) { |
| 418 | I915_WRITE(INSTPM, |
| 419 | INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); |
| 420 | } |
| 421 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 422 | return ret; |
| 423 | } |
| 424 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 425 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 426 | { |
| 427 | if (!ring->private) |
| 428 | return; |
| 429 | |
| 430 | cleanup_pipe_control(ring); |
| 431 | } |
| 432 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 433 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 434 | update_mboxes(struct intel_ring_buffer *ring, |
| 435 | u32 seqno, |
| 436 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 437 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 438 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
| 439 | MI_SEMAPHORE_GLOBAL_GTT | |
| 440 | MI_SEMAPHORE_REGISTER | |
| 441 | MI_SEMAPHORE_UPDATE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 442 | intel_ring_emit(ring, seqno); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 443 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 444 | } |
| 445 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 446 | /** |
| 447 | * gen6_add_request - Update the semaphore mailbox registers |
| 448 | * |
| 449 | * @ring - ring that is adding a request |
| 450 | * @seqno - return seqno stuck into the ring |
| 451 | * |
| 452 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 453 | * This acts like a signal in the canonical semaphore. |
| 454 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 455 | static int |
| 456 | gen6_add_request(struct intel_ring_buffer *ring, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 457 | u32 *seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 458 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 459 | u32 mbox1_reg; |
| 460 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 461 | int ret; |
| 462 | |
| 463 | ret = intel_ring_begin(ring, 10); |
| 464 | if (ret) |
| 465 | return ret; |
| 466 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 467 | mbox1_reg = ring->signal_mbox[0]; |
| 468 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 469 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 470 | *seqno = i915_gem_get_seqno(ring->dev); |
| 471 | |
| 472 | update_mboxes(ring, *seqno, mbox1_reg); |
| 473 | update_mboxes(ring, *seqno, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 474 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 475 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 476 | intel_ring_emit(ring, *seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 477 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 478 | intel_ring_advance(ring); |
| 479 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 480 | return 0; |
| 481 | } |
| 482 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 483 | /** |
| 484 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 485 | * |
| 486 | * @waiter - ring that is waiting |
| 487 | * @signaller - ring which has, or will signal |
| 488 | * @seqno - seqno which the waiter will block on |
| 489 | */ |
| 490 | static int |
| 491 | intel_ring_sync(struct intel_ring_buffer *waiter, |
| 492 | struct intel_ring_buffer *signaller, |
| 493 | int ring, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 494 | u32 seqno) |
| 495 | { |
| 496 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 497 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 498 | MI_SEMAPHORE_COMPARE | |
| 499 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 500 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 501 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 502 | if (ret) |
| 503 | return ret; |
| 504 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 505 | intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]); |
| 506 | intel_ring_emit(waiter, seqno); |
| 507 | intel_ring_emit(waiter, 0); |
| 508 | intel_ring_emit(waiter, MI_NOOP); |
| 509 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 514 | /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */ |
| 515 | int |
| 516 | render_ring_sync_to(struct intel_ring_buffer *waiter, |
| 517 | struct intel_ring_buffer *signaller, |
| 518 | u32 seqno) |
| 519 | { |
| 520 | WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 521 | return intel_ring_sync(waiter, |
| 522 | signaller, |
| 523 | RCS, |
| 524 | seqno); |
| 525 | } |
| 526 | |
| 527 | /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */ |
| 528 | int |
| 529 | gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter, |
| 530 | struct intel_ring_buffer *signaller, |
| 531 | u32 seqno) |
| 532 | { |
| 533 | WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 534 | return intel_ring_sync(waiter, |
| 535 | signaller, |
| 536 | VCS, |
| 537 | seqno); |
| 538 | } |
| 539 | |
| 540 | /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */ |
| 541 | int |
| 542 | gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, |
| 543 | struct intel_ring_buffer *signaller, |
| 544 | u32 seqno) |
| 545 | { |
| 546 | WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID); |
| 547 | return intel_ring_sync(waiter, |
| 548 | signaller, |
| 549 | BCS, |
| 550 | seqno); |
| 551 | } |
| 552 | |
| 553 | |
| 554 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 555 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 556 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 557 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 558 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 559 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 560 | intel_ring_emit(ring__, 0); \ |
| 561 | intel_ring_emit(ring__, 0); \ |
| 562 | } while (0) |
| 563 | |
| 564 | static int |
| 565 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 566 | u32 *result) |
| 567 | { |
| 568 | struct drm_device *dev = ring->dev; |
| 569 | u32 seqno = i915_gem_get_seqno(dev); |
| 570 | struct pipe_control *pc = ring->private; |
| 571 | u32 scratch_addr = pc->gtt_offset + 128; |
| 572 | int ret; |
| 573 | |
| 574 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 575 | * incoherent with writes to memory, i.e. completely fubar, |
| 576 | * so we need to use PIPE_NOTIFY instead. |
| 577 | * |
| 578 | * However, we also need to workaround the qword write |
| 579 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 580 | * memory before requesting an interrupt. |
| 581 | */ |
| 582 | ret = intel_ring_begin(ring, 32); |
| 583 | if (ret) |
| 584 | return ret; |
| 585 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 586 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 587 | PIPE_CONTROL_WRITE_FLUSH | |
| 588 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 589 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 590 | intel_ring_emit(ring, seqno); |
| 591 | intel_ring_emit(ring, 0); |
| 592 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 593 | scratch_addr += 128; /* write to separate cachelines */ |
| 594 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 595 | scratch_addr += 128; |
| 596 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 597 | scratch_addr += 128; |
| 598 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 599 | scratch_addr += 128; |
| 600 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 601 | scratch_addr += 128; |
| 602 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 603 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 604 | PIPE_CONTROL_WRITE_FLUSH | |
| 605 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 606 | PIPE_CONTROL_NOTIFY); |
| 607 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 608 | intel_ring_emit(ring, seqno); |
| 609 | intel_ring_emit(ring, 0); |
| 610 | intel_ring_advance(ring); |
| 611 | |
| 612 | *result = seqno; |
| 613 | return 0; |
| 614 | } |
| 615 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 616 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 617 | render_ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 618 | u32 *result) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 619 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 620 | struct drm_device *dev = ring->dev; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 621 | u32 seqno = i915_gem_get_seqno(dev); |
| 622 | int ret; |
Zhenyu Wang | ca76482 | 2010-05-27 10:26:42 +0800 | [diff] [blame] | 623 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 624 | ret = intel_ring_begin(ring, 4); |
| 625 | if (ret) |
| 626 | return ret; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 627 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 628 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 629 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 630 | intel_ring_emit(ring, seqno); |
| 631 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 632 | intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 633 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 634 | *result = seqno; |
| 635 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 636 | } |
| 637 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 638 | static u32 |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 639 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) |
| 640 | { |
| 641 | struct drm_device *dev = ring->dev; |
| 642 | |
| 643 | /* Workaround to force correct ordering between irq and seqno writes on |
| 644 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 645 | * ACTHD) before reading the status page. */ |
| 646 | if (IS_GEN7(dev)) |
| 647 | intel_ring_get_active_head(ring); |
| 648 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 649 | } |
| 650 | |
| 651 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 652 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 653 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 654 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 655 | } |
| 656 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 657 | static u32 |
| 658 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 659 | { |
| 660 | struct pipe_control *pc = ring->private; |
| 661 | return pc->cpu_page[0]; |
| 662 | } |
| 663 | |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 664 | static void |
| 665 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 666 | { |
| 667 | dev_priv->gt_irq_mask &= ~mask; |
| 668 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 669 | POSTING_READ(GTIMR); |
| 670 | } |
| 671 | |
| 672 | static void |
| 673 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 674 | { |
| 675 | dev_priv->gt_irq_mask |= mask; |
| 676 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 677 | POSTING_READ(GTIMR); |
| 678 | } |
| 679 | |
| 680 | static void |
| 681 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 682 | { |
| 683 | dev_priv->irq_mask &= ~mask; |
| 684 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 685 | POSTING_READ(IMR); |
| 686 | } |
| 687 | |
| 688 | static void |
| 689 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 690 | { |
| 691 | dev_priv->irq_mask |= mask; |
| 692 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 693 | POSTING_READ(IMR); |
| 694 | } |
| 695 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 696 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 697 | render_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 698 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 699 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 700 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 701 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 702 | if (!dev->irq_enabled) |
| 703 | return false; |
| 704 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 705 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 706 | if (ring->irq_refcount++ == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 707 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 708 | ironlake_enable_irq(dev_priv, |
| 709 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 710 | else |
| 711 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 712 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 713 | spin_unlock(&ring->irq_lock); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 714 | |
| 715 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 718 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 719 | render_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 720 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 721 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 722 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 723 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 724 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 725 | if (--ring->irq_refcount == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 726 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 727 | ironlake_disable_irq(dev_priv, |
| 728 | GT_USER_INTERRUPT | |
| 729 | GT_PIPE_NOTIFY); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 730 | else |
| 731 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 732 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 733 | spin_unlock(&ring->irq_lock); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 734 | } |
| 735 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 736 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 737 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 738 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 739 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 740 | u32 mmio = 0; |
| 741 | |
| 742 | /* The ring status page addresses are no longer next to the rest of |
| 743 | * the ring registers as of gen7. |
| 744 | */ |
| 745 | if (IS_GEN7(dev)) { |
| 746 | switch (ring->id) { |
| 747 | case RING_RENDER: |
| 748 | mmio = RENDER_HWS_PGA_GEN7; |
| 749 | break; |
| 750 | case RING_BLT: |
| 751 | mmio = BLT_HWS_PGA_GEN7; |
| 752 | break; |
| 753 | case RING_BSD: |
| 754 | mmio = BSD_HWS_PGA_GEN7; |
| 755 | break; |
| 756 | } |
| 757 | } else if (IS_GEN6(ring->dev)) { |
| 758 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 759 | } else { |
| 760 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 761 | } |
| 762 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 763 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 764 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 765 | } |
| 766 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 767 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 768 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 769 | u32 invalidate_domains, |
| 770 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 771 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 772 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 773 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 774 | ret = intel_ring_begin(ring, 2); |
| 775 | if (ret) |
| 776 | return ret; |
| 777 | |
| 778 | intel_ring_emit(ring, MI_FLUSH); |
| 779 | intel_ring_emit(ring, MI_NOOP); |
| 780 | intel_ring_advance(ring); |
| 781 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 782 | } |
| 783 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 784 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 785 | ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 786 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 787 | { |
| 788 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 789 | int ret; |
| 790 | |
| 791 | ret = intel_ring_begin(ring, 4); |
| 792 | if (ret) |
| 793 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 794 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 795 | seqno = i915_gem_get_seqno(ring->dev); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 796 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 797 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 798 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 799 | intel_ring_emit(ring, seqno); |
| 800 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 801 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 802 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 803 | *result = seqno; |
| 804 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 805 | } |
| 806 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 807 | static bool |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 808 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 809 | { |
| 810 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 811 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 812 | |
| 813 | if (!dev->irq_enabled) |
| 814 | return false; |
| 815 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 816 | /* It looks like we need to prevent the gt from suspending while waiting |
| 817 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 818 | * blt/bsd rings on ivb. */ |
| 819 | if (IS_GEN7(dev)) |
| 820 | gen6_gt_force_wake_get(dev_priv); |
| 821 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 822 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 823 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 824 | ring->irq_mask &= ~rflag; |
| 825 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 826 | ironlake_enable_irq(dev_priv, gflag); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 827 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 828 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 829 | |
| 830 | return true; |
| 831 | } |
| 832 | |
| 833 | static void |
| 834 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 835 | { |
| 836 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 837 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 838 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 839 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 840 | if (--ring->irq_refcount == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 841 | ring->irq_mask |= rflag; |
| 842 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 843 | ironlake_disable_irq(dev_priv, gflag); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 844 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 845 | spin_unlock(&ring->irq_lock); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 846 | |
| 847 | if (IS_GEN7(dev)) |
| 848 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 849 | } |
| 850 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 851 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 852 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 853 | { |
Feng, Boqun | 5bfa106 | 2011-05-16 16:02:39 +0800 | [diff] [blame] | 854 | struct drm_device *dev = ring->dev; |
| 855 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 856 | |
| 857 | if (!dev->irq_enabled) |
| 858 | return false; |
| 859 | |
| 860 | spin_lock(&ring->irq_lock); |
| 861 | if (ring->irq_refcount++ == 0) { |
| 862 | if (IS_G4X(dev)) |
| 863 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
| 864 | else |
| 865 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
| 866 | } |
| 867 | spin_unlock(&ring->irq_lock); |
| 868 | |
| 869 | return true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 870 | } |
| 871 | static void |
| 872 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 873 | { |
Feng, Boqun | 5bfa106 | 2011-05-16 16:02:39 +0800 | [diff] [blame] | 874 | struct drm_device *dev = ring->dev; |
| 875 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 876 | |
| 877 | spin_lock(&ring->irq_lock); |
| 878 | if (--ring->irq_refcount == 0) { |
| 879 | if (IS_G4X(dev)) |
| 880 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
| 881 | else |
| 882 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
| 883 | } |
| 884 | spin_unlock(&ring->irq_lock); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 885 | } |
| 886 | |
| 887 | static int |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 888 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 889 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 890 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 891 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 892 | ret = intel_ring_begin(ring, 2); |
| 893 | if (ret) |
| 894 | return ret; |
| 895 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 896 | intel_ring_emit(ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 897 | MI_BATCH_BUFFER_START | (2 << 6) | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 898 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 899 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 900 | intel_ring_advance(ring); |
| 901 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 902 | return 0; |
| 903 | } |
| 904 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 905 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 906 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 907 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 908 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 909 | struct drm_device *dev = ring->dev; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 910 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 911 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 912 | if (IS_I830(dev) || IS_845G(dev)) { |
| 913 | ret = intel_ring_begin(ring, 4); |
| 914 | if (ret) |
| 915 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 916 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 917 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 918 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 919 | intel_ring_emit(ring, offset + len - 8); |
| 920 | intel_ring_emit(ring, 0); |
| 921 | } else { |
| 922 | ret = intel_ring_begin(ring, 2); |
| 923 | if (ret) |
| 924 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 925 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 926 | if (INTEL_INFO(dev)->gen >= 4) { |
| 927 | intel_ring_emit(ring, |
| 928 | MI_BATCH_BUFFER_START | (2 << 6) | |
| 929 | MI_BATCH_NON_SECURE_I965); |
| 930 | intel_ring_emit(ring, offset); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 931 | } else { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 932 | intel_ring_emit(ring, |
| 933 | MI_BATCH_BUFFER_START | (2 << 6)); |
| 934 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 935 | } |
| 936 | } |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 937 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 938 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 939 | return 0; |
| 940 | } |
| 941 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 942 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 943 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 944 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 945 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 946 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 947 | obj = ring->status_page.obj; |
| 948 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 949 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 950 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 951 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 952 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 953 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 954 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 955 | |
| 956 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 957 | } |
| 958 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 959 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 960 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 961 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 962 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 963 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 964 | int ret; |
| 965 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 966 | obj = i915_gem_alloc_object(dev, 4096); |
| 967 | if (obj == NULL) { |
| 968 | DRM_ERROR("Failed to allocate status page\n"); |
| 969 | ret = -ENOMEM; |
| 970 | goto err; |
| 971 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 972 | |
| 973 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 974 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 975 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 976 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 977 | goto err_unref; |
| 978 | } |
| 979 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 980 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 981 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 982 | if (ring->status_page.page_addr == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 983 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 984 | goto err_unpin; |
| 985 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 986 | ring->status_page.obj = obj; |
| 987 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 988 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 989 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 990 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 991 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 992 | |
| 993 | return 0; |
| 994 | |
| 995 | err_unpin: |
| 996 | i915_gem_object_unpin(obj); |
| 997 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 998 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 999 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1000 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1001 | } |
| 1002 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1003 | int intel_init_ring_buffer(struct drm_device *dev, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1004 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1005 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1006 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1007 | int ret; |
| 1008 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1009 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1010 | INIT_LIST_HEAD(&ring->active_list); |
| 1011 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1012 | INIT_LIST_HEAD(&ring->gpu_write_list); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1013 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1014 | init_waitqueue_head(&ring->irq_queue); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1015 | spin_lock_init(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1016 | ring->irq_mask = ~0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1017 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1018 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1019 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1020 | if (ret) |
| 1021 | return ret; |
| 1022 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1023 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1024 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1025 | if (obj == NULL) { |
| 1026 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1027 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1028 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1029 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1030 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1031 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1032 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1033 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1034 | if (ret) |
| 1035 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1036 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1037 | ring->map.size = ring->size; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1038 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1039 | ring->map.type = 0; |
| 1040 | ring->map.flags = 0; |
| 1041 | ring->map.mtrr = 0; |
| 1042 | |
| 1043 | drm_core_ioremap_wc(&ring->map, dev); |
| 1044 | if (ring->map.handle == NULL) { |
| 1045 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1046 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1047 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1048 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1049 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1050 | ring->virtual_start = ring->map.handle; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1051 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1052 | if (ret) |
| 1053 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1054 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1055 | /* Workaround an erratum on the i830 which causes a hang if |
| 1056 | * the TAIL pointer points to within the last 2 cachelines |
| 1057 | * of the buffer. |
| 1058 | */ |
| 1059 | ring->effective_size = ring->size; |
| 1060 | if (IS_I830(ring->dev)) |
| 1061 | ring->effective_size -= 128; |
| 1062 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1063 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1064 | |
| 1065 | err_unmap: |
| 1066 | drm_core_ioremapfree(&ring->map, dev); |
| 1067 | err_unpin: |
| 1068 | i915_gem_object_unpin(obj); |
| 1069 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1070 | drm_gem_object_unreference(&obj->base); |
| 1071 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1072 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1073 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1074 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1075 | } |
| 1076 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1077 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1078 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1079 | struct drm_i915_private *dev_priv; |
| 1080 | int ret; |
| 1081 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1082 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1083 | return; |
| 1084 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1085 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1086 | dev_priv = ring->dev->dev_private; |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 1087 | ret = intel_wait_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1088 | if (ret) |
| 1089 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1090 | ring->name, ret); |
| 1091 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1092 | I915_WRITE_CTL(ring, 0); |
| 1093 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1094 | drm_core_ioremapfree(&ring->map, ring->dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1095 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1096 | i915_gem_object_unpin(ring->obj); |
| 1097 | drm_gem_object_unreference(&ring->obj->base); |
| 1098 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1099 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1100 | if (ring->cleanup) |
| 1101 | ring->cleanup(ring); |
| 1102 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1103 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1104 | } |
| 1105 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1106 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1107 | { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1108 | unsigned int *virt; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1109 | int rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1110 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1111 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1112 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1113 | if (ret) |
| 1114 | return ret; |
| 1115 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1116 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1117 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1118 | rem /= 8; |
| 1119 | while (rem--) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1120 | *virt++ = MI_NOOP; |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1121 | *virt++ = MI_NOOP; |
| 1122 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1123 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1124 | ring->tail = 0; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1125 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1126 | |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1130 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1131 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1132 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1133 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1134 | unsigned long end; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1135 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1136 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1137 | if (drm_core_check_feature(dev, DRIVER_GEM)) |
| 1138 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1139 | * leaving it early runs the risk of corrupting GEM state (due |
| 1140 | * to running on almost untested codepaths). But on resume |
| 1141 | * timers don't work yet, so prevent a complete hang in that |
| 1142 | * case by choosing an insanely large timeout. */ |
| 1143 | end = jiffies + 60 * HZ; |
| 1144 | else |
| 1145 | end = jiffies + 3 * HZ; |
| 1146 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1147 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1148 | ring->head = I915_READ_HEAD(ring); |
| 1149 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1150 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1151 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1152 | return 0; |
| 1153 | } |
| 1154 | |
| 1155 | if (dev->primary->master) { |
| 1156 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1157 | if (master_priv->sarea_priv) |
| 1158 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1159 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1160 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1161 | msleep(1); |
Chris Wilson | f4e0b29 | 2010-10-29 21:06:16 +0100 | [diff] [blame] | 1162 | if (atomic_read(&dev_priv->mm.wedged)) |
| 1163 | return -EAGAIN; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1164 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1165 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1166 | return -EBUSY; |
| 1167 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1168 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1169 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1170 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1171 | { |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1172 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 1173 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1174 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1175 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1176 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
| 1177 | return -EIO; |
| 1178 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1179 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1180 | ret = intel_wrap_ring_buffer(ring); |
| 1181 | if (unlikely(ret)) |
| 1182 | return ret; |
| 1183 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1184 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1185 | if (unlikely(ring->space < n)) { |
| 1186 | ret = intel_wait_ring_buffer(ring, n); |
| 1187 | if (unlikely(ret)) |
| 1188 | return ret; |
| 1189 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1190 | |
| 1191 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1192 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1193 | } |
| 1194 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1195 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1196 | { |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1197 | ring->tail &= ring->size - 1; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1198 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1199 | } |
| 1200 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1201 | static const struct intel_ring_buffer render_ring = { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1202 | .name = "render ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 1203 | .id = RING_RENDER, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1204 | .mmio_base = RENDER_RING_BASE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1205 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1206 | .init = init_render_ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1207 | .write_tail = ring_write_tail, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1208 | .flush = render_ring_flush, |
| 1209 | .add_request = render_ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1210 | .get_seqno = ring_get_seqno, |
| 1211 | .irq_get = render_ring_get_irq, |
| 1212 | .irq_put = render_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1213 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1214 | .cleanup = render_ring_cleanup, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1215 | .sync_to = render_ring_sync_to, |
| 1216 | .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID, |
| 1217 | MI_SEMAPHORE_SYNC_RV, |
| 1218 | MI_SEMAPHORE_SYNC_RB}, |
| 1219 | .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC}, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1220 | }; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1221 | |
| 1222 | /* ring buffer for bit-stream decoder */ |
| 1223 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1224 | static const struct intel_ring_buffer bsd_ring = { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1225 | .name = "bsd ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 1226 | .id = RING_BSD, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1227 | .mmio_base = BSD_RING_BASE, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1228 | .size = 32 * PAGE_SIZE, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1229 | .init = init_ring_common, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1230 | .write_tail = ring_write_tail, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1231 | .flush = bsd_ring_flush, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1232 | .add_request = ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1233 | .get_seqno = ring_get_seqno, |
| 1234 | .irq_get = bsd_ring_get_irq, |
| 1235 | .irq_put = bsd_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1236 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1237 | }; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1238 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1239 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1240 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1241 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1242 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1243 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1244 | |
| 1245 | /* Every tail move must follow the sequence below */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1246 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1247 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1248 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
| 1249 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1250 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1251 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 1252 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
| 1253 | 50)) |
| 1254 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1255 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1256 | I915_WRITE_TAIL(ring, value); |
| 1257 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1258 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1259 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1260 | } |
| 1261 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1262 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1263 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1264 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1265 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1266 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1267 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1268 | ret = intel_ring_begin(ring, 4); |
| 1269 | if (ret) |
| 1270 | return ret; |
| 1271 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1272 | cmd = MI_FLUSH_DW; |
| 1273 | if (invalidate & I915_GEM_GPU_DOMAINS) |
| 1274 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 1275 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1276 | intel_ring_emit(ring, 0); |
| 1277 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1278 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1279 | intel_ring_advance(ring); |
| 1280 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1281 | } |
| 1282 | |
| 1283 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1284 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1285 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1286 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1287 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1288 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1289 | ret = intel_ring_begin(ring, 2); |
| 1290 | if (ret) |
| 1291 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1292 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1293 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
| 1294 | /* bit0-7 is the length on GEN6+ */ |
| 1295 | intel_ring_emit(ring, offset); |
| 1296 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1297 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1298 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1299 | } |
| 1300 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1301 | static bool |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1302 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
| 1303 | { |
| 1304 | return gen6_ring_get_irq(ring, |
| 1305 | GT_USER_INTERRUPT, |
| 1306 | GEN6_RENDER_USER_INTERRUPT); |
| 1307 | } |
| 1308 | |
| 1309 | static void |
| 1310 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
| 1311 | { |
| 1312 | return gen6_ring_put_irq(ring, |
| 1313 | GT_USER_INTERRUPT, |
| 1314 | GEN6_RENDER_USER_INTERRUPT); |
| 1315 | } |
| 1316 | |
| 1317 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1318 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 1319 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1320 | return gen6_ring_get_irq(ring, |
| 1321 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1322 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | static void |
| 1326 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 1327 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1328 | return gen6_ring_put_irq(ring, |
| 1329 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1330 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1331 | } |
| 1332 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1333 | /* ring buffer for Video Codec for Gen6+ */ |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1334 | static const struct intel_ring_buffer gen6_bsd_ring = { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1335 | .name = "gen6 bsd ring", |
| 1336 | .id = RING_BSD, |
| 1337 | .mmio_base = GEN6_BSD_RING_BASE, |
| 1338 | .size = 32 * PAGE_SIZE, |
| 1339 | .init = init_ring_common, |
| 1340 | .write_tail = gen6_bsd_ring_write_tail, |
| 1341 | .flush = gen6_ring_flush, |
| 1342 | .add_request = gen6_add_request, |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1343 | .get_seqno = gen6_ring_get_seqno, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1344 | .irq_get = gen6_bsd_ring_get_irq, |
| 1345 | .irq_put = gen6_bsd_ring_put_irq, |
| 1346 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1347 | .sync_to = gen6_bsd_ring_sync_to, |
| 1348 | .semaphore_register = {MI_SEMAPHORE_SYNC_VR, |
| 1349 | MI_SEMAPHORE_SYNC_INVALID, |
| 1350 | MI_SEMAPHORE_SYNC_VB}, |
| 1351 | .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC}, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1352 | }; |
| 1353 | |
| 1354 | /* Blitter support (SandyBridge+) */ |
| 1355 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1356 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1357 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1358 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1359 | return gen6_ring_get_irq(ring, |
| 1360 | GT_BLT_USER_INTERRUPT, |
| 1361 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1362 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1363 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1364 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1365 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1366 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1367 | gen6_ring_put_irq(ring, |
| 1368 | GT_BLT_USER_INTERRUPT, |
| 1369 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1370 | } |
| 1371 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1372 | |
| 1373 | /* Workaround for some stepping of SNB, |
| 1374 | * each time when BLT engine ring tail moved, |
| 1375 | * the first command in the ring to be parsed |
| 1376 | * should be MI_BATCH_BUFFER_START |
| 1377 | */ |
| 1378 | #define NEED_BLT_WORKAROUND(dev) \ |
| 1379 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
| 1380 | |
| 1381 | static inline struct drm_i915_gem_object * |
| 1382 | to_blt_workaround(struct intel_ring_buffer *ring) |
| 1383 | { |
| 1384 | return ring->private; |
| 1385 | } |
| 1386 | |
| 1387 | static int blt_ring_init(struct intel_ring_buffer *ring) |
| 1388 | { |
| 1389 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
| 1390 | struct drm_i915_gem_object *obj; |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1391 | u32 *ptr; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1392 | int ret; |
| 1393 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1394 | obj = i915_gem_alloc_object(ring->dev, 4096); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1395 | if (obj == NULL) |
| 1396 | return -ENOMEM; |
| 1397 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1398 | ret = i915_gem_object_pin(obj, 4096, true); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1399 | if (ret) { |
| 1400 | drm_gem_object_unreference(&obj->base); |
| 1401 | return ret; |
| 1402 | } |
| 1403 | |
| 1404 | ptr = kmap(obj->pages[0]); |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1405 | *ptr++ = MI_BATCH_BUFFER_END; |
| 1406 | *ptr++ = MI_NOOP; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1407 | kunmap(obj->pages[0]); |
| 1408 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1409 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1410 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1411 | i915_gem_object_unpin(obj); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1412 | drm_gem_object_unreference(&obj->base); |
| 1413 | return ret; |
| 1414 | } |
| 1415 | |
| 1416 | ring->private = obj; |
| 1417 | } |
| 1418 | |
| 1419 | return init_ring_common(ring); |
| 1420 | } |
| 1421 | |
| 1422 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
| 1423 | int num_dwords) |
| 1424 | { |
| 1425 | if (ring->private) { |
| 1426 | int ret = intel_ring_begin(ring, num_dwords+2); |
| 1427 | if (ret) |
| 1428 | return ret; |
| 1429 | |
| 1430 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
| 1431 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
| 1432 | |
| 1433 | return 0; |
| 1434 | } else |
| 1435 | return intel_ring_begin(ring, 4); |
| 1436 | } |
| 1437 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1438 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1439 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1440 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1441 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1442 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1443 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1444 | ret = blt_ring_begin(ring, 4); |
| 1445 | if (ret) |
| 1446 | return ret; |
| 1447 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1448 | cmd = MI_FLUSH_DW; |
| 1449 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
| 1450 | cmd |= MI_INVALIDATE_TLB; |
| 1451 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1452 | intel_ring_emit(ring, 0); |
| 1453 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1454 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1455 | intel_ring_advance(ring); |
| 1456 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1457 | } |
| 1458 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1459 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
| 1460 | { |
| 1461 | if (!ring->private) |
| 1462 | return; |
| 1463 | |
| 1464 | i915_gem_object_unpin(ring->private); |
| 1465 | drm_gem_object_unreference(ring->private); |
| 1466 | ring->private = NULL; |
| 1467 | } |
| 1468 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1469 | static const struct intel_ring_buffer gen6_blt_ring = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1470 | .name = "blt ring", |
| 1471 | .id = RING_BLT, |
| 1472 | .mmio_base = BLT_RING_BASE, |
| 1473 | .size = 32 * PAGE_SIZE, |
| 1474 | .init = blt_ring_init, |
| 1475 | .write_tail = ring_write_tail, |
| 1476 | .flush = blt_ring_flush, |
| 1477 | .add_request = gen6_add_request, |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1478 | .get_seqno = gen6_ring_get_seqno, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1479 | .irq_get = blt_ring_get_irq, |
| 1480 | .irq_put = blt_ring_put_irq, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1481 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1482 | .cleanup = blt_ring_cleanup, |
| 1483 | .sync_to = gen6_blt_ring_sync_to, |
| 1484 | .semaphore_register = {MI_SEMAPHORE_SYNC_BR, |
| 1485 | MI_SEMAPHORE_SYNC_BV, |
| 1486 | MI_SEMAPHORE_SYNC_INVALID}, |
| 1487 | .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC}, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1488 | }; |
| 1489 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1490 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1491 | { |
| 1492 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1493 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1494 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1495 | *ring = render_ring; |
| 1496 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1497 | ring->add_request = gen6_add_request; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 1498 | ring->flush = gen6_render_ring_flush; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1499 | ring->irq_get = gen6_render_ring_get_irq; |
| 1500 | ring->irq_put = gen6_render_ring_put_irq; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1501 | ring->get_seqno = gen6_ring_get_seqno; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1502 | } else if (IS_GEN5(dev)) { |
| 1503 | ring->add_request = pc_render_add_request; |
| 1504 | ring->get_seqno = pc_render_get_seqno; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1505 | } |
| 1506 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1507 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1508 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1509 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1510 | } |
| 1511 | |
| 1512 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1513 | } |
| 1514 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1515 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1516 | { |
| 1517 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1518 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1519 | |
| 1520 | *ring = render_ring; |
| 1521 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1522 | ring->add_request = gen6_add_request; |
| 1523 | ring->irq_get = gen6_render_ring_get_irq; |
| 1524 | ring->irq_put = gen6_render_ring_put_irq; |
| 1525 | } else if (IS_GEN5(dev)) { |
| 1526 | ring->add_request = pc_render_add_request; |
| 1527 | ring->get_seqno = pc_render_get_seqno; |
| 1528 | } |
| 1529 | |
Keith Packard | f323470 | 2011-07-22 10:44:39 -0700 | [diff] [blame] | 1530 | if (!I915_NEED_GFX_HWS(dev)) |
| 1531 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1532 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1533 | ring->dev = dev; |
| 1534 | INIT_LIST_HEAD(&ring->active_list); |
| 1535 | INIT_LIST_HEAD(&ring->request_list); |
| 1536 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 1537 | |
| 1538 | ring->size = size; |
| 1539 | ring->effective_size = ring->size; |
| 1540 | if (IS_I830(ring->dev)) |
| 1541 | ring->effective_size -= 128; |
| 1542 | |
| 1543 | ring->map.offset = start; |
| 1544 | ring->map.size = size; |
| 1545 | ring->map.type = 0; |
| 1546 | ring->map.flags = 0; |
| 1547 | ring->map.mtrr = 0; |
| 1548 | |
| 1549 | drm_core_ioremap_wc(&ring->map, dev); |
| 1550 | if (ring->map.handle == NULL) { |
| 1551 | DRM_ERROR("can not ioremap virtual address for" |
| 1552 | " ring buffer\n"); |
| 1553 | return -ENOMEM; |
| 1554 | } |
| 1555 | |
| 1556 | ring->virtual_start = (void __force __iomem *)ring->map.handle; |
| 1557 | return 0; |
| 1558 | } |
| 1559 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1560 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1561 | { |
| 1562 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1563 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1564 | |
Jesse Barnes | 65d3eb1 | 2011-04-06 14:54:44 -0700 | [diff] [blame] | 1565 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1566 | *ring = gen6_bsd_ring; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1567 | else |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1568 | *ring = bsd_ring; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1569 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1570 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1571 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1572 | |
| 1573 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1574 | { |
| 1575 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1576 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1577 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1578 | *ring = gen6_blt_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1579 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1580 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1581 | } |