Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | #include <linux/mm.h> |
| 10 | #include <linux/delay.h> |
| 11 | #include <linux/clk.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/clkdev.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/err.h> |
| 16 | |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 17 | #include "crmregs-imx3.h" |
| 18 | #include "clk.h" |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 19 | #include "common.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 20 | #include "hardware.h" |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 21 | |
| 22 | struct arm_ahb_div { |
| 23 | unsigned char arm, ahb, sel; |
| 24 | }; |
| 25 | |
| 26 | static struct arm_ahb_div clk_consumer[] = { |
| 27 | { .arm = 1, .ahb = 4, .sel = 0}, |
| 28 | { .arm = 1, .ahb = 3, .sel = 1}, |
| 29 | { .arm = 2, .ahb = 2, .sel = 0}, |
| 30 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 31 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 32 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 33 | { .arm = 4, .ahb = 1, .sel = 0}, |
| 34 | { .arm = 1, .ahb = 5, .sel = 0}, |
| 35 | { .arm = 1, .ahb = 8, .sel = 0}, |
| 36 | { .arm = 1, .ahb = 6, .sel = 1}, |
| 37 | { .arm = 2, .ahb = 4, .sel = 0}, |
| 38 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 39 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 40 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 41 | { .arm = 4, .ahb = 2, .sel = 0}, |
| 42 | { .arm = 0, .ahb = 0, .sel = 0}, |
| 43 | }; |
| 44 | |
| 45 | static char hsp_div_532[] = { 4, 8, 3, 0 }; |
| 46 | static char hsp_div_400[] = { 3, 6, 3, 0 }; |
| 47 | |
| 48 | static const char *std_sel[] = {"ppll", "arm"}; |
| 49 | static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; |
| 50 | |
| 51 | enum mx35_clks { |
| 52 | ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, |
| 53 | arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, |
| 54 | esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, |
| 55 | spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, |
| 56 | ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, |
| 57 | audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, |
| 58 | edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, |
| 59 | esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, |
| 60 | gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, |
| 61 | kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, |
| 62 | rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, |
| 63 | ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, |
Alex Gershgorin | 7852399 | 2012-09-02 09:27:20 +0300 | [diff] [blame] | 64 | wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, |
| 65 | gpu2d_gate, clk_max |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | static struct clk *clk[clk_max]; |
| 69 | |
Fabio Estevam | 3ea8098 | 2013-01-08 23:37:01 -0200 | [diff] [blame] | 70 | int __init mx35_clocks_init(void) |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 71 | { |
| 72 | void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); |
| 73 | u32 pdr0, consumer_sel, hsp_sel; |
| 74 | struct arm_ahb_div *aad; |
| 75 | unsigned char *hsp_div; |
Fabio Estevam | 3ea8098 | 2013-01-08 23:37:01 -0200 | [diff] [blame] | 76 | u32 i; |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 77 | |
| 78 | pdr0 = __raw_readl(base + MXC_CCM_PDR0); |
| 79 | consumer_sel = (pdr0 >> 16) & 0xf; |
| 80 | aad = &clk_consumer[consumer_sel]; |
| 81 | if (!aad->arm) { |
| 82 | pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); |
| 83 | /* |
| 84 | * We are basically stuck. Continue with a default entry and hope we |
| 85 | * get far enough to actually show the above message |
| 86 | */ |
| 87 | aad = &clk_consumer[0]; |
| 88 | } |
| 89 | |
| 90 | clk[ckih] = imx_clk_fixed("ckih", 24000000); |
| 91 | clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); |
| 92 | clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); |
| 93 | |
| 94 | clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); |
| 95 | |
| 96 | if (aad->sel) |
| 97 | clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); |
| 98 | else |
| 99 | clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); |
| 100 | |
| 101 | if (clk_get_rate(clk[arm]) > 400000000) |
| 102 | hsp_div = hsp_div_532; |
| 103 | else |
| 104 | hsp_div = hsp_div_400; |
| 105 | |
| 106 | hsp_sel = (pdr0 >> 20) & 0x3; |
| 107 | if (!hsp_div[hsp_sel]) { |
| 108 | pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); |
| 109 | hsp_sel = 0; |
| 110 | } |
| 111 | |
| 112 | clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); |
| 113 | |
| 114 | clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); |
| 115 | clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); |
| 116 | |
| 117 | clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); |
| 118 | clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); |
| 119 | clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); |
| 120 | |
| 121 | clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 122 | clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); |
| 123 | |
| 124 | clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 125 | clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); |
| 126 | clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); |
| 127 | clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); |
| 128 | |
| 129 | clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 130 | clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ |
| 131 | clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); |
| 132 | |
| 133 | clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 134 | clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); |
| 135 | clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); |
| 136 | clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); |
| 137 | clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); |
| 138 | |
| 139 | clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 140 | clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); |
| 141 | |
| 142 | clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); |
| 143 | |
Alex Gershgorin | 7852399 | 2012-09-02 09:27:20 +0300 | [diff] [blame] | 144 | clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); |
| 145 | clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); |
| 146 | |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 147 | clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); |
| 148 | clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); |
| 149 | clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); |
| 150 | clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); |
| 151 | clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); |
| 152 | clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); |
| 153 | clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); |
| 154 | clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); |
| 155 | clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); |
| 156 | clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); |
| 157 | clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); |
| 158 | clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); |
| 159 | clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); |
| 160 | clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); |
| 161 | clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); |
| 162 | clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); |
| 163 | |
| 164 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); |
| 165 | clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); |
| 166 | clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); |
| 167 | clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); |
| 168 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); |
| 169 | clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); |
| 170 | clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); |
| 171 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); |
| 172 | clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); |
| 173 | clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); |
| 174 | clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); |
| 175 | clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); |
| 176 | clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); |
| 177 | clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); |
| 178 | clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); |
| 179 | clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); |
| 180 | |
| 181 | clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); |
| 182 | clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); |
| 183 | clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); |
| 184 | clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); |
| 185 | clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); |
| 186 | clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); |
| 187 | clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); |
| 188 | clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); |
| 189 | clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); |
| 190 | clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); |
| 191 | clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); |
| 192 | clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); |
| 193 | clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); |
| 194 | clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); |
| 195 | clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); |
| 196 | |
Alex Gershgorin | 7852399 | 2012-09-02 09:27:20 +0300 | [diff] [blame] | 197 | clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 198 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); |
| 199 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); |
| 200 | |
| 201 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
| 202 | if (IS_ERR(clk[i])) |
| 203 | pr_err("i.MX35 clk %d: register failed with %ld\n", |
| 204 | i, PTR_ERR(clk[i])); |
| 205 | |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 206 | clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); |
| 207 | clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); |
| 208 | clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); |
| 209 | clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); |
| 210 | clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); |
| 211 | clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); |
| 212 | clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); |
| 213 | clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); |
| 214 | clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); |
| 215 | clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); |
| 216 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); |
| 217 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); |
| 218 | clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); |
| 219 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); |
| 220 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); |
| 221 | clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); |
| 222 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); |
| 223 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); |
| 224 | /* i.mx35 has the i.mx27 type fec */ |
| 225 | clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); |
| 226 | clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); |
| 227 | clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 228 | clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); |
| 229 | clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); |
| 230 | clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 231 | clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); |
| 232 | clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); |
Alex Gershgorin | 7852399 | 2012-09-02 09:27:20 +0300 | [diff] [blame] | 233 | clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 234 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); |
| 235 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); |
Fabio Estevam | 4854005 | 2012-08-20 09:39:22 -0300 | [diff] [blame] | 236 | clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); |
| 237 | clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 238 | /* i.mx35 has the i.mx21 type uart */ |
| 239 | clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); |
| 240 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); |
| 241 | clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); |
| 242 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); |
| 243 | clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); |
| 244 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); |
| 245 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); |
| 246 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); |
| 247 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); |
| 248 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); |
| 249 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); |
| 250 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); |
| 251 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); |
| 252 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); |
| 253 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); |
Peter Chen | 61c4b56 | 2013-01-17 18:03:17 +0800 | [diff] [blame] | 254 | clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); |
| 255 | clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); |
| 256 | clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 257 | clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); |
Shawn Guo | 4d62435 | 2012-09-15 13:34:09 +0800 | [diff] [blame] | 258 | clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); |
Alex Gershgorin | 7852399 | 2012-09-02 09:27:20 +0300 | [diff] [blame] | 259 | clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 260 | |
| 261 | clk_prepare_enable(clk[spba_gate]); |
| 262 | clk_prepare_enable(clk[gpio1_gate]); |
| 263 | clk_prepare_enable(clk[gpio2_gate]); |
| 264 | clk_prepare_enable(clk[gpio3_gate]); |
| 265 | clk_prepare_enable(clk[iim_gate]); |
| 266 | clk_prepare_enable(clk[emi_gate]); |
| 267 | |
Uwe Kleine-König | c520c92 | 2012-07-02 11:30:34 +0200 | [diff] [blame] | 268 | /* |
| 269 | * SCC is needed to boot via mmc after a watchdog reset. The clock code |
| 270 | * before conversion to common clk also enabled UART1 (which isn't |
| 271 | * handled here and not needed for mmc) and IIM (which is enabled |
| 272 | * unconditionally above). |
| 273 | */ |
| 274 | clk_prepare_enable(clk[scc_gate]); |
| 275 | |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 276 | imx_print_silicon_rev("i.MX35", mx35_revision()); |
| 277 | |
| 278 | #ifdef CONFIG_MXC_USE_EPIT |
Sascha Hauer | 2cfb451 | 2012-05-16 12:29:53 +0200 | [diff] [blame] | 279 | epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 280 | #else |
Sascha Hauer | 2cfb451 | 2012-05-16 12:29:53 +0200 | [diff] [blame] | 281 | mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); |
Sascha Hauer | 5b48a61 | 2012-04-03 12:41:13 +0200 | [diff] [blame] | 282 | #endif |
| 283 | |
| 284 | return 0; |
| 285 | } |