SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/clock.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 David Brownell |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/fs.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/at91_pmc.h> |
| 29 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 30 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 31 | #include "clock.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 32 | |
Andrew Victor | 55c20c0 | 2006-06-20 19:31:39 +0100 | [diff] [blame] | 33 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 34 | /* |
| 35 | * There's a lot more which can be done with clocks, including cpufreq |
| 36 | * integration, slow clock mode support (for system suspend), letting |
| 37 | * PLLB be used at other rates (on boards that don't need USB), etc. |
| 38 | */ |
| 39 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 40 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
| 41 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) |
| 42 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 43 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 44 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 45 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 46 | /* |
| 47 | * Chips have some kind of clocks : group them by functionality |
| 48 | */ |
| 49 | #define cpu_has_utmi() ( cpu_is_at91cap9() \ |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 50 | || cpu_is_at91sam9rl() \ |
| 51 | || cpu_is_at91sam9g45()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 52 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 53 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
| 54 | || cpu_is_at91sam9g45()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 55 | |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 56 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 57 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 58 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
| 59 | || cpu_is_at91sam9g45())) |
| 60 | |
| 61 | #define cpu_has_upll() (cpu_is_at91sam9g45()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 62 | |
| 63 | /* USB host HS & FS */ |
| 64 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| 65 | |
| 66 | /* USB device FS only */ |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 67 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
| 68 | || cpu_is_at91sam9g45())) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 69 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 70 | static LIST_HEAD(clocks); |
| 71 | static DEFINE_SPINLOCK(clk_lock); |
| 72 | |
| 73 | static u32 at91_pllb_usb_init; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Four primary clock sources: two crystal oscillators (32K, main), and |
| 77 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at |
| 78 | * 48 MHz (unless no USB function clocks are needed). The main clock and |
| 79 | * both PLLs are turned off to run in "slow clock mode" (system suspend). |
| 80 | */ |
| 81 | static struct clk clk32k = { |
| 82 | .name = "clk32k", |
| 83 | .rate_hz = AT91_SLOW_CLOCK, |
| 84 | .users = 1, /* always on */ |
| 85 | .id = 0, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 86 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 87 | }; |
| 88 | static struct clk main_clk = { |
| 89 | .name = "main", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 90 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 91 | .id = 1, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 92 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 93 | }; |
| 94 | static struct clk plla = { |
| 95 | .name = "plla", |
| 96 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 97 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 98 | .id = 2, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 99 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | static void pllb_mode(struct clk *clk, int is_on) |
| 103 | { |
| 104 | u32 value; |
| 105 | |
| 106 | if (is_on) { |
| 107 | is_on = AT91_PMC_LOCKB; |
| 108 | value = at91_pllb_usb_init; |
| 109 | } else |
| 110 | value = 0; |
| 111 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 112 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 113 | at91_sys_write(AT91_CKGR_PLLBR, value); |
| 114 | |
| 115 | do { |
| 116 | cpu_relax(); |
| 117 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
| 118 | } |
| 119 | |
| 120 | static struct clk pllb = { |
| 121 | .name = "pllb", |
| 122 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 123 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 124 | .mode = pllb_mode, |
| 125 | .id = 3, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 126 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | static void pmc_sys_mode(struct clk *clk, int is_on) |
| 130 | { |
| 131 | if (is_on) |
| 132 | at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); |
| 133 | else |
| 134 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); |
| 135 | } |
| 136 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 137 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
| 138 | { |
| 139 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 140 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 141 | if (cpu_is_at91sam9g45()) { |
| 142 | if (is_on) |
| 143 | uckr |= AT91_PMC_BIASEN; |
| 144 | else |
| 145 | uckr &= ~AT91_PMC_BIASEN; |
| 146 | } |
| 147 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 148 | if (is_on) { |
| 149 | is_on = AT91_PMC_LOCKU; |
| 150 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
| 151 | } else |
| 152 | at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
| 153 | |
| 154 | do { |
| 155 | cpu_relax(); |
| 156 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
| 157 | } |
| 158 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 159 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 160 | static struct clk udpck = { |
| 161 | .name = "udpck", |
| 162 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 163 | .mode = pmc_sys_mode, |
| 164 | }; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 165 | static struct clk utmi_clk = { |
| 166 | .name = "utmi_clk", |
| 167 | .parent = &main_clk, |
| 168 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ |
| 169 | .mode = pmc_uckr_mode, |
| 170 | .type = CLK_TYPE_PLL, |
| 171 | }; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 172 | static struct clk uhpck = { |
| 173 | .name = "uhpck", |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 174 | /*.parent = ... we choose parent at runtime */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 175 | .mode = pmc_sys_mode, |
| 176 | }; |
| 177 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 178 | |
| 179 | /* |
| 180 | * The master clock is divided from the CPU clock (by 1-4). It's used for |
| 181 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more |
| 182 | * (e.g baud rate generation). It's sourced from one of the primary clocks. |
| 183 | */ |
| 184 | static struct clk mck = { |
| 185 | .name = "mck", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 186 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 190 | { |
| 191 | if (is_on) |
| 192 | at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); |
| 193 | else |
| 194 | at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); |
| 195 | } |
| 196 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 197 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| 198 | { |
| 199 | switch (css) { |
| 200 | case AT91_PMC_CSS_SLOW: |
| 201 | return &clk32k; |
| 202 | case AT91_PMC_CSS_MAIN: |
| 203 | return &main_clk; |
| 204 | case AT91_PMC_CSS_PLLA: |
| 205 | return &plla; |
| 206 | case AT91_PMC_CSS_PLLB: |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 207 | if (cpu_has_upll()) |
| 208 | /* CSS_PLLB == CSS_UPLL */ |
| 209 | return &utmi_clk; |
| 210 | else if (cpu_has_pllb()) |
| 211 | return &pllb; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 212 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 213 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 214 | return NULL; |
| 215 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 216 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 217 | /* |
| 218 | * Associate a particular clock with a function (eg, "uart") and device. |
| 219 | * The drivers can then request the same 'function' with several different |
| 220 | * devices and not care about which clock name to use. |
| 221 | */ |
| 222 | void __init at91_clock_associate(const char *id, struct device *dev, const char *func) |
| 223 | { |
| 224 | struct clk *clk = clk_get(NULL, id); |
| 225 | |
| 226 | if (!dev || !clk || !IS_ERR(clk_get(dev, func))) |
| 227 | return; |
| 228 | |
| 229 | clk->function = func; |
| 230 | clk->dev = dev; |
| 231 | } |
| 232 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 233 | /* clocks cannot be de-registered no refcounting necessary */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 234 | struct clk *clk_get(struct device *dev, const char *id) |
| 235 | { |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 236 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 237 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 238 | list_for_each_entry(clk, &clocks, node) { |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 239 | if (strcmp(id, clk->name) == 0) |
| 240 | return clk; |
| 241 | if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) |
| 242 | return clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | return ERR_PTR(-ENOENT); |
| 246 | } |
| 247 | EXPORT_SYMBOL(clk_get); |
| 248 | |
| 249 | void clk_put(struct clk *clk) |
| 250 | { |
| 251 | } |
| 252 | EXPORT_SYMBOL(clk_put); |
| 253 | |
| 254 | static void __clk_enable(struct clk *clk) |
| 255 | { |
| 256 | if (clk->parent) |
| 257 | __clk_enable(clk->parent); |
| 258 | if (clk->users++ == 0 && clk->mode) |
| 259 | clk->mode(clk, 1); |
| 260 | } |
| 261 | |
| 262 | int clk_enable(struct clk *clk) |
| 263 | { |
| 264 | unsigned long flags; |
| 265 | |
| 266 | spin_lock_irqsave(&clk_lock, flags); |
| 267 | __clk_enable(clk); |
| 268 | spin_unlock_irqrestore(&clk_lock, flags); |
| 269 | return 0; |
| 270 | } |
| 271 | EXPORT_SYMBOL(clk_enable); |
| 272 | |
| 273 | static void __clk_disable(struct clk *clk) |
| 274 | { |
| 275 | BUG_ON(clk->users == 0); |
| 276 | if (--clk->users == 0 && clk->mode) |
| 277 | clk->mode(clk, 0); |
| 278 | if (clk->parent) |
| 279 | __clk_disable(clk->parent); |
| 280 | } |
| 281 | |
| 282 | void clk_disable(struct clk *clk) |
| 283 | { |
| 284 | unsigned long flags; |
| 285 | |
| 286 | spin_lock_irqsave(&clk_lock, flags); |
| 287 | __clk_disable(clk); |
| 288 | spin_unlock_irqrestore(&clk_lock, flags); |
| 289 | } |
| 290 | EXPORT_SYMBOL(clk_disable); |
| 291 | |
| 292 | unsigned long clk_get_rate(struct clk *clk) |
| 293 | { |
| 294 | unsigned long flags; |
| 295 | unsigned long rate; |
| 296 | |
| 297 | spin_lock_irqsave(&clk_lock, flags); |
| 298 | for (;;) { |
| 299 | rate = clk->rate_hz; |
| 300 | if (rate || !clk->parent) |
| 301 | break; |
| 302 | clk = clk->parent; |
| 303 | } |
| 304 | spin_unlock_irqrestore(&clk_lock, flags); |
| 305 | return rate; |
| 306 | } |
| 307 | EXPORT_SYMBOL(clk_get_rate); |
| 308 | |
| 309 | /*------------------------------------------------------------------------*/ |
| 310 | |
| 311 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 312 | |
| 313 | /* |
| 314 | * For now, only the programmable clocks support reparenting (MCK could |
| 315 | * do this too, with care) or rate changing (the PLLs could do this too, |
| 316 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get |
| 317 | * a better rate match; we don't. |
| 318 | */ |
| 319 | |
| 320 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 321 | { |
| 322 | unsigned long flags; |
| 323 | unsigned prescale; |
| 324 | unsigned long actual; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 325 | unsigned long prev = ULONG_MAX; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 326 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 327 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 328 | return -EINVAL; |
| 329 | spin_lock_irqsave(&clk_lock, flags); |
| 330 | |
| 331 | actual = clk->parent->rate_hz; |
| 332 | for (prescale = 0; prescale < 7; prescale++) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 333 | if (actual > rate) |
| 334 | prev = actual; |
| 335 | |
| 336 | if (actual && actual <= rate) { |
| 337 | if ((prev - rate) < (rate - actual)) { |
| 338 | actual = prev; |
| 339 | prescale--; |
| 340 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 341 | break; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 342 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 343 | actual >>= 1; |
| 344 | } |
| 345 | |
| 346 | spin_unlock_irqrestore(&clk_lock, flags); |
| 347 | return (prescale < 7) ? actual : -ENOENT; |
| 348 | } |
| 349 | EXPORT_SYMBOL(clk_round_rate); |
| 350 | |
| 351 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 352 | { |
| 353 | unsigned long flags; |
| 354 | unsigned prescale; |
| 355 | unsigned long actual; |
| 356 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 357 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 358 | return -EINVAL; |
| 359 | if (clk->users) |
| 360 | return -EBUSY; |
| 361 | spin_lock_irqsave(&clk_lock, flags); |
| 362 | |
| 363 | actual = clk->parent->rate_hz; |
| 364 | for (prescale = 0; prescale < 7; prescale++) { |
| 365 | if (actual && actual <= rate) { |
| 366 | u32 pckr; |
| 367 | |
| 368 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 369 | pckr &= AT91_PMC_CSS; /* clock selection */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 370 | pckr |= prescale << 2; |
| 371 | at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); |
| 372 | clk->rate_hz = actual; |
| 373 | break; |
| 374 | } |
| 375 | actual >>= 1; |
| 376 | } |
| 377 | |
| 378 | spin_unlock_irqrestore(&clk_lock, flags); |
| 379 | return (prescale < 7) ? actual : -ENOENT; |
| 380 | } |
| 381 | EXPORT_SYMBOL(clk_set_rate); |
| 382 | |
| 383 | struct clk *clk_get_parent(struct clk *clk) |
| 384 | { |
| 385 | return clk->parent; |
| 386 | } |
| 387 | EXPORT_SYMBOL(clk_get_parent); |
| 388 | |
| 389 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 390 | { |
| 391 | unsigned long flags; |
| 392 | |
| 393 | if (clk->users) |
| 394 | return -EBUSY; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 395 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 396 | return -EINVAL; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 397 | |
| 398 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) |
| 399 | return -EINVAL; |
| 400 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 401 | spin_lock_irqsave(&clk_lock, flags); |
| 402 | |
| 403 | clk->rate_hz = parent->rate_hz; |
| 404 | clk->parent = parent; |
| 405 | at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); |
| 406 | |
| 407 | spin_unlock_irqrestore(&clk_lock, flags); |
| 408 | return 0; |
| 409 | } |
| 410 | EXPORT_SYMBOL(clk_set_parent); |
| 411 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 412 | /* establish PCK0..PCKN parentage and rate */ |
David Brownell | 72e7ae8 | 2008-02-06 22:03:42 +0100 | [diff] [blame] | 413 | static void __init init_programmable_clock(struct clk *clk) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 414 | { |
| 415 | struct clk *parent; |
| 416 | u32 pckr; |
| 417 | |
| 418 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
| 419 | parent = at91_css_to_clk(pckr & AT91_PMC_CSS); |
| 420 | clk->parent = parent; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 421 | clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2)); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 422 | } |
| 423 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 424 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
| 425 | |
| 426 | /*------------------------------------------------------------------------*/ |
| 427 | |
| 428 | #ifdef CONFIG_DEBUG_FS |
| 429 | |
| 430 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 431 | { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 432 | u32 scsr, pcsr, uckr = 0, sr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 433 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 434 | |
| 435 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); |
| 436 | seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 437 | seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); |
| 438 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); |
| 439 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 440 | if (cpu_has_pllb()) |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 441 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 442 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 443 | seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 444 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 445 | if (cpu_has_upll()) |
| 446 | seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 447 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); |
| 448 | |
| 449 | seq_printf(s, "\n"); |
| 450 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 451 | list_for_each_entry(clk, &clocks, node) { |
| 452 | char *state; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 453 | |
| 454 | if (clk->mode == pmc_sys_mode) |
| 455 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 456 | else if (clk->mode == pmc_periph_mode) |
| 457 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 458 | else if (clk->mode == pmc_uckr_mode) |
| 459 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 460 | else if (clk->pmc_mask) |
| 461 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 462 | else if (clk == &clk32k || clk == &main_clk) |
| 463 | state = "on"; |
| 464 | else |
| 465 | state = ""; |
| 466 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 467 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 468 | clk->name, clk->users, state, clk_get_rate(clk), |
| 469 | clk->parent ? clk->parent->name : ""); |
| 470 | } |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static int at91_clk_open(struct inode *inode, struct file *file) |
| 475 | { |
| 476 | return single_open(file, at91_clk_show, NULL); |
| 477 | } |
| 478 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 479 | static const struct file_operations at91_clk_operations = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 480 | .open = at91_clk_open, |
| 481 | .read = seq_read, |
| 482 | .llseek = seq_lseek, |
| 483 | .release = single_release, |
| 484 | }; |
| 485 | |
| 486 | static int __init at91_clk_debugfs_init(void) |
| 487 | { |
| 488 | /* /sys/kernel/debug/at91_clk */ |
| 489 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); |
| 490 | |
| 491 | return 0; |
| 492 | } |
| 493 | postcore_initcall(at91_clk_debugfs_init); |
| 494 | |
| 495 | #endif |
| 496 | |
| 497 | /*------------------------------------------------------------------------*/ |
| 498 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 499 | /* Register a new clock */ |
| 500 | int __init clk_register(struct clk *clk) |
| 501 | { |
| 502 | if (clk_is_peripheral(clk)) { |
| 503 | clk->parent = &mck; |
| 504 | clk->mode = pmc_periph_mode; |
| 505 | list_add_tail(&clk->node, &clocks); |
| 506 | } |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 507 | else if (clk_is_sys(clk)) { |
| 508 | clk->parent = &mck; |
| 509 | clk->mode = pmc_sys_mode; |
| 510 | |
| 511 | list_add_tail(&clk->node, &clocks); |
| 512 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 513 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 514 | else if (clk_is_programmable(clk)) { |
| 515 | clk->mode = pmc_sys_mode; |
| 516 | init_programmable_clock(clk); |
| 517 | list_add_tail(&clk->node, &clocks); |
| 518 | } |
| 519 | #endif |
| 520 | |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | |
| 525 | /*------------------------------------------------------------------------*/ |
| 526 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 527 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) |
| 528 | { |
| 529 | unsigned mul, div; |
| 530 | |
| 531 | div = reg & 0xff; |
| 532 | mul = (reg >> 16) & 0x7ff; |
| 533 | if (div && mul) { |
| 534 | freq /= div; |
| 535 | freq *= mul + 1; |
| 536 | } else |
| 537 | freq = 0; |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 538 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 539 | return freq; |
| 540 | } |
| 541 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 542 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
| 543 | { |
| 544 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) |
| 545 | return freq / 2; |
| 546 | else |
| 547 | return freq; |
| 548 | } |
| 549 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 550 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
| 551 | { |
| 552 | unsigned i, div = 0, mul = 0, diff = 1 << 30; |
| 553 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; |
| 554 | |
| 555 | /* PLL output max 240 MHz (or 180 MHz per errata) */ |
| 556 | if (out_freq > 240000000) |
| 557 | goto fail; |
| 558 | |
| 559 | for (i = 1; i < 256; i++) { |
| 560 | int diff1; |
| 561 | unsigned input, mul1; |
| 562 | |
| 563 | /* |
| 564 | * PLL input between 1MHz and 32MHz per spec, but lower |
| 565 | * frequences seem necessary in some cases so allow 100K. |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 566 | * Warning: some newer products need 2MHz min. |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 567 | */ |
| 568 | input = main_freq / i; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 569 | if (cpu_is_at91sam9g20() && input < 2000000) |
| 570 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 571 | if (input < 100000) |
| 572 | continue; |
| 573 | if (input > 32000000) |
| 574 | continue; |
| 575 | |
| 576 | mul1 = out_freq / input; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 577 | if (cpu_is_at91sam9g20() && mul > 63) |
| 578 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 579 | if (mul1 > 2048) |
| 580 | continue; |
| 581 | if (mul1 < 2) |
| 582 | goto fail; |
| 583 | |
| 584 | diff1 = out_freq - input * mul1; |
| 585 | if (diff1 < 0) |
| 586 | diff1 = -diff1; |
| 587 | if (diff > diff1) { |
| 588 | diff = diff1; |
| 589 | div = i; |
| 590 | mul = mul1; |
| 591 | if (diff == 0) |
| 592 | break; |
| 593 | } |
| 594 | } |
| 595 | if (i == 256 && diff > (out_freq >> 5)) |
| 596 | goto fail; |
| 597 | return ret | ((mul - 1) << 16) | div; |
| 598 | fail: |
| 599 | return 0; |
| 600 | } |
| 601 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 602 | static struct clk *const standard_pmc_clocks[] __initdata = { |
| 603 | /* four primary clocks */ |
| 604 | &clk32k, |
| 605 | &main_clk, |
| 606 | &plla, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 607 | |
| 608 | /* MCK */ |
| 609 | &mck |
| 610 | }; |
| 611 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 612 | /* PLLB generated USB full speed clock init */ |
| 613 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) |
| 614 | { |
| 615 | /* |
| 616 | * USB clock init: choose 48 MHz PLLB value, |
| 617 | * disable 48MHz clock during usb peripheral suspend. |
| 618 | * |
| 619 | * REVISIT: assumes MCK doesn't derive from PLLB! |
| 620 | */ |
| 621 | uhpck.parent = &pllb; |
| 622 | |
| 623 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; |
| 624 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); |
| 625 | if (cpu_is_at91rm9200()) { |
| 626 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 627 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
| 628 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 629 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
| 630 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || |
| 631 | cpu_is_at91sam9g10()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 632 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 633 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
| 634 | } else if (cpu_is_at91cap9()) { |
| 635 | uhpck.pmc_mask = AT91CAP9_PMC_UHP; |
| 636 | } |
| 637 | at91_sys_write(AT91_CKGR_PLLBR, 0); |
| 638 | |
| 639 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 640 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 641 | } |
| 642 | |
| 643 | /* UPLL generated USB full speed clock init */ |
| 644 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) |
| 645 | { |
| 646 | /* |
| 647 | * USB clock init: choose 480 MHz from UPLL, |
| 648 | */ |
| 649 | unsigned int usbr = AT91_PMC_USBS_UPLL; |
| 650 | |
| 651 | /* Setup divider by 10 to reach 48 MHz */ |
| 652 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; |
| 653 | |
| 654 | at91_sys_write(AT91_PMC_USB, usbr); |
| 655 | |
| 656 | /* Now set uhpck values */ |
| 657 | uhpck.parent = &utmi_clk; |
| 658 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 659 | uhpck.rate_hz = utmi_clk.parent->rate_hz; |
| 660 | uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
| 661 | } |
| 662 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 663 | int __init at91_clock_init(unsigned long main_clock) |
| 664 | { |
| 665 | unsigned tmp, freq, mckr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 666 | int i; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 667 | int pll_overclock = false; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 668 | |
| 669 | /* |
| 670 | * When the bootloader initialized the main oscillator correctly, |
| 671 | * there's no problem using the cycle counter. But if it didn't, |
| 672 | * or when using oscillator bypass mode, we must be told the speed |
| 673 | * of the main clock. |
| 674 | */ |
| 675 | if (!main_clock) { |
| 676 | do { |
| 677 | tmp = at91_sys_read(AT91_CKGR_MCFR); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 678 | } while (!(tmp & AT91_PMC_MAINRDY)); |
| 679 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 680 | } |
| 681 | main_clk.rate_hz = main_clock; |
| 682 | |
| 683 | /* report if PLLA is more than mildly overclocked */ |
| 684 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 685 | if (cpu_has_300M_plla()) { |
| 686 | if (plla.rate_hz > 300000000) |
| 687 | pll_overclock = true; |
| 688 | } else if (cpu_has_800M_plla()) { |
| 689 | if (plla.rate_hz > 800000000) |
| 690 | pll_overclock = true; |
| 691 | } else { |
| 692 | if (plla.rate_hz > 209000000) |
| 693 | pll_overclock = true; |
| 694 | } |
| 695 | if (pll_overclock) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 696 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 697 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 698 | if (cpu_is_at91sam9g45()) { |
| 699 | mckr = at91_sys_read(AT91_PMC_MCKR); |
| 700 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ |
| 701 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 702 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 703 | if (!cpu_has_pllb() && cpu_has_upll()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 704 | /* setup UTMI clock as the fourth primary clock |
| 705 | * (instead of pllb) */ |
| 706 | utmi_clk.type |= CLK_TYPE_PRIMARY; |
| 707 | utmi_clk.id = 3; |
| 708 | } |
| 709 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 710 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 711 | /* |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 712 | * USB HS clock init |
| 713 | */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 714 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 715 | /* |
| 716 | * multiplier is hard-wired to 40 |
| 717 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
| 718 | */ |
| 719 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 720 | |
| 721 | /* |
| 722 | * USB FS clock init |
| 723 | */ |
| 724 | if (cpu_has_pllb()) |
| 725 | at91_pllb_usbfs_clock_init(main_clock); |
| 726 | if (cpu_has_upll()) |
| 727 | /* assumes that we choose UPLL for USB and not PLLA */ |
| 728 | at91_upll_usbfs_clock_init(main_clock); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 729 | |
| 730 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 731 | * MCK and CPU derive from one of those primary clocks. |
| 732 | * For now, assume this parentage won't change. |
| 733 | */ |
| 734 | mckr = at91_sys_read(AT91_PMC_MCKR); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 735 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 736 | freq = mck.parent->rate_hz; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 737 | freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 738 | if (cpu_is_at91rm9200()) { |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 739 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 740 | } else if (cpu_is_at91sam9g20()) { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 741 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
| 742 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 743 | if (mckr & AT91_PMC_PDIV) |
| 744 | freq /= 2; /* processor clock division */ |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 745 | } else if (cpu_is_at91sam9g45()) { |
| 746 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
| 747 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 748 | } else { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 749 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 750 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 751 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 752 | /* Register the PMC's standard clocks */ |
| 753 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
| 754 | list_add_tail(&standard_pmc_clocks[i]->node, &clocks); |
| 755 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 756 | if (cpu_has_pllb()) |
| 757 | list_add_tail(&pllb.node, &clocks); |
| 758 | |
| 759 | if (cpu_has_uhp()) |
| 760 | list_add_tail(&uhpck.node, &clocks); |
| 761 | |
| 762 | if (cpu_has_udpfs()) |
| 763 | list_add_tail(&udpck.node, &clocks); |
| 764 | |
| 765 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 766 | list_add_tail(&utmi_clk.node, &clocks); |
| 767 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 768 | /* MCK and CPU clock are "always on" */ |
| 769 | clk_enable(&mck); |
| 770 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 771 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
| 772 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, |
| 773 | (unsigned) main_clock / 1000000, |
| 774 | ((unsigned) main_clock % 1000000) / 1000); |
| 775 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 776 | return 0; |
| 777 | } |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 778 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 779 | /* |
| 780 | * Several unused clocks may be active. Turn them off. |
| 781 | */ |
| 782 | static int __init at91_clock_reset(void) |
| 783 | { |
| 784 | unsigned long pcdr = 0; |
| 785 | unsigned long scdr = 0; |
| 786 | struct clk *clk; |
| 787 | |
| 788 | list_for_each_entry(clk, &clocks, node) { |
| 789 | if (clk->users > 0) |
| 790 | continue; |
| 791 | |
| 792 | if (clk->mode == pmc_periph_mode) |
| 793 | pcdr |= clk->pmc_mask; |
| 794 | |
| 795 | if (clk->mode == pmc_sys_mode) |
| 796 | scdr |= clk->pmc_mask; |
| 797 | |
| 798 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 799 | } |
| 800 | |
| 801 | at91_sys_write(AT91_PMC_PCDR, pcdr); |
| 802 | at91_sys_write(AT91_PMC_SCDR, scdr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 803 | |
| 804 | return 0; |
| 805 | } |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 806 | late_initcall(at91_clock_reset); |