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Bryan Wu1394f032007-05-06 14:50:22 -07001/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6
7#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_
9
10#define MAX_BLACKFIN_DMA_CHANNEL 36
11
12#define CH_PPI0 0
13#define CH_PPI (CH_PPI0)
14#define CH_PPI1 1
15#define CH_SPORT0_RX 12
16#define CH_SPORT0_TX 13
17#define CH_SPORT1_RX 14
18#define CH_SPORT1_TX 15
19#define CH_SPI 16
20#define CH_UART_RX 17
21#define CH_UART_TX 18
22#define CH_MEM_STREAM0_DEST 24 /* TX */
23#define CH_MEM_STREAM0_SRC 25 /* RX */
24#define CH_MEM_STREAM1_DEST 26 /* TX */
25#define CH_MEM_STREAM1_SRC 27 /* RX */
26#define CH_MEM_STREAM2_DEST 28
27#define CH_MEM_STREAM2_SRC 29
Michael Hennerich92322da2008-05-17 15:59:11 +080028#define CH_MEM_STREAM3_DEST 30
29#define CH_MEM_STREAM3_SRC 31
Bryan Wu1394f032007-05-06 14:50:22 -070030#define CH_IMEM_STREAM0_DEST 32
31#define CH_IMEM_STREAM0_SRC 33
Michael Hennerich92322da2008-05-17 15:59:11 +080032#define CH_IMEM_STREAM1_DEST 34
33#define CH_IMEM_STREAM1_SRC 35
Bryan Wu1394f032007-05-06 14:50:22 -070034
Bryan Wu1394f032007-05-06 14:50:22 -070035#endif