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Stephen Streete0c99052006-03-07 23:53:24 -08001/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
Mika Westerberga0d26422013-01-22 12:26:32 +02003 * Copyright (C) 2013, Intel Corporation
Stephen Streete0c99052006-03-07 23:53:24 -08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stephen Streete0c99052006-03-07 23:53:24 -080014 */
15
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020016#include <linux/bitops.h>
Stephen Streete0c99052006-03-07 23:53:24 -080017#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
Sachin Kamatcbfd6a22013-04-08 15:49:33 +053022#include <linux/err.h>
Stephen Streete0c99052006-03-07 23:53:24 -080023#include <linux/interrupt.h>
Andy Shevchenko9df461e2015-03-25 15:06:16 +020024#include <linux/kernel.h>
Jarkko Nikula34cadd92015-07-30 16:30:07 +030025#include <linux/pci.h>
Stephen Streete0c99052006-03-07 23:53:24 -080026#include <linux/platform_device.h>
Sebastian Andrzej Siewior8348c252010-11-22 17:12:15 -080027#include <linux/spi/pxa2xx_spi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080028#include <linux/spi/spi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080029#include <linux/delay.h>
Eric Miaoa7bb3902009-04-06 19:00:54 -070030#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Mika Westerberg3343b7a2013-01-22 12:26:27 +020032#include <linux/clk.h>
Mika Westerberg7d94a502013-01-22 12:26:30 +020033#include <linux/pm_runtime.h>
Mika Westerberga3496852013-01-22 12:26:33 +020034#include <linux/acpi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080035
Mika Westerbergcd7bed02013-01-22 12:26:28 +020036#include "spi-pxa2xx.h"
Stephen Streete0c99052006-03-07 23:53:24 -080037
38MODULE_AUTHOR("Stephen Street");
Will Newton037cdaf2007-12-10 15:49:25 -080039MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
Stephen Streete0c99052006-03-07 23:53:24 -080040MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -070041MODULE_ALIAS("platform:pxa2xx-spi");
Stephen Streete0c99052006-03-07 23:53:24 -080042
Vernon Sauderf1f640a2008-10-15 22:02:43 -070043#define TIMOUT_DFLT 1000
44
Ned Forresterb97c74b2008-02-23 15:23:40 -080045/*
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
51 */
52#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
Stephen Street8d94cc52006-12-10 02:18:54 -080053 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
Ned Forresterb97c74b2008-02-23 15:23:40 -080054 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
Stephen Street8d94cc52006-12-10 02:18:54 -080058
Weike Chene5262d02014-11-26 02:35:10 -080059#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
Jarkko Nikula624ea722015-10-28 15:13:39 +020065#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66#define LPSS_CS_CONTROL_SW_MODE BIT(0)
67#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
Jarkko Nikulad0283eb2015-10-28 15:13:40 +020068#define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
69#define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020070#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
Mika Westerberga0d26422013-01-22 12:26:32 +020072
Jarkko Nikuladccf7362015-06-04 16:55:11 +030073struct lpss_config {
74 /* LPSS offset from drv_data->ioaddr */
75 unsigned offset;
76 /* Register offsets from drv_data->lpss_base or -1 */
77 int reg_general;
78 int reg_ssp;
79 int reg_cs_ctrl;
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020080 int reg_capabilities;
Jarkko Nikuladccf7362015-06-04 16:55:11 +030081 /* FIFO thresholds */
82 u32 rx_threshold;
83 u32 tx_threshold_lo;
84 u32 tx_threshold_hi;
85};
86
87/* Keep these sorted with enum pxa_ssp_type */
88static const struct lpss_config lpss_platforms[] = {
89 { /* LPSS_LPT_SSP */
90 .offset = 0x800,
91 .reg_general = 0x08,
92 .reg_ssp = 0x0c,
93 .reg_cs_ctrl = 0x18,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020094 .reg_capabilities = -1,
Jarkko Nikuladccf7362015-06-04 16:55:11 +030095 .rx_threshold = 64,
96 .tx_threshold_lo = 160,
97 .tx_threshold_hi = 224,
98 },
99 { /* LPSS_BYT_SSP */
100 .offset = 0x400,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +0200104 .reg_capabilities = -1,
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300109 { /* LPSS_SPT_SSP */
110 .offset = 0x200,
111 .reg_general = -1,
112 .reg_ssp = 0x20,
113 .reg_cs_ctrl = 0x24,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +0200114 .reg_capabilities = 0xfc,
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300115 .rx_threshold = 1,
116 .tx_threshold_lo = 32,
117 .tx_threshold_hi = 56,
118 },
Jarkko Nikulab7c08cf2015-10-28 15:13:42 +0200119 { /* LPSS_BXT_SSP */
120 .offset = 0x200,
121 .reg_general = -1,
122 .reg_ssp = 0x20,
123 .reg_cs_ctrl = 0x24,
124 .reg_capabilities = 0xfc,
125 .rx_threshold = 1,
126 .tx_threshold_lo = 16,
127 .tx_threshold_hi = 48,
128 },
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300129};
130
131static inline const struct lpss_config
132*lpss_get_config(const struct driver_data *drv_data)
133{
134 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
135}
136
Mika Westerberga0d26422013-01-22 12:26:32 +0200137static bool is_lpss_ssp(const struct driver_data *drv_data)
138{
Jarkko Nikula03fbf482015-06-04 16:55:10 +0300139 switch (drv_data->ssp_type) {
140 case LPSS_LPT_SSP:
141 case LPSS_BYT_SSP:
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300142 case LPSS_SPT_SSP:
Jarkko Nikulab7c08cf2015-10-28 15:13:42 +0200143 case LPSS_BXT_SSP:
Jarkko Nikula03fbf482015-06-04 16:55:10 +0300144 return true;
145 default:
146 return false;
147 }
Mika Westerberga0d26422013-01-22 12:26:32 +0200148}
149
Weike Chene5262d02014-11-26 02:35:10 -0800150static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
151{
152 return drv_data->ssp_type == QUARK_X1000_SSP;
153}
154
Weike Chen4fdb2422014-10-08 08:50:22 -0700155static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
156{
157 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800158 case QUARK_X1000_SSP:
159 return QUARK_X1000_SSCR1_CHANGE_MASK;
Weike Chen4fdb2422014-10-08 08:50:22 -0700160 default:
161 return SSCR1_CHANGE_MASK;
162 }
163}
164
165static u32
166pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
167{
168 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800169 case QUARK_X1000_SSP:
170 return RX_THRESH_QUARK_X1000_DFLT;
Weike Chen4fdb2422014-10-08 08:50:22 -0700171 default:
172 return RX_THRESH_DFLT;
173 }
174}
175
176static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
177{
Weike Chen4fdb2422014-10-08 08:50:22 -0700178 u32 mask;
179
180 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800181 case QUARK_X1000_SSP:
182 mask = QUARK_X1000_SSSR_TFL_MASK;
183 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700184 default:
185 mask = SSSR_TFL_MASK;
186 break;
187 }
188
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200189 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
Weike Chen4fdb2422014-10-08 08:50:22 -0700190}
191
192static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
193 u32 *sccr1_reg)
194{
195 u32 mask;
196
197 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800198 case QUARK_X1000_SSP:
199 mask = QUARK_X1000_SSCR1_RFT;
200 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700201 default:
202 mask = SSCR1_RFT;
203 break;
204 }
205 *sccr1_reg &= ~mask;
206}
207
208static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
209 u32 *sccr1_reg, u32 threshold)
210{
211 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800212 case QUARK_X1000_SSP:
213 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
214 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700215 default:
216 *sccr1_reg |= SSCR1_RxTresh(threshold);
217 break;
218 }
219}
220
221static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
222 u32 clk_div, u8 bits)
223{
224 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800225 case QUARK_X1000_SSP:
226 return clk_div
227 | QUARK_X1000_SSCR0_Motorola
228 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
229 | SSCR0_SSE;
Weike Chen4fdb2422014-10-08 08:50:22 -0700230 default:
231 return clk_div
232 | SSCR0_Motorola
233 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
234 | SSCR0_SSE
235 | (bits > 16 ? SSCR0_EDSS : 0);
236 }
237}
238
Mika Westerberga0d26422013-01-22 12:26:32 +0200239/*
240 * Read and write LPSS SSP private registers. Caller must first check that
241 * is_lpss_ssp() returns true before these can be called.
242 */
243static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
244{
245 WARN_ON(!drv_data->lpss_base);
246 return readl(drv_data->lpss_base + offset);
247}
248
249static void __lpss_ssp_write_priv(struct driver_data *drv_data,
250 unsigned offset, u32 value)
251{
252 WARN_ON(!drv_data->lpss_base);
253 writel(value, drv_data->lpss_base + offset);
254}
255
256/*
257 * lpss_ssp_setup - perform LPSS SSP specific setup
258 * @drv_data: pointer to the driver private data
259 *
260 * Perform LPSS SSP specific setup. This function must be called first if
261 * one is going to use LPSS SSP private registers.
262 */
263static void lpss_ssp_setup(struct driver_data *drv_data)
264{
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300265 const struct lpss_config *config;
266 u32 value;
Mika Westerberga0d26422013-01-22 12:26:32 +0200267
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300268 config = lpss_get_config(drv_data);
269 drv_data->lpss_base = drv_data->ioaddr + config->offset;
Mika Westerberga0d26422013-01-22 12:26:32 +0200270
271 /* Enable software chip select control */
Jarkko Nikula0e897212015-10-22 16:44:42 +0300272 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
Jarkko Nikula624ea722015-10-28 15:13:39 +0200273 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
274 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300275 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
Mika Westerberg0054e282013-03-05 12:05:17 +0200276
277 /* Enable multiblock DMA transfers */
Mika Westerberg1de70612013-07-03 13:25:06 +0300278 if (drv_data->master_info->enable_dma) {
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300279 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
Mika Westerberg1de70612013-07-03 13:25:06 +0300280
Jarkko Nikula82ba2c22015-06-04 16:55:12 +0300281 if (config->reg_general >= 0) {
282 value = __lpss_ssp_read_priv(drv_data,
283 config->reg_general);
Jarkko Nikula624ea722015-10-28 15:13:39 +0200284 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
Jarkko Nikula82ba2c22015-06-04 16:55:12 +0300285 __lpss_ssp_write_priv(drv_data,
286 config->reg_general, value);
287 }
Mika Westerberg1de70612013-07-03 13:25:06 +0300288 }
Mika Westerberga0d26422013-01-22 12:26:32 +0200289}
290
291static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
292{
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300293 const struct lpss_config *config;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200294 u32 value, cs;
Mika Westerberga0d26422013-01-22 12:26:32 +0200295
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300296 config = lpss_get_config(drv_data);
297
298 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200299 if (enable) {
300 cs = drv_data->cur_msg->spi->chip_select;
301 cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT;
302 if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) {
303 /*
304 * When switching another chip select output active
305 * the output must be selected first and wait 2 ssp_clk
306 * cycles before changing state to active. Otherwise
307 * a short glitch will occur on the previous chip
308 * select since output select is latched but state
309 * control is not.
310 */
311 value &= ~LPSS_CS_CONTROL_CS_SEL_MASK;
312 value |= cs;
313 __lpss_ssp_write_priv(drv_data,
314 config->reg_cs_ctrl, value);
315 ndelay(1000000000 /
316 (drv_data->master->max_speed_hz / 2));
317 }
Jarkko Nikula624ea722015-10-28 15:13:39 +0200318 value &= ~LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200319 } else {
Jarkko Nikula624ea722015-10-28 15:13:39 +0200320 value |= LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200321 }
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300322 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
Mika Westerberga0d26422013-01-22 12:26:32 +0200323}
324
Eric Miaoa7bb3902009-04-06 19:00:54 -0700325static void cs_assert(struct driver_data *drv_data)
326{
327 struct chip_data *chip = drv_data->cur_chip;
328
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800329 if (drv_data->ssp_type == CE4100_SSP) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200330 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800331 return;
332 }
333
Eric Miaoa7bb3902009-04-06 19:00:54 -0700334 if (chip->cs_control) {
335 chip->cs_control(PXA2XX_CS_ASSERT);
336 return;
337 }
338
Mika Westerberga0d26422013-01-22 12:26:32 +0200339 if (gpio_is_valid(chip->gpio_cs)) {
Eric Miaoa7bb3902009-04-06 19:00:54 -0700340 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
Mika Westerberga0d26422013-01-22 12:26:32 +0200341 return;
342 }
343
Jarkko Nikula7566bcc2014-12-18 15:04:20 +0200344 if (is_lpss_ssp(drv_data))
345 lpss_ssp_cs_control(drv_data, true);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700346}
347
348static void cs_deassert(struct driver_data *drv_data)
349{
350 struct chip_data *chip = drv_data->cur_chip;
351
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800352 if (drv_data->ssp_type == CE4100_SSP)
353 return;
354
Eric Miaoa7bb3902009-04-06 19:00:54 -0700355 if (chip->cs_control) {
Daniel Ribeiro2b2562d2009-04-08 22:48:03 -0300356 chip->cs_control(PXA2XX_CS_DEASSERT);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700357 return;
358 }
359
Mika Westerberga0d26422013-01-22 12:26:32 +0200360 if (gpio_is_valid(chip->gpio_cs)) {
Eric Miaoa7bb3902009-04-06 19:00:54 -0700361 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
Mika Westerberga0d26422013-01-22 12:26:32 +0200362 return;
363 }
364
Jarkko Nikula7566bcc2014-12-18 15:04:20 +0200365 if (is_lpss_ssp(drv_data))
366 lpss_ssp_cs_control(drv_data, false);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700367}
368
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200369int pxa2xx_spi_flush(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800370{
371 unsigned long limit = loops_per_jiffy << 1;
372
Stephen Streete0c99052006-03-07 23:53:24 -0800373 do {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200374 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
375 pxa2xx_spi_read(drv_data, SSDR);
376 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800377 write_SSSR_CS(drv_data, SSSR_ROR);
Stephen Streete0c99052006-03-07 23:53:24 -0800378
379 return limit;
380}
381
Stephen Street8d94cc52006-12-10 02:18:54 -0800382static int null_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800383{
Stephen Street9708c122006-03-28 14:05:23 -0800384 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800385
Weike Chen4fdb2422014-10-08 08:50:22 -0700386 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800387 || (drv_data->tx == drv_data->tx_end))
388 return 0;
389
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200390 pxa2xx_spi_write(drv_data, SSDR, 0);
Stephen Street8d94cc52006-12-10 02:18:54 -0800391 drv_data->tx += n_bytes;
392
393 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800394}
395
Stephen Street8d94cc52006-12-10 02:18:54 -0800396static int null_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800397{
Stephen Street9708c122006-03-28 14:05:23 -0800398 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800399
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200400 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
401 && (drv_data->rx < drv_data->rx_end)) {
402 pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800403 drv_data->rx += n_bytes;
404 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800405
406 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800407}
408
Stephen Street8d94cc52006-12-10 02:18:54 -0800409static int u8_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800410{
Weike Chen4fdb2422014-10-08 08:50:22 -0700411 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800412 || (drv_data->tx == drv_data->tx_end))
413 return 0;
414
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200415 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800416 ++drv_data->tx;
417
418 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800419}
420
Stephen Street8d94cc52006-12-10 02:18:54 -0800421static int u8_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800422{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200423 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
424 && (drv_data->rx < drv_data->rx_end)) {
425 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800426 ++drv_data->rx;
427 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800428
429 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800430}
431
Stephen Street8d94cc52006-12-10 02:18:54 -0800432static int u16_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800433{
Weike Chen4fdb2422014-10-08 08:50:22 -0700434 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800435 || (drv_data->tx == drv_data->tx_end))
436 return 0;
437
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200438 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800439 drv_data->tx += 2;
440
441 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800442}
443
Stephen Street8d94cc52006-12-10 02:18:54 -0800444static int u16_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800445{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200446 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
447 && (drv_data->rx < drv_data->rx_end)) {
448 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800449 drv_data->rx += 2;
450 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800451
452 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800453}
Stephen Street8d94cc52006-12-10 02:18:54 -0800454
455static int u32_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800456{
Weike Chen4fdb2422014-10-08 08:50:22 -0700457 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800458 || (drv_data->tx == drv_data->tx_end))
459 return 0;
460
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200461 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800462 drv_data->tx += 4;
463
464 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800465}
466
Stephen Street8d94cc52006-12-10 02:18:54 -0800467static int u32_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800468{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200469 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
470 && (drv_data->rx < drv_data->rx_end)) {
471 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800472 drv_data->rx += 4;
473 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800474
475 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800476}
477
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200478void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800479{
480 struct spi_message *msg = drv_data->cur_msg;
481 struct spi_transfer *trans = drv_data->cur_transfer;
482
483 /* Move to next transfer */
484 if (trans->transfer_list.next != &msg->transfers) {
485 drv_data->cur_transfer =
486 list_entry(trans->transfer_list.next,
487 struct spi_transfer,
488 transfer_list);
489 return RUNNING_STATE;
490 } else
491 return DONE_STATE;
492}
493
Stephen Streete0c99052006-03-07 23:53:24 -0800494/* caller already set message->status; dma and pio irqs are blocked */
Stephen Street5daa3ba2006-05-20 15:00:19 -0700495static void giveback(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800496{
497 struct spi_transfer* last_transfer;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700498 struct spi_message *msg;
Stephen Streete0c99052006-03-07 23:53:24 -0800499
Stephen Street5daa3ba2006-05-20 15:00:19 -0700500 msg = drv_data->cur_msg;
501 drv_data->cur_msg = NULL;
502 drv_data->cur_transfer = NULL;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700503
Axel Lin23e2c2a2014-02-12 22:13:27 +0800504 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
Stephen Streete0c99052006-03-07 23:53:24 -0800505 transfer_list);
506
Ned Forrester84235972008-09-13 02:33:17 -0700507 /* Delay if requested before any change in chip select */
508 if (last_transfer->delay_usecs)
509 udelay(last_transfer->delay_usecs);
510
511 /* Drop chip select UNLESS cs_change is true or we are returning
512 * a message with an error, or next message is for another chip
513 */
Stephen Streete0c99052006-03-07 23:53:24 -0800514 if (!last_transfer->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700515 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700516 else {
517 struct spi_message *next_msg;
518
519 /* Holding of cs was hinted, but we need to make sure
520 * the next message is for the same chip. Don't waste
521 * time with the following tests unless this was hinted.
522 *
523 * We cannot postpone this until pump_messages, because
524 * after calling msg->complete (below) the driver that
525 * sent the current message could be unloaded, which
526 * could invalidate the cs_control() callback...
527 */
528
529 /* get a pointer to the next message, if any */
Mika Westerberg7f86bde2013-01-22 12:26:26 +0200530 next_msg = spi_get_next_queued_message(drv_data->master);
Ned Forrester84235972008-09-13 02:33:17 -0700531
532 /* see if the next and current messages point
533 * to the same chip
534 */
535 if (next_msg && next_msg->spi != msg->spi)
536 next_msg = NULL;
537 if (!next_msg || msg->state == ERROR_STATE)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700538 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700539 }
Stephen Streete0c99052006-03-07 23:53:24 -0800540
Eric Miaoa7bb3902009-04-06 19:00:54 -0700541 drv_data->cur_chip = NULL;
Mika Westerbergc957e8f2014-12-29 10:33:36 +0200542 spi_finalize_current_message(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -0800543}
544
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800545static void reset_sccr1(struct driver_data *drv_data)
546{
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800547 struct chip_data *chip = drv_data->cur_chip;
548 u32 sccr1_reg;
549
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200550 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800551 sccr1_reg &= ~SSCR1_RFT;
552 sccr1_reg |= chip->threshold;
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200553 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800554}
555
Stephen Street8d94cc52006-12-10 02:18:54 -0800556static void int_error_stop(struct driver_data *drv_data, const char* msg)
557{
Stephen Street8d94cc52006-12-10 02:18:54 -0800558 /* Stop and reset SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800559 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800560 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800561 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200562 pxa2xx_spi_write(drv_data, SSTO, 0);
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200563 pxa2xx_spi_flush(drv_data);
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200564 pxa2xx_spi_write(drv_data, SSCR0,
565 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
Stephen Street8d94cc52006-12-10 02:18:54 -0800566
567 dev_err(&drv_data->pdev->dev, "%s\n", msg);
568
569 drv_data->cur_msg->state = ERROR_STATE;
570 tasklet_schedule(&drv_data->pump_transfers);
571}
572
573static void int_transfer_complete(struct driver_data *drv_data)
574{
Stephen Street8d94cc52006-12-10 02:18:54 -0800575 /* Stop SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800576 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800577 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800578 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200579 pxa2xx_spi_write(drv_data, SSTO, 0);
Stephen Street8d94cc52006-12-10 02:18:54 -0800580
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300581 /* Update total byte transferred return count actual bytes read */
Stephen Street8d94cc52006-12-10 02:18:54 -0800582 drv_data->cur_msg->actual_length += drv_data->len -
583 (drv_data->rx_end - drv_data->rx);
584
Ned Forrester84235972008-09-13 02:33:17 -0700585 /* Transfer delays and chip select release are
586 * handled in pump_transfers or giveback
587 */
Stephen Street8d94cc52006-12-10 02:18:54 -0800588
589 /* Move to next transfer */
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200590 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
Stephen Street8d94cc52006-12-10 02:18:54 -0800591
592 /* Schedule transfer tasklet */
593 tasklet_schedule(&drv_data->pump_transfers);
594}
595
Stephen Streete0c99052006-03-07 23:53:24 -0800596static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
597{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200598 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
599 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
Stephen Street8d94cc52006-12-10 02:18:54 -0800600
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200601 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
Stephen Streete0c99052006-03-07 23:53:24 -0800602
Stephen Street8d94cc52006-12-10 02:18:54 -0800603 if (irq_status & SSSR_ROR) {
604 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
605 return IRQ_HANDLED;
606 }
Stephen Streete0c99052006-03-07 23:53:24 -0800607
Stephen Street8d94cc52006-12-10 02:18:54 -0800608 if (irq_status & SSSR_TINT) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200609 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
Stephen Street8d94cc52006-12-10 02:18:54 -0800610 if (drv_data->read(drv_data)) {
611 int_transfer_complete(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800612 return IRQ_HANDLED;
613 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800614 }
Stephen Streete0c99052006-03-07 23:53:24 -0800615
Stephen Street8d94cc52006-12-10 02:18:54 -0800616 /* Drain rx fifo, Fill tx fifo and prevent overruns */
617 do {
618 if (drv_data->read(drv_data)) {
619 int_transfer_complete(drv_data);
620 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800621 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800622 } while (drv_data->write(drv_data));
Stephen Streete0c99052006-03-07 23:53:24 -0800623
Stephen Street8d94cc52006-12-10 02:18:54 -0800624 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data);
626 return IRQ_HANDLED;
627 }
Stephen Streete0c99052006-03-07 23:53:24 -0800628
Stephen Street8d94cc52006-12-10 02:18:54 -0800629 if (drv_data->tx == drv_data->tx_end) {
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800630 u32 bytes_left;
631 u32 sccr1_reg;
632
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200633 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800634 sccr1_reg &= ~SSCR1_TIE;
635
636 /*
637 * PXA25x_SSP has no timeout, set up rx threshould for the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300638 * remaining RX bytes.
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800639 */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800640 if (pxa25x_ssp_comp(drv_data)) {
Weike Chen4fdb2422014-10-08 08:50:22 -0700641 u32 rx_thre;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800642
Weike Chen4fdb2422014-10-08 08:50:22 -0700643 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800644
645 bytes_left = drv_data->rx_end - drv_data->rx;
646 switch (drv_data->n_bytes) {
647 case 4:
648 bytes_left >>= 1;
649 case 2:
650 bytes_left >>= 1;
Stephen Street8d94cc52006-12-10 02:18:54 -0800651 }
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800652
Weike Chen4fdb2422014-10-08 08:50:22 -0700653 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
654 if (rx_thre > bytes_left)
655 rx_thre = bytes_left;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800656
Weike Chen4fdb2422014-10-08 08:50:22 -0700657 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
Stephen Streete0c99052006-03-07 23:53:24 -0800658 }
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200659 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
Stephen Streete0c99052006-03-07 23:53:24 -0800660 }
661
Stephen Street5daa3ba2006-05-20 15:00:19 -0700662 /* We did something */
663 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800664}
665
David Howells7d12e782006-10-05 14:55:46 +0100666static irqreturn_t ssp_int(int irq, void *dev_id)
Stephen Streete0c99052006-03-07 23:53:24 -0800667{
Jeff Garzikc7bec5a2006-10-06 15:00:58 -0400668 struct driver_data *drv_data = dev_id;
Mika Westerberg7d94a502013-01-22 12:26:30 +0200669 u32 sccr1_reg;
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800670 u32 mask = drv_data->mask_sr;
671 u32 status;
672
Mika Westerberg7d94a502013-01-22 12:26:30 +0200673 /*
674 * The IRQ might be shared with other peripherals so we must first
675 * check that are we RPM suspended or not. If we are we assume that
676 * the IRQ was not for us (we shouldn't be RPM suspended when the
677 * interrupt is enabled).
678 */
679 if (pm_runtime_suspended(&drv_data->pdev->dev))
680 return IRQ_NONE;
681
Mika Westerberg269e4a42013-09-04 13:37:43 +0300682 /*
683 * If the device is not yet in RPM suspended state and we get an
684 * interrupt that is meant for another device, check if status bits
685 * are all set to one. That means that the device is already
686 * powered off.
687 */
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200688 status = pxa2xx_spi_read(drv_data, SSSR);
Mika Westerberg269e4a42013-09-04 13:37:43 +0300689 if (status == ~0)
690 return IRQ_NONE;
691
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200692 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800693
694 /* Ignore possible writes if we don't need to write */
695 if (!(sccr1_reg & SSCR1_TIE))
696 mask &= ~SSSR_TFS;
697
Tan, Jui Nee02bc9332015-09-01 10:22:51 +0800698 /* Ignore RX timeout interrupt if it is disabled */
699 if (!(sccr1_reg & SSCR1_TINTE))
700 mask &= ~SSSR_TINT;
701
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800702 if (!(status & mask))
703 return IRQ_NONE;
Stephen Streete0c99052006-03-07 23:53:24 -0800704
705 if (!drv_data->cur_msg) {
Stephen Street5daa3ba2006-05-20 15:00:19 -0700706
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200707 pxa2xx_spi_write(drv_data, SSCR0,
708 pxa2xx_spi_read(drv_data, SSCR0)
709 & ~SSCR0_SSE);
710 pxa2xx_spi_write(drv_data, SSCR1,
711 pxa2xx_spi_read(drv_data, SSCR1)
712 & ~drv_data->int_cr1);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800713 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200714 pxa2xx_spi_write(drv_data, SSTO, 0);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800715 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street5daa3ba2006-05-20 15:00:19 -0700716
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300717 dev_err(&drv_data->pdev->dev,
718 "bad message state in interrupt handler\n");
Stephen Street5daa3ba2006-05-20 15:00:19 -0700719
Stephen Streete0c99052006-03-07 23:53:24 -0800720 /* Never fail */
721 return IRQ_HANDLED;
722 }
723
724 return drv_data->transfer_handler(drv_data);
725}
726
Weike Chene5262d02014-11-26 02:35:10 -0800727/*
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200728 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
729 * input frequency by fractions of 2^24. It also has a divider by 5.
730 *
731 * There are formulas to get baud rate value for given input frequency and
732 * divider parameters, such as DDS_CLK_RATE and SCR:
733 *
734 * Fsys = 200MHz
735 *
736 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
737 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
738 *
739 * DDS_CLK_RATE either 2^n or 2^n / 5.
740 * SCR is in range 0 .. 255
741 *
742 * Divisor = 5^i * 2^j * 2 * k
743 * i = [0, 1] i = 1 iff j = 0 or j > 3
744 * j = [0, 23] j = 0 iff i = 1
745 * k = [1, 256]
746 * Special case: j = 0, i = 1: Divisor = 2 / 5
747 *
748 * Accordingly to the specification the recommended values for DDS_CLK_RATE
749 * are:
750 * Case 1: 2^n, n = [0, 23]
751 * Case 2: 2^24 * 2 / 5 (0x666666)
752 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
753 *
754 * In all cases the lowest possible value is better.
755 *
756 * The function calculates parameters for all cases and chooses the one closest
757 * to the asked baud rate.
Weike Chene5262d02014-11-26 02:35:10 -0800758 */
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200759static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
Weike Chene5262d02014-11-26 02:35:10 -0800760{
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200761 unsigned long xtal = 200000000;
762 unsigned long fref = xtal / 2; /* mandatory division by 2,
763 see (2) */
764 /* case 3 */
765 unsigned long fref1 = fref / 2; /* case 1 */
766 unsigned long fref2 = fref * 2 / 5; /* case 2 */
767 unsigned long scale;
768 unsigned long q, q1, q2;
769 long r, r1, r2;
770 u32 mul;
Weike Chene5262d02014-11-26 02:35:10 -0800771
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200772 /* Case 1 */
773
774 /* Set initial value for DDS_CLK_RATE */
775 mul = (1 << 24) >> 1;
776
777 /* Calculate initial quot */
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300778 q1 = DIV_ROUND_UP(fref1, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200779
780 /* Scale q1 if it's too big */
781 if (q1 > 256) {
782 /* Scale q1 to range [1, 512] */
783 scale = fls_long(q1 - 1);
784 if (scale > 9) {
785 q1 >>= scale - 9;
786 mul >>= scale - 9;
787 }
788
789 /* Round the result if we have a remainder */
790 q1 += q1 & 1;
791 }
792
793 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
794 scale = __ffs(q1);
795 q1 >>= scale;
796 mul >>= scale;
797
798 /* Get the remainder */
799 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
800
801 /* Case 2 */
802
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300803 q2 = DIV_ROUND_UP(fref2, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200804 r2 = abs(fref2 / q2 - rate);
805
806 /*
807 * Choose the best between two: less remainder we have the better. We
808 * can't go case 2 if q2 is greater than 256 since SCR register can
809 * hold only values 0 .. 255.
810 */
811 if (r2 >= r1 || q2 > 256) {
812 /* case 1 is better */
813 r = r1;
814 q = q1;
815 } else {
816 /* case 2 is better */
817 r = r2;
818 q = q2;
819 mul = (1 << 24) * 2 / 5;
820 }
821
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300822 /* Check case 3 only if the divisor is big enough */
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200823 if (fref / rate >= 80) {
824 u64 fssp;
825 u32 m;
826
827 /* Calculate initial quot */
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300828 q1 = DIV_ROUND_UP(fref, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200829 m = (1 << 24) / q1;
830
831 /* Get the remainder */
832 fssp = (u64)fref * m;
833 do_div(fssp, 1 << 24);
834 r1 = abs(fssp - rate);
835
836 /* Choose this one if it suits better */
837 if (r1 < r) {
838 /* case 3 is better */
839 q = 1;
840 mul = m;
Weike Chene5262d02014-11-26 02:35:10 -0800841 }
842 }
843
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200844 *dds = mul;
845 return q - 1;
Weike Chene5262d02014-11-26 02:35:10 -0800846}
847
Mika Westerberg3343b7a2013-01-22 12:26:27 +0200848static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
eric miao2f1a74e2007-11-21 18:50:53 +0800849{
Jarkko Nikula0eca7cf2015-09-25 10:27:17 +0300850 unsigned long ssp_clk = drv_data->master->max_speed_hz;
Mika Westerberg3343b7a2013-01-22 12:26:27 +0200851 const struct ssp_device *ssp = drv_data->ssp;
852
853 rate = min_t(int, ssp_clk, rate);
eric miao2f1a74e2007-11-21 18:50:53 +0800854
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800855 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200856 return (ssp_clk / (2 * rate) - 1) & 0xff;
eric miao2f1a74e2007-11-21 18:50:53 +0800857 else
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200858 return (ssp_clk / rate - 1) & 0xfff;
eric miao2f1a74e2007-11-21 18:50:53 +0800859}
860
Weike Chene5262d02014-11-26 02:35:10 -0800861static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300862 int rate)
Weike Chene5262d02014-11-26 02:35:10 -0800863{
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300864 struct chip_data *chip = drv_data->cur_chip;
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200865 unsigned int clk_div;
Weike Chene5262d02014-11-26 02:35:10 -0800866
867 switch (drv_data->ssp_type) {
868 case QUARK_X1000_SSP:
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200869 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
Dan Carpentereecacf72015-03-31 16:49:38 +0300870 break;
Weike Chene5262d02014-11-26 02:35:10 -0800871 default:
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200872 clk_div = ssp_get_clk_div(drv_data, rate);
Dan Carpentereecacf72015-03-31 16:49:38 +0300873 break;
Weike Chene5262d02014-11-26 02:35:10 -0800874 }
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200875 return clk_div << 8;
Weike Chene5262d02014-11-26 02:35:10 -0800876}
877
Stephen Streete0c99052006-03-07 23:53:24 -0800878static void pump_transfers(unsigned long data)
879{
880 struct driver_data *drv_data = (struct driver_data *)data;
881 struct spi_message *message = NULL;
882 struct spi_transfer *transfer = NULL;
883 struct spi_transfer *previous = NULL;
884 struct chip_data *chip = NULL;
Stephen Street9708c122006-03-28 14:05:23 -0800885 u32 clk_div = 0;
886 u8 bits = 0;
887 u32 speed = 0;
888 u32 cr0;
Stephen Street8d94cc52006-12-10 02:18:54 -0800889 u32 cr1;
890 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
891 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
Weike Chen4fdb2422014-10-08 08:50:22 -0700892 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800893
894 /* Get current state information */
895 message = drv_data->cur_msg;
896 transfer = drv_data->cur_transfer;
897 chip = drv_data->cur_chip;
898
899 /* Handle for abort */
900 if (message->state == ERROR_STATE) {
901 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700902 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800903 return;
904 }
905
906 /* Handle end of message */
907 if (message->state == DONE_STATE) {
908 message->status = 0;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700909 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800910 return;
911 }
912
Ned Forrester84235972008-09-13 02:33:17 -0700913 /* Delay if requested at end of transfer before CS change */
Stephen Streete0c99052006-03-07 23:53:24 -0800914 if (message->state == RUNNING_STATE) {
915 previous = list_entry(transfer->transfer_list.prev,
916 struct spi_transfer,
917 transfer_list);
918 if (previous->delay_usecs)
919 udelay(previous->delay_usecs);
Ned Forrester84235972008-09-13 02:33:17 -0700920
921 /* Drop chip select only if cs_change is requested */
922 if (previous->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700923 cs_deassert(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800924 }
925
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200926 /* Check if we can DMA this transfer */
927 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
Ned Forrester7e964452008-09-13 02:33:18 -0700928
929 /* reject already-mapped transfers; PIO won't always work */
930 if (message->is_dma_mapped
931 || transfer->rx_dma || transfer->tx_dma) {
932 dev_err(&drv_data->pdev->dev,
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300933 "pump_transfers: mapped transfer length of "
934 "%u is greater than %d\n",
Ned Forrester7e964452008-09-13 02:33:18 -0700935 transfer->len, MAX_DMA_LEN);
936 message->status = -EINVAL;
937 giveback(drv_data);
938 return;
939 }
940
941 /* warn ... we force this to PIO mode */
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300942 dev_warn_ratelimited(&message->spi->dev,
943 "pump_transfers: DMA disabled for transfer length %ld "
944 "greater than %d\n",
945 (long)drv_data->len, MAX_DMA_LEN);
Stephen Street8d94cc52006-12-10 02:18:54 -0800946 }
947
Stephen Streete0c99052006-03-07 23:53:24 -0800948 /* Setup the transfer state based on the type of transfer */
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200949 if (pxa2xx_spi_flush(drv_data) == 0) {
Stephen Streete0c99052006-03-07 23:53:24 -0800950 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
951 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700952 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800953 return;
954 }
Stephen Street9708c122006-03-28 14:05:23 -0800955 drv_data->n_bytes = chip->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800956 drv_data->tx = (void *)transfer->tx_buf;
957 drv_data->tx_end = drv_data->tx + transfer->len;
958 drv_data->rx = transfer->rx_buf;
959 drv_data->rx_end = drv_data->rx + transfer->len;
960 drv_data->rx_dma = transfer->rx_dma;
961 drv_data->tx_dma = transfer->tx_dma;
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200962 drv_data->len = transfer->len;
Stephen Streete0c99052006-03-07 23:53:24 -0800963 drv_data->write = drv_data->tx ? chip->write : null_writer;
964 drv_data->read = drv_data->rx ? chip->read : null_reader;
Stephen Street9708c122006-03-28 14:05:23 -0800965
966 /* Change speed and bit per word on a per transfer */
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300967 bits = transfer->bits_per_word;
968 speed = transfer->speed_hz;
Stephen Street9708c122006-03-28 14:05:23 -0800969
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300970 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
Stephen Street9708c122006-03-28 14:05:23 -0800971
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300972 if (bits <= 8) {
973 drv_data->n_bytes = 1;
974 drv_data->read = drv_data->read != null_reader ?
975 u8_reader : null_reader;
976 drv_data->write = drv_data->write != null_writer ?
977 u8_writer : null_writer;
978 } else if (bits <= 16) {
979 drv_data->n_bytes = 2;
980 drv_data->read = drv_data->read != null_reader ?
981 u16_reader : null_reader;
982 drv_data->write = drv_data->write != null_writer ?
983 u16_writer : null_writer;
984 } else if (bits <= 32) {
985 drv_data->n_bytes = 4;
986 drv_data->read = drv_data->read != null_reader ?
987 u32_reader : null_reader;
988 drv_data->write = drv_data->write != null_writer ?
989 u32_writer : null_writer;
Stephen Street9708c122006-03-28 14:05:23 -0800990 }
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300991 /*
992 * if bits/word is changed in dma mode, then must check the
993 * thresholds and burst also
994 */
995 if (chip->enable_dma) {
996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
997 message->spi,
998 bits, &dma_burst,
999 &dma_thresh))
1000 dev_warn_ratelimited(&message->spi->dev,
1001 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1002 }
1003
Andy Shevchenkod74c4b12015-10-22 16:44:39 +03001004 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
Jarkko Nikula196b0e22015-09-15 16:26:27 +03001005 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
Andy Shevchenkod74c4b12015-10-22 16:44:39 +03001006 if (!pxa25x_ssp_comp(drv_data))
1007 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1008 drv_data->master->max_speed_hz
1009 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1010 chip->enable_dma ? "DMA" : "PIO");
1011 else
1012 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1013 drv_data->master->max_speed_hz / 2
1014 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1015 chip->enable_dma ? "DMA" : "PIO");
Stephen Street9708c122006-03-28 14:05:23 -08001016
Stephen Streete0c99052006-03-07 23:53:24 -08001017 message->state = RUNNING_STATE;
1018
Ned Forrester7e964452008-09-13 02:33:18 -07001019 drv_data->dma_mapped = 0;
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001020 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1021 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
Ned Forrester7e964452008-09-13 02:33:18 -07001022 if (drv_data->dma_mapped) {
Stephen Streete0c99052006-03-07 23:53:24 -08001023
1024 /* Ensure we have the correct interrupt handler */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001025 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
Stephen Streete0c99052006-03-07 23:53:24 -08001026
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001027 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
Stephen Streete0c99052006-03-07 23:53:24 -08001028
Stephen Street8d94cc52006-12-10 02:18:54 -08001029 /* Clear status and start DMA engine */
1030 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001031 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001032
1033 pxa2xx_spi_dma_start(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001034 } else {
1035 /* Ensure we have the correct interrupt handler */
1036 drv_data->transfer_handler = interrupt_transfer;
1037
Stephen Street8d94cc52006-12-10 02:18:54 -08001038 /* Clear status */
1039 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001040 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street8d94cc52006-12-10 02:18:54 -08001041 }
1042
Mika Westerberga0d26422013-01-22 12:26:32 +02001043 if (is_lpss_ssp(drv_data)) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045 != chip->lpss_rx_threshold)
1046 pxa2xx_spi_write(drv_data, SSIRF,
1047 chip->lpss_rx_threshold);
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049 != chip->lpss_tx_threshold)
1050 pxa2xx_spi_write(drv_data, SSITF,
1051 chip->lpss_tx_threshold);
Mika Westerberga0d26422013-01-22 12:26:32 +02001052 }
1053
Weike Chene5262d02014-11-26 02:35:10 -08001054 if (is_quark_x1000_ssp(drv_data) &&
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001055 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1056 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
Weike Chene5262d02014-11-26 02:35:10 -08001057
Stephen Street8d94cc52006-12-10 02:18:54 -08001058 /* see if we need to reload the config registers */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1060 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1061 != (cr1 & change_mask)) {
Ned Forresterb97c74b2008-02-23 15:23:40 -08001062 /* stop the SSP, and update the other bits */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001063 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001064 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001065 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001066 /* first set CR1 without interrupt and service enables */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001067 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001068 /* restart the SSP */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001069 pxa2xx_spi_write(drv_data, SSCR0, cr0);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001070
Stephen Street8d94cc52006-12-10 02:18:54 -08001071 } else {
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001072 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001073 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
Stephen Streete0c99052006-03-07 23:53:24 -08001074 }
Ned Forresterb97c74b2008-02-23 15:23:40 -08001075
Eric Miaoa7bb3902009-04-06 19:00:54 -07001076 cs_assert(drv_data);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001077
1078 /* after chip select, release the data by enabling service
1079 * requests and interrupts, without changing any mode bits */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001080 pxa2xx_spi_write(drv_data, SSCR1, cr1);
Stephen Streete0c99052006-03-07 23:53:24 -08001081}
1082
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001083static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1084 struct spi_message *msg)
Stephen Streete0c99052006-03-07 23:53:24 -08001085{
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001086 struct driver_data *drv_data = spi_master_get_devdata(master);
Stephen Streete0c99052006-03-07 23:53:24 -08001087
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001088 drv_data->cur_msg = msg;
Stephen Streete0c99052006-03-07 23:53:24 -08001089 /* Initial message state*/
1090 drv_data->cur_msg->state = START_STATE;
1091 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1092 struct spi_transfer,
1093 transfer_list);
1094
Stephen Street8d94cc52006-12-10 02:18:54 -08001095 /* prepare to setup the SSP, in pump_transfers, using the per
1096 * chip configuration */
Stephen Streete0c99052006-03-07 23:53:24 -08001097 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Stephen Streete0c99052006-03-07 23:53:24 -08001098
1099 /* Mark as busy and launch transfers */
1100 tasklet_schedule(&drv_data->pump_transfers);
Stephen Streete0c99052006-03-07 23:53:24 -08001101 return 0;
1102}
1103
Mika Westerberg7d94a502013-01-22 12:26:30 +02001104static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1105{
1106 struct driver_data *drv_data = spi_master_get_devdata(master);
1107
1108 /* Disable the SSP now */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001109 pxa2xx_spi_write(drv_data, SSCR0,
1110 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
Mika Westerberg7d94a502013-01-22 12:26:30 +02001111
Mika Westerberg7d94a502013-01-22 12:26:30 +02001112 return 0;
1113}
1114
Eric Miaoa7bb3902009-04-06 19:00:54 -07001115static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1116 struct pxa2xx_spi_chip *chip_info)
1117{
1118 int err = 0;
1119
1120 if (chip == NULL || chip_info == NULL)
1121 return 0;
1122
1123 /* NOTE: setup() can be called multiple times, possibly with
1124 * different chip_info, release previously requested GPIO
1125 */
1126 if (gpio_is_valid(chip->gpio_cs))
1127 gpio_free(chip->gpio_cs);
1128
1129 /* If (*cs_control) is provided, ignore GPIO chip select */
1130 if (chip_info->cs_control) {
1131 chip->cs_control = chip_info->cs_control;
1132 return 0;
1133 }
1134
1135 if (gpio_is_valid(chip_info->gpio_cs)) {
1136 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1137 if (err) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001138 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1139 chip_info->gpio_cs);
Eric Miaoa7bb3902009-04-06 19:00:54 -07001140 return err;
1141 }
1142
1143 chip->gpio_cs = chip_info->gpio_cs;
1144 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1145
1146 err = gpio_direction_output(chip->gpio_cs,
1147 !chip->gpio_cs_inverted);
1148 }
1149
1150 return err;
1151}
1152
Stephen Streete0c99052006-03-07 23:53:24 -08001153static int setup(struct spi_device *spi)
1154{
1155 struct pxa2xx_spi_chip *chip_info = NULL;
1156 struct chip_data *chip;
Jarkko Nikuladccf7362015-06-04 16:55:11 +03001157 const struct lpss_config *config;
Stephen Streete0c99052006-03-07 23:53:24 -08001158 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Mika Westerberga0d26422013-01-22 12:26:32 +02001159 uint tx_thres, tx_hi_thres, rx_thres;
1160
Weike Chene5262d02014-11-26 02:35:10 -08001161 switch (drv_data->ssp_type) {
1162 case QUARK_X1000_SSP:
1163 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1164 tx_hi_thres = 0;
1165 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1166 break;
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001167 case LPSS_LPT_SSP:
1168 case LPSS_BYT_SSP:
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001169 case LPSS_SPT_SSP:
Jarkko Nikulab7c08cf2015-10-28 15:13:42 +02001170 case LPSS_BXT_SSP:
Jarkko Nikuladccf7362015-06-04 16:55:11 +03001171 config = lpss_get_config(drv_data);
1172 tx_thres = config->tx_threshold_lo;
1173 tx_hi_thres = config->tx_threshold_hi;
1174 rx_thres = config->rx_threshold;
Weike Chene5262d02014-11-26 02:35:10 -08001175 break;
1176 default:
Mika Westerberga0d26422013-01-22 12:26:32 +02001177 tx_thres = TX_THRESH_DFLT;
1178 tx_hi_thres = 0;
1179 rx_thres = RX_THRESH_DFLT;
Weike Chene5262d02014-11-26 02:35:10 -08001180 break;
Mika Westerberga0d26422013-01-22 12:26:32 +02001181 }
Stephen Streete0c99052006-03-07 23:53:24 -08001182
Stephen Street8d94cc52006-12-10 02:18:54 -08001183 /* Only alloc on first setup */
Stephen Streete0c99052006-03-07 23:53:24 -08001184 chip = spi_get_ctldata(spi);
Stephen Street8d94cc52006-12-10 02:18:54 -08001185 if (!chip) {
Stephen Streete0c99052006-03-07 23:53:24 -08001186 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Jingoo Han9deae452014-04-29 17:19:38 +09001187 if (!chip)
Stephen Streete0c99052006-03-07 23:53:24 -08001188 return -ENOMEM;
1189
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001190 if (drv_data->ssp_type == CE4100_SSP) {
1191 if (spi->chip_select > 4) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001192 dev_err(&spi->dev,
1193 "failed setup: cs number must not be > 4.\n");
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001194 kfree(chip);
1195 return -EINVAL;
1196 }
1197
1198 chip->frm = spi->chip_select;
1199 } else
1200 chip->gpio_cs = -1;
Stephen Streete0c99052006-03-07 23:53:24 -08001201 chip->enable_dma = 0;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001202 chip->timeout = TIMOUT_DFLT;
Stephen Streete0c99052006-03-07 23:53:24 -08001203 }
1204
Stephen Street8d94cc52006-12-10 02:18:54 -08001205 /* protocol drivers may change the chip settings, so...
1206 * if chip_info exists, use it */
1207 chip_info = spi->controller_data;
1208
Stephen Streete0c99052006-03-07 23:53:24 -08001209 /* chip_info isn't always needed */
Stephen Street8d94cc52006-12-10 02:18:54 -08001210 chip->cr1 = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001211 if (chip_info) {
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001212 if (chip_info->timeout)
1213 chip->timeout = chip_info->timeout;
1214 if (chip_info->tx_threshold)
1215 tx_thres = chip_info->tx_threshold;
Mika Westerberga0d26422013-01-22 12:26:32 +02001216 if (chip_info->tx_hi_threshold)
1217 tx_hi_thres = chip_info->tx_hi_threshold;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001218 if (chip_info->rx_threshold)
1219 rx_thres = chip_info->rx_threshold;
1220 chip->enable_dma = drv_data->master_info->enable_dma;
Stephen Streete0c99052006-03-07 23:53:24 -08001221 chip->dma_threshold = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001222 if (chip_info->enable_loopback)
1223 chip->cr1 = SSCR1_LBM;
Mika Westerberga3496852013-01-22 12:26:33 +02001224 } else if (ACPI_HANDLE(&spi->dev)) {
1225 /*
1226 * Slave devices enumerated from ACPI namespace don't
1227 * usually have chip_info but we still might want to use
1228 * DMA with them.
1229 */
1230 chip->enable_dma = drv_data->master_info->enable_dma;
Stephen Streete0c99052006-03-07 23:53:24 -08001231 }
1232
Mika Westerberga0d26422013-01-22 12:26:32 +02001233 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1234 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1235 | SSITF_TxHiThresh(tx_hi_thres);
1236
Stephen Street8d94cc52006-12-10 02:18:54 -08001237 /* set dma burst and threshold outside of chip_info path so that if
1238 * chip_info goes away after setting chip->enable_dma, the
1239 * burst and threshold can still respond to changes in bits_per_word */
1240 if (chip->enable_dma) {
1241 /* set up legal burst and threshold for dma */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001242 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1243 spi->bits_per_word,
Stephen Street8d94cc52006-12-10 02:18:54 -08001244 &chip->dma_burst_size,
1245 &chip->dma_threshold)) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001246 dev_warn(&spi->dev,
1247 "in setup: DMA burst size reduced to match bits_per_word\n");
Stephen Street8d94cc52006-12-10 02:18:54 -08001248 }
1249 }
1250
Weike Chene5262d02014-11-26 02:35:10 -08001251 switch (drv_data->ssp_type) {
1252 case QUARK_X1000_SSP:
1253 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1254 & QUARK_X1000_SSCR1_RFT)
1255 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1256 & QUARK_X1000_SSCR1_TFT);
1257 break;
1258 default:
1259 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1260 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1261 break;
1262 }
1263
Justin Clacherty7f6ee1a2007-01-26 00:56:44 -08001264 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1265 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1266 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
Stephen Streete0c99052006-03-07 23:53:24 -08001267
Mika Westerbergb8331722013-01-22 12:26:31 +02001268 if (spi->mode & SPI_LOOP)
1269 chip->cr1 |= SSCR1_LBM;
1270
Stephen Streete0c99052006-03-07 23:53:24 -08001271 if (spi->bits_per_word <= 8) {
1272 chip->n_bytes = 1;
Stephen Streete0c99052006-03-07 23:53:24 -08001273 chip->read = u8_reader;
1274 chip->write = u8_writer;
1275 } else if (spi->bits_per_word <= 16) {
1276 chip->n_bytes = 2;
Stephen Streete0c99052006-03-07 23:53:24 -08001277 chip->read = u16_reader;
1278 chip->write = u16_writer;
1279 } else if (spi->bits_per_word <= 32) {
Stephen Streete0c99052006-03-07 23:53:24 -08001280 chip->n_bytes = 4;
Stephen Streete0c99052006-03-07 23:53:24 -08001281 chip->read = u32_reader;
1282 chip->write = u32_writer;
Stephen Streete0c99052006-03-07 23:53:24 -08001283 }
Stephen Streete0c99052006-03-07 23:53:24 -08001284
1285 spi_set_ctldata(spi, chip);
1286
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001287 if (drv_data->ssp_type == CE4100_SSP)
1288 return 0;
1289
Eric Miaoa7bb3902009-04-06 19:00:54 -07001290 return setup_cs(spi, chip, chip_info);
Stephen Streete0c99052006-03-07 23:53:24 -08001291}
1292
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001293static void cleanup(struct spi_device *spi)
Stephen Streete0c99052006-03-07 23:53:24 -08001294{
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001295 struct chip_data *chip = spi_get_ctldata(spi);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001296 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001297
Daniel Ribeiro7348d822009-05-12 13:19:36 -07001298 if (!chip)
1299 return;
1300
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001301 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
Eric Miaoa7bb3902009-04-06 19:00:54 -07001302 gpio_free(chip->gpio_cs);
1303
Stephen Streete0c99052006-03-07 23:53:24 -08001304 kfree(chip);
1305}
1306
Jarkko Nikula0db64212015-10-28 15:13:43 +02001307#ifdef CONFIG_PCI
Mika Westerberga3496852013-01-22 12:26:33 +02001308#ifdef CONFIG_ACPI
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001309
Mathias Krause8422ddf2015-06-13 14:22:14 +02001310static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001311 { "INT33C0", LPSS_LPT_SSP },
1312 { "INT33C1", LPSS_LPT_SSP },
1313 { "INT3430", LPSS_LPT_SSP },
1314 { "INT3431", LPSS_LPT_SSP },
1315 { "80860F0E", LPSS_BYT_SSP },
1316 { "8086228E", LPSS_BYT_SSP },
1317 { },
1318};
1319MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1320
Jarkko Nikula0db64212015-10-28 15:13:43 +02001321static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1322{
1323 unsigned int devid;
1324 int port_id = -1;
1325
1326 if (adev && adev->pnp.unique_id &&
1327 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1328 port_id = devid;
1329 return port_id;
1330}
1331#else /* !CONFIG_ACPI */
1332static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1333{
1334 return -1;
1335}
1336#endif
1337
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001338/*
1339 * PCI IDs of compound devices that integrate both host controller and private
1340 * integrated DMA engine. Please note these are not used in module
1341 * autoloading and probing in this module but matching the LPSS SSP type.
1342 */
1343static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1344 /* SPT-LP */
1345 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1346 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1347 /* SPT-H */
1348 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1349 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
Jarkko Nikulab7c08cf2015-10-28 15:13:42 +02001350 /* BXT */
1351 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1352 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1353 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1354 /* APL */
1355 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1356 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1357 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
Axel Lin94e5c232015-08-04 13:52:22 +08001358 { },
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001359};
1360
1361static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1362{
1363 struct device *dev = param;
1364
1365 if (dev != chan->device->dev->parent)
1366 return false;
1367
1368 return true;
1369}
1370
Mika Westerberga3496852013-01-22 12:26:33 +02001371static struct pxa2xx_spi_master *
Jarkko Nikula0db64212015-10-28 15:13:43 +02001372pxa2xx_spi_init_pdata(struct platform_device *pdev)
Mika Westerberga3496852013-01-22 12:26:33 +02001373{
1374 struct pxa2xx_spi_master *pdata;
Mika Westerberga3496852013-01-22 12:26:33 +02001375 struct acpi_device *adev;
1376 struct ssp_device *ssp;
1377 struct resource *res;
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001378 const struct acpi_device_id *adev_id = NULL;
1379 const struct pci_device_id *pcidev_id = NULL;
Jarkko Nikula3b8b6d02015-10-22 16:44:41 +03001380 int type;
Mika Westerberga3496852013-01-22 12:26:33 +02001381
Jarkko Nikulab9f69402015-09-25 10:27:18 +03001382 adev = ACPI_COMPANION(&pdev->dev);
Mika Westerberga3496852013-01-22 12:26:33 +02001383
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001384 if (dev_is_pci(pdev->dev.parent))
1385 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1386 to_pci_dev(pdev->dev.parent));
Jarkko Nikula0db64212015-10-28 15:13:43 +02001387 else if (adev)
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001388 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1389 &pdev->dev);
Jarkko Nikula0db64212015-10-28 15:13:43 +02001390 else
1391 return NULL;
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001392
1393 if (adev_id)
1394 type = (int)adev_id->driver_data;
1395 else if (pcidev_id)
1396 type = (int)pcidev_id->driver_data;
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001397 else
1398 return NULL;
1399
Mika Westerbergcc0ee982013-06-20 17:44:22 +03001400 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
Jingoo Han9deae452014-04-29 17:19:38 +09001401 if (!pdata)
Mika Westerberga3496852013-01-22 12:26:33 +02001402 return NULL;
Mika Westerberga3496852013-01-22 12:26:33 +02001403
1404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405 if (!res)
1406 return NULL;
1407
1408 ssp = &pdata->ssp;
1409
1410 ssp->phys_base = res->start;
Sachin Kamatcbfd6a22013-04-08 15:49:33 +05301411 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1412 if (IS_ERR(ssp->mmio_base))
Mika Westerberg6dc81f62013-05-13 13:45:09 +03001413 return NULL;
Mika Westerberga3496852013-01-22 12:26:33 +02001414
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001415 if (pcidev_id) {
1416 pdata->tx_param = pdev->dev.parent;
1417 pdata->rx_param = pdev->dev.parent;
1418 pdata->dma_filter = pxa2xx_spi_idma_filter;
1419 }
1420
Mika Westerberga3496852013-01-22 12:26:33 +02001421 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1422 ssp->irq = platform_get_irq(pdev, 0);
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001423 ssp->type = type;
Mika Westerberga3496852013-01-22 12:26:33 +02001424 ssp->pdev = pdev;
Jarkko Nikula0db64212015-10-28 15:13:43 +02001425 ssp->port_id = pxa2xx_spi_get_port_id(adev);
Mika Westerberga3496852013-01-22 12:26:33 +02001426
1427 pdata->num_chipselect = 1;
Mika Westerbergcddb3392013-05-13 13:45:10 +03001428 pdata->enable_dma = true;
Mika Westerberga3496852013-01-22 12:26:33 +02001429
1430 return pdata;
1431}
1432
Jarkko Nikula0db64212015-10-28 15:13:43 +02001433#else /* !CONFIG_PCI */
Mika Westerberga3496852013-01-22 12:26:33 +02001434static inline struct pxa2xx_spi_master *
Jarkko Nikula0db64212015-10-28 15:13:43 +02001435pxa2xx_spi_init_pdata(struct platform_device *pdev)
Mika Westerberga3496852013-01-22 12:26:33 +02001436{
1437 return NULL;
1438}
1439#endif
1440
Grant Likelyfd4a3192012-12-07 16:57:14 +00001441static int pxa2xx_spi_probe(struct platform_device *pdev)
Stephen Streete0c99052006-03-07 23:53:24 -08001442{
1443 struct device *dev = &pdev->dev;
1444 struct pxa2xx_spi_master *platform_info;
1445 struct spi_master *master;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001446 struct driver_data *drv_data;
eric miao2f1a74e2007-11-21 18:50:53 +08001447 struct ssp_device *ssp;
Jarkko Nikula8b136ba2015-10-28 15:13:41 +02001448 const struct lpss_config *config;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001449 int status;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001450 u32 tmp;
Stephen Streete0c99052006-03-07 23:53:24 -08001451
Mika Westerberg851bacf2013-01-07 12:44:33 +02001452 platform_info = dev_get_platdata(dev);
1453 if (!platform_info) {
Jarkko Nikula0db64212015-10-28 15:13:43 +02001454 platform_info = pxa2xx_spi_init_pdata(pdev);
Mika Westerberga3496852013-01-22 12:26:33 +02001455 if (!platform_info) {
1456 dev_err(&pdev->dev, "missing platform data\n");
1457 return -ENODEV;
1458 }
Mika Westerberg851bacf2013-01-07 12:44:33 +02001459 }
Stephen Streete0c99052006-03-07 23:53:24 -08001460
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001461 ssp = pxa_ssp_request(pdev->id, pdev->name);
Mika Westerberg851bacf2013-01-07 12:44:33 +02001462 if (!ssp)
1463 ssp = &platform_info->ssp;
1464
1465 if (!ssp->mmio_base) {
1466 dev_err(&pdev->dev, "failed to get ssp\n");
Stephen Streete0c99052006-03-07 23:53:24 -08001467 return -ENODEV;
1468 }
1469
Jarkko Nikula757fe8d2015-08-05 10:04:05 +03001470 master = spi_alloc_master(dev, sizeof(struct driver_data));
Stephen Streete0c99052006-03-07 23:53:24 -08001471 if (!master) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001472 dev_err(&pdev->dev, "cannot alloc spi_master\n");
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001473 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001474 return -ENOMEM;
1475 }
1476 drv_data = spi_master_get_devdata(master);
1477 drv_data->master = master;
1478 drv_data->master_info = platform_info;
1479 drv_data->pdev = pdev;
eric miao2f1a74e2007-11-21 18:50:53 +08001480 drv_data->ssp = ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001481
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001482 master->dev.parent = &pdev->dev;
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001483 master->dev.of_node = pdev->dev.of_node;
David Brownelle7db06b2009-06-17 16:26:04 -07001484 /* the spi->mode bits understood by this driver: */
Mika Westerbergb8331722013-01-22 12:26:31 +02001485 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
David Brownelle7db06b2009-06-17 16:26:04 -07001486
Mika Westerberg851bacf2013-01-07 12:44:33 +02001487 master->bus_num = ssp->port_id;
Mike Rapoport7ad0ba92009-04-06 19:00:57 -07001488 master->dma_alignment = DMA_ALIGNMENT;
Stephen Streete0c99052006-03-07 23:53:24 -08001489 master->cleanup = cleanup;
1490 master->setup = setup;
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001491 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
Mika Westerberg7d94a502013-01-22 12:26:30 +02001492 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
Mark Brown7dd62782013-07-28 15:35:21 +01001493 master->auto_runtime_pm = true;
Stephen Streete0c99052006-03-07 23:53:24 -08001494
eric miao2f1a74e2007-11-21 18:50:53 +08001495 drv_data->ssp_type = ssp->type;
Stephen Streete0c99052006-03-07 23:53:24 -08001496
eric miao2f1a74e2007-11-21 18:50:53 +08001497 drv_data->ioaddr = ssp->mmio_base;
1498 drv_data->ssdr_physical = ssp->phys_base + SSDR;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001499 if (pxa25x_ssp_comp(drv_data)) {
Weike Chene5262d02014-11-26 02:35:10 -08001500 switch (drv_data->ssp_type) {
1501 case QUARK_X1000_SSP:
1502 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1503 break;
1504 default:
1505 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1506 break;
1507 }
1508
Stephen Streete0c99052006-03-07 23:53:24 -08001509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 } else {
Stephen Warren24778be2013-05-21 20:36:35 -06001514 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Stephen Streete0c99052006-03-07 23:53:24 -08001515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
Mika Westerberg59288082013-01-22 12:26:29 +02001516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
Stephen Streete0c99052006-03-07 23:53:24 -08001517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1519 }
1520
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -08001521 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1522 drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001523 if (status < 0) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001524 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
Stephen Streete0c99052006-03-07 23:53:24 -08001525 goto out_error_master_alloc;
1526 }
1527
1528 /* Setup DMA if requested */
Stephen Streete0c99052006-03-07 23:53:24 -08001529 if (platform_info->enable_dma) {
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001530 status = pxa2xx_spi_dma_setup(drv_data);
1531 if (status) {
Mika Westerbergcddb3392013-05-13 13:45:10 +03001532 dev_dbg(dev, "no DMA channels available, using PIO\n");
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001533 platform_info->enable_dma = false;
Stephen Streete0c99052006-03-07 23:53:24 -08001534 }
Stephen Streete0c99052006-03-07 23:53:24 -08001535 }
1536
1537 /* Enable SOC clock */
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001538 clk_prepare_enable(ssp->clk);
1539
Jarkko Nikula0eca7cf2015-09-25 10:27:17 +03001540 master->max_speed_hz = clk_get_rate(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001541
1542 /* Load default SSP configuration */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001543 pxa2xx_spi_write(drv_data, SSCR0, 0);
Weike Chene5262d02014-11-26 02:35:10 -08001544 switch (drv_data->ssp_type) {
1545 case QUARK_X1000_SSP:
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001546 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1547 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1548 pxa2xx_spi_write(drv_data, SSCR1, tmp);
Weike Chene5262d02014-11-26 02:35:10 -08001549
1550 /* using the Motorola SPI protocol and use 8 bit frame */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001551 pxa2xx_spi_write(drv_data, SSCR0,
1552 QUARK_X1000_SSCR0_Motorola
1553 | QUARK_X1000_SSCR0_DataSize(8));
Weike Chene5262d02014-11-26 02:35:10 -08001554 break;
1555 default:
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001556 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1557 SSCR1_TxTresh(TX_THRESH_DFLT);
1558 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1559 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1560 pxa2xx_spi_write(drv_data, SSCR0, tmp);
Weike Chene5262d02014-11-26 02:35:10 -08001561 break;
1562 }
1563
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001564 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001565 pxa2xx_spi_write(drv_data, SSTO, 0);
Weike Chene5262d02014-11-26 02:35:10 -08001566
1567 if (!is_quark_x1000_ssp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001568 pxa2xx_spi_write(drv_data, SSPSP, 0);
Stephen Streete0c99052006-03-07 23:53:24 -08001569
Jarkko Nikula7566bcc2014-12-18 15:04:20 +02001570 if (is_lpss_ssp(drv_data))
1571 lpss_ssp_setup(drv_data);
Mika Westerberga0d26422013-01-22 12:26:32 +02001572
Jarkko Nikula8b136ba2015-10-28 15:13:41 +02001573 if (is_lpss_ssp(drv_data)) {
1574 lpss_ssp_setup(drv_data);
1575 config = lpss_get_config(drv_data);
1576 if (config->reg_capabilities >= 0) {
1577 tmp = __lpss_ssp_read_priv(drv_data,
1578 config->reg_capabilities);
1579 tmp &= LPSS_CAPS_CS_EN_MASK;
1580 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1581 platform_info->num_chipselect = ffz(tmp);
1582 }
1583 }
1584 master->num_chipselect = platform_info->num_chipselect;
1585
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001586 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1587 (unsigned long)drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001588
Antonio Ospite836d1a22014-05-30 18:18:09 +02001589 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1590 pm_runtime_use_autosuspend(&pdev->dev);
1591 pm_runtime_set_active(&pdev->dev);
1592 pm_runtime_enable(&pdev->dev);
1593
Stephen Streete0c99052006-03-07 23:53:24 -08001594 /* Register with the SPI framework */
1595 platform_set_drvdata(pdev, drv_data);
Jingoo Hana807fcd2013-09-24 13:46:55 +09001596 status = devm_spi_register_master(&pdev->dev, master);
Stephen Streete0c99052006-03-07 23:53:24 -08001597 if (status != 0) {
1598 dev_err(&pdev->dev, "problem registering spi master\n");
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001599 goto out_error_clock_enabled;
Stephen Streete0c99052006-03-07 23:53:24 -08001600 }
1601
1602 return status;
1603
Stephen Streete0c99052006-03-07 23:53:24 -08001604out_error_clock_enabled:
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001605 clk_disable_unprepare(ssp->clk);
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001606 pxa2xx_spi_dma_release(drv_data);
eric miao2f1a74e2007-11-21 18:50:53 +08001607 free_irq(ssp->irq, drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001608
1609out_error_master_alloc:
1610 spi_master_put(master);
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001611 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001612 return status;
1613}
1614
1615static int pxa2xx_spi_remove(struct platform_device *pdev)
1616{
1617 struct driver_data *drv_data = platform_get_drvdata(pdev);
Julia Lawall51e911e2009-01-06 14:41:45 -08001618 struct ssp_device *ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001619
1620 if (!drv_data)
1621 return 0;
Julia Lawall51e911e2009-01-06 14:41:45 -08001622 ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001623
Mika Westerberg7d94a502013-01-22 12:26:30 +02001624 pm_runtime_get_sync(&pdev->dev);
1625
Stephen Streete0c99052006-03-07 23:53:24 -08001626 /* Disable the SSP at the peripheral and SOC level */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001627 pxa2xx_spi_write(drv_data, SSCR0, 0);
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001628 clk_disable_unprepare(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001629
1630 /* Release DMA */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001631 if (drv_data->master_info->enable_dma)
1632 pxa2xx_spi_dma_release(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001633
Mika Westerberg7d94a502013-01-22 12:26:30 +02001634 pm_runtime_put_noidle(&pdev->dev);
1635 pm_runtime_disable(&pdev->dev);
1636
Stephen Streete0c99052006-03-07 23:53:24 -08001637 /* Release IRQ */
eric miao2f1a74e2007-11-21 18:50:53 +08001638 free_irq(ssp->irq, drv_data);
1639
1640 /* Release SSP */
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001641 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001642
Stephen Streete0c99052006-03-07 23:53:24 -08001643 return 0;
1644}
1645
1646static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1647{
1648 int status = 0;
1649
1650 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1651 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1652}
1653
Mika Westerberg382cebb2014-01-16 14:50:55 +02001654#ifdef CONFIG_PM_SLEEP
Mike Rapoport86d25932009-07-21 17:50:16 +03001655static int pxa2xx_spi_suspend(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001656{
Mike Rapoport86d25932009-07-21 17:50:16 +03001657 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001658 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001659 int status = 0;
1660
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001661 status = spi_master_suspend(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001662 if (status != 0)
1663 return status;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001664 pxa2xx_spi_write(drv_data, SSCR0, 0);
Dmitry Eremin-Solenikov2b9375b2014-11-06 14:08:29 +03001665
1666 if (!pm_runtime_suspended(dev))
1667 clk_disable_unprepare(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001668
1669 return 0;
1670}
1671
Mike Rapoport86d25932009-07-21 17:50:16 +03001672static int pxa2xx_spi_resume(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001673{
Mike Rapoport86d25932009-07-21 17:50:16 +03001674 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001675 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001676 int status = 0;
1677
1678 /* Enable the SSP clock */
Dmitry Eremin-Solenikov2b9375b2014-11-06 14:08:29 +03001679 if (!pm_runtime_suspended(dev))
1680 clk_prepare_enable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001681
Chew, Chiau Eec50325f2013-11-29 02:13:11 +08001682 /* Restore LPSS private register bits */
Jarkko Nikula48421ad2015-01-28 10:09:42 +02001683 if (is_lpss_ssp(drv_data))
1684 lpss_ssp_setup(drv_data);
Chew, Chiau Eec50325f2013-11-29 02:13:11 +08001685
Stephen Streete0c99052006-03-07 23:53:24 -08001686 /* Start the queue running */
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001687 status = spi_master_resume(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001688 if (status != 0) {
Mike Rapoport86d25932009-07-21 17:50:16 +03001689 dev_err(dev, "problem starting queue (%d)\n", status);
Stephen Streete0c99052006-03-07 23:53:24 -08001690 return status;
1691 }
1692
1693 return 0;
1694}
Mika Westerberg7d94a502013-01-22 12:26:30 +02001695#endif
1696
Rafael J. Wysockiec833052014-12-13 00:41:15 +01001697#ifdef CONFIG_PM
Mika Westerberg7d94a502013-01-22 12:26:30 +02001698static int pxa2xx_spi_runtime_suspend(struct device *dev)
1699{
1700 struct driver_data *drv_data = dev_get_drvdata(dev);
1701
1702 clk_disable_unprepare(drv_data->ssp->clk);
1703 return 0;
1704}
1705
1706static int pxa2xx_spi_runtime_resume(struct device *dev)
1707{
1708 struct driver_data *drv_data = dev_get_drvdata(dev);
1709
1710 clk_prepare_enable(drv_data->ssp->clk);
1711 return 0;
1712}
1713#endif
Mike Rapoport86d25932009-07-21 17:50:16 +03001714
Alexey Dobriyan47145212009-12-14 18:00:08 -08001715static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
Mika Westerberg7d94a502013-01-22 12:26:30 +02001716 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1717 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1718 pxa2xx_spi_runtime_resume, NULL)
Mike Rapoport86d25932009-07-21 17:50:16 +03001719};
Stephen Streete0c99052006-03-07 23:53:24 -08001720
1721static struct platform_driver driver = {
1722 .driver = {
Mike Rapoport86d25932009-07-21 17:50:16 +03001723 .name = "pxa2xx-spi",
Mike Rapoport86d25932009-07-21 17:50:16 +03001724 .pm = &pxa2xx_spi_pm_ops,
Mika Westerberga3496852013-01-22 12:26:33 +02001725 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
Stephen Streete0c99052006-03-07 23:53:24 -08001726 },
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001727 .probe = pxa2xx_spi_probe,
David Brownelld1e44d92007-10-16 01:27:46 -07001728 .remove = pxa2xx_spi_remove,
Stephen Streete0c99052006-03-07 23:53:24 -08001729 .shutdown = pxa2xx_spi_shutdown,
Stephen Streete0c99052006-03-07 23:53:24 -08001730};
1731
1732static int __init pxa2xx_spi_init(void)
1733{
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001734 return platform_driver_register(&driver);
Stephen Streete0c99052006-03-07 23:53:24 -08001735}
Antonio Ospite5b61a742009-09-22 16:46:10 -07001736subsys_initcall(pxa2xx_spi_init);
Stephen Streete0c99052006-03-07 23:53:24 -08001737
1738static void __exit pxa2xx_spi_exit(void)
1739{
1740 platform_driver_unregister(&driver);
1741}
1742module_exit(pxa2xx_spi_exit);