| Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 1 | /* |
| 2 | * bits.h - register bits of the ChipIdea USB IP core |
| 3 | * |
| 4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
| 5 | * |
| 6 | * Author: David Lopo |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H |
| 14 | #define __DRIVERS_USB_CHIPIDEA_BITS_H |
| 15 | |
| 16 | /* HCCPARAMS */ |
| 17 | #define HCCPARAMS_LEN BIT(17) |
| 18 | |
| 19 | /* DCCPARAMS */ |
| 20 | #define DCCPARAMS_DEN (0x1F << 0) |
| 21 | #define DCCPARAMS_DC BIT(7) |
| 22 | |
| 23 | /* TESTMODE */ |
| 24 | #define TESTMODE_FORCE BIT(0) |
| 25 | |
| 26 | /* USBCMD */ |
| 27 | #define USBCMD_RS BIT(0) |
| 28 | #define USBCMD_RST BIT(1) |
| 29 | #define USBCMD_SUTW BIT(13) |
| 30 | #define USBCMD_ATDTW BIT(14) |
| 31 | |
| 32 | /* USBSTS & USBINTR */ |
| 33 | #define USBi_UI BIT(0) |
| 34 | #define USBi_UEI BIT(1) |
| 35 | #define USBi_PCI BIT(2) |
| 36 | #define USBi_URI BIT(6) |
| 37 | #define USBi_SLI BIT(8) |
| 38 | |
| 39 | /* DEVICEADDR */ |
| 40 | #define DEVICEADDR_USBADRA BIT(24) |
| 41 | #define DEVICEADDR_USBADR (0x7FUL << 25) |
| 42 | |
| 43 | /* PORTSC */ |
| 44 | #define PORTSC_FPR BIT(6) |
| 45 | #define PORTSC_SUSP BIT(7) |
| 46 | #define PORTSC_HSP BIT(9) |
| 47 | #define PORTSC_PTC (0x0FUL << 16) |
| 48 | |
| 49 | /* DEVLC */ |
| 50 | #define DEVLC_PSPD (0x03UL << 25) |
| 51 | #define DEVLC_PSPD_HS (0x02UL << 25) |
| 52 | |
| Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame^] | 53 | /* OTGSC */ |
| 54 | #define OTGSC_IDPU BIT(5) |
| 55 | #define OTGSC_ID BIT(8) |
| 56 | #define OTGSC_AVV BIT(9) |
| 57 | #define OTGSC_ASV BIT(10) |
| 58 | #define OTGSC_BSV BIT(11) |
| 59 | #define OTGSC_BSE BIT(12) |
| 60 | #define OTGSC_IDIS BIT(16) |
| 61 | #define OTGSC_AVVIS BIT(17) |
| 62 | #define OTGSC_ASVIS BIT(18) |
| 63 | #define OTGSC_BSVIS BIT(19) |
| 64 | #define OTGSC_BSEIS BIT(20) |
| 65 | #define OTGSC_IDIE BIT(24) |
| 66 | #define OTGSC_AVVIE BIT(25) |
| 67 | #define OTGSC_ASVIE BIT(26) |
| 68 | #define OTGSC_BSVIE BIT(27) |
| 69 | #define OTGSC_BSEIE BIT(28) |
| 70 | |
| Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 71 | /* USBMODE */ |
| 72 | #define USBMODE_CM (0x03UL << 0) |
| 73 | #define USBMODE_CM_IDLE (0x00UL << 0) |
| 74 | #define USBMODE_CM_DEVICE (0x02UL << 0) |
| 75 | #define USBMODE_CM_HOST (0x03UL << 0) |
| 76 | #define USBMODE_SLOM BIT(3) |
| 77 | #define USBMODE_SDIS BIT(4) |
| 78 | |
| 79 | /* ENDPTCTRL */ |
| 80 | #define ENDPTCTRL_RXS BIT(0) |
| 81 | #define ENDPTCTRL_RXT (0x03UL << 2) |
| 82 | #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ |
| 83 | #define ENDPTCTRL_RXE BIT(7) |
| 84 | #define ENDPTCTRL_TXS BIT(16) |
| 85 | #define ENDPTCTRL_TXT (0x03UL << 18) |
| 86 | #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ |
| 87 | #define ENDPTCTRL_TXE BIT(23) |
| 88 | |
| 89 | #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */ |