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Sascha Hauer47d37d62011-01-11 15:54:54 +01001/*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
Janusz Uzycki914d3b12014-10-10 13:13:28 +020017#if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
Sascha Hauer47d37d62011-01-11 15:54:54 +010021#include <linux/kernel.h>
Sascha Hauer47d37d62011-01-11 15:54:54 +010022#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27#include <linux/slab.h>
28#include <linux/wait.h>
29#include <linux/tty.h>
30#include <linux/tty_driver.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/serial_core.h>
34#include <linux/platform_device.h>
35#include <linux/device.h>
36#include <linux/clk.h>
37#include <linux/delay.h>
38#include <linux/io.h>
Fabio Estevam1ea66072012-06-18 10:06:09 -030039#include <linux/of_device.h>
Huang Shijiee8001632012-11-16 16:03:53 +080040#include <linux/dma-mapping.h>
Shawn Guobcc20f92013-02-26 13:47:41 +080041#include <linux/dmaengine.h>
Sascha Hauer47d37d62011-01-11 15:54:54 +010042
43#include <asm/cacheflush.h>
44
Janusz Uzyckif9e42392014-10-10 18:53:26 +020045#include <linux/gpio.h>
46#include <linux/gpio/consumer.h>
Janusz Uzycki7c573d72014-10-10 18:53:25 +020047#include <linux/err.h>
Janusz Uzyckif9e42392014-10-10 18:53:26 +020048#include <linux/irq.h>
Janusz Uzycki7c573d72014-10-10 18:53:25 +020049#include "serial_mctrl_gpio.h"
50
Sascha Hauer47d37d62011-01-11 15:54:54 +010051#define MXS_AUART_PORTS 5
Hector Palacios9987f762013-10-03 09:32:03 +020052#define MXS_AUART_FIFO_SIZE 16
Sascha Hauer47d37d62011-01-11 15:54:54 +010053
54#define AUART_CTRL0 0x00000000
55#define AUART_CTRL0_SET 0x00000004
56#define AUART_CTRL0_CLR 0x00000008
57#define AUART_CTRL0_TOG 0x0000000c
58#define AUART_CTRL1 0x00000010
59#define AUART_CTRL1_SET 0x00000014
60#define AUART_CTRL1_CLR 0x00000018
61#define AUART_CTRL1_TOG 0x0000001c
62#define AUART_CTRL2 0x00000020
63#define AUART_CTRL2_SET 0x00000024
64#define AUART_CTRL2_CLR 0x00000028
65#define AUART_CTRL2_TOG 0x0000002c
66#define AUART_LINECTRL 0x00000030
67#define AUART_LINECTRL_SET 0x00000034
68#define AUART_LINECTRL_CLR 0x00000038
69#define AUART_LINECTRL_TOG 0x0000003c
70#define AUART_LINECTRL2 0x00000040
71#define AUART_LINECTRL2_SET 0x00000044
72#define AUART_LINECTRL2_CLR 0x00000048
73#define AUART_LINECTRL2_TOG 0x0000004c
74#define AUART_INTR 0x00000050
75#define AUART_INTR_SET 0x00000054
76#define AUART_INTR_CLR 0x00000058
77#define AUART_INTR_TOG 0x0000005c
78#define AUART_DATA 0x00000060
79#define AUART_STAT 0x00000070
80#define AUART_DEBUG 0x00000080
81#define AUART_VERSION 0x00000090
82#define AUART_AUTOBAUD 0x000000a0
83
84#define AUART_CTRL0_SFTRST (1 << 31)
85#define AUART_CTRL0_CLKGATE (1 << 30)
Huang Shijiee8001632012-11-16 16:03:53 +080086#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
87#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
88#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
89
90#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
91
92#define AUART_CTRL2_DMAONERR (1 << 26)
93#define AUART_CTRL2_TXDMAE (1 << 25)
94#define AUART_CTRL2_RXDMAE (1 << 24)
Sascha Hauer47d37d62011-01-11 15:54:54 +010095
96#define AUART_CTRL2_CTSEN (1 << 15)
Huang Shijie00592022012-08-08 10:37:59 +080097#define AUART_CTRL2_RTSEN (1 << 14)
Sascha Hauer47d37d62011-01-11 15:54:54 +010098#define AUART_CTRL2_RTS (1 << 11)
99#define AUART_CTRL2_RXE (1 << 9)
100#define AUART_CTRL2_TXE (1 << 8)
101#define AUART_CTRL2_UARTEN (1 << 0)
102
103#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
104#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
105#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
106#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
107#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
108#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
109#define AUART_LINECTRL_WLEN_MASK 0x00000060
110#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
111#define AUART_LINECTRL_FEN (1 << 4)
112#define AUART_LINECTRL_STP2 (1 << 3)
113#define AUART_LINECTRL_EPS (1 << 2)
114#define AUART_LINECTRL_PEN (1 << 1)
115#define AUART_LINECTRL_BRK (1 << 0)
116
117#define AUART_INTR_RTIEN (1 << 22)
118#define AUART_INTR_TXIEN (1 << 21)
119#define AUART_INTR_RXIEN (1 << 20)
120#define AUART_INTR_CTSMIEN (1 << 17)
121#define AUART_INTR_RTIS (1 << 6)
122#define AUART_INTR_TXIS (1 << 5)
123#define AUART_INTR_RXIS (1 << 4)
124#define AUART_INTR_CTSMIS (1 << 1)
125
126#define AUART_STAT_BUSY (1 << 29)
127#define AUART_STAT_CTS (1 << 28)
128#define AUART_STAT_TXFE (1 << 27)
129#define AUART_STAT_TXFF (1 << 25)
130#define AUART_STAT_RXFE (1 << 24)
131#define AUART_STAT_OERR (1 << 19)
132#define AUART_STAT_BERR (1 << 18)
133#define AUART_STAT_PERR (1 << 17)
134#define AUART_STAT_FERR (1 << 16)
Huang Shijiee8001632012-11-16 16:03:53 +0800135#define AUART_STAT_RXCOUNT_MASK 0xffff
Sascha Hauer47d37d62011-01-11 15:54:54 +0100136
137static struct uart_driver auart_driver;
138
Huang Shijief4b1f03b2012-11-16 16:03:52 +0800139enum mxs_auart_type {
140 IMX23_AUART,
141 IMX28_AUART,
142};
143
Sascha Hauer47d37d62011-01-11 15:54:54 +0100144struct mxs_auart_port {
145 struct uart_port port;
146
Huang Shijiee8001632012-11-16 16:03:53 +0800147#define MXS_AUART_DMA_ENABLED 0x2
148#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
149#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
Huang Shijie8418e672013-08-03 10:09:14 -0400150#define MXS_AUART_RTSCTS 4 /* bit 4 */
Huang Shijiee8001632012-11-16 16:03:53 +0800151 unsigned long flags;
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200152 unsigned int mctrl_prev;
Huang Shijief4b1f03b2012-11-16 16:03:52 +0800153 enum mxs_auart_type devtype;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100154
Sascha Hauer47d37d62011-01-11 15:54:54 +0100155 struct clk *clk;
156 struct device *dev;
Huang Shijiee8001632012-11-16 16:03:53 +0800157
158 /* for DMA */
Huang Shijiee8001632012-11-16 16:03:53 +0800159 struct scatterlist tx_sgl;
160 struct dma_chan *tx_dma_chan;
161 void *tx_dma_buf;
162
163 struct scatterlist rx_sgl;
164 struct dma_chan *rx_dma_chan;
165 void *rx_dma_buf;
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200166
167 struct mctrl_gpios *gpios;
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200168 int gpio_irq[UART_GPIO_MAX];
169 bool ms_irq_enabled;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100170};
171
Huang Shijief4b1f03b2012-11-16 16:03:52 +0800172static struct platform_device_id mxs_auart_devtype[] = {
173 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
174 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
175 { /* sentinel */ }
176};
177MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
178
179static struct of_device_id mxs_auart_dt_ids[] = {
180 {
181 .compatible = "fsl,imx28-auart",
182 .data = &mxs_auart_devtype[IMX28_AUART]
183 }, {
184 .compatible = "fsl,imx23-auart",
185 .data = &mxs_auart_devtype[IMX23_AUART]
186 }, { /* sentinel */ }
187};
188MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
189
190static inline int is_imx28_auart(struct mxs_auart_port *s)
191{
192 return s->devtype == IMX28_AUART;
193}
194
Huang Shijiee8001632012-11-16 16:03:53 +0800195static inline bool auart_dma_enabled(struct mxs_auart_port *s)
196{
197 return s->flags & MXS_AUART_DMA_ENABLED;
198}
199
Sascha Hauer47d37d62011-01-11 15:54:54 +0100200static void mxs_auart_stop_tx(struct uart_port *u);
201
202#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
203
Huang Shijiee8001632012-11-16 16:03:53 +0800204static void mxs_auart_tx_chars(struct mxs_auart_port *s);
205
206static void dma_tx_callback(void *param)
207{
208 struct mxs_auart_port *s = param;
209 struct circ_buf *xmit = &s->port.state->xmit;
210
211 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
212
213 /* clear the bit used to serialize the DMA tx. */
214 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
Peter Zijlstra4e857c52014-03-17 18:06:10 +0100215 smp_mb__after_atomic();
Huang Shijiee8001632012-11-16 16:03:53 +0800216
217 /* wake up the possible processes. */
218 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
219 uart_write_wakeup(&s->port);
220
221 mxs_auart_tx_chars(s);
222}
223
224static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
225{
226 struct dma_async_tx_descriptor *desc;
227 struct scatterlist *sgl = &s->tx_sgl;
228 struct dma_chan *channel = s->tx_dma_chan;
229 u32 pio;
230
231 /* [1] : send PIO. Note, the first pio word is CTRL1. */
232 pio = AUART_CTRL1_XFER_COUNT(size);
233 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
234 1, DMA_TRANS_NONE, 0);
235 if (!desc) {
236 dev_err(s->dev, "step 1 error\n");
237 return -EINVAL;
238 }
239
240 /* [2] : set DMA buffer. */
241 sg_init_one(sgl, s->tx_dma_buf, size);
242 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
243 desc = dmaengine_prep_slave_sg(channel, sgl,
244 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
245 if (!desc) {
246 dev_err(s->dev, "step 2 error\n");
247 return -EINVAL;
248 }
249
250 /* [3] : submit the DMA */
251 desc->callback = dma_tx_callback;
252 desc->callback_param = s;
253 dmaengine_submit(desc);
254 dma_async_issue_pending(channel);
255 return 0;
256}
257
258static void mxs_auart_tx_chars(struct mxs_auart_port *s)
Sascha Hauer47d37d62011-01-11 15:54:54 +0100259{
260 struct circ_buf *xmit = &s->port.state->xmit;
261
Huang Shijiee8001632012-11-16 16:03:53 +0800262 if (auart_dma_enabled(s)) {
fabio.estevam@freescale.com87b8bed2013-01-07 23:11:06 -0200263 u32 i = 0;
Huang Shijiee8001632012-11-16 16:03:53 +0800264 int size;
265 void *buffer = s->tx_dma_buf;
266
267 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
268 return;
269
270 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
271 size = min_t(u32, UART_XMIT_SIZE - i,
272 CIRC_CNT_TO_END(xmit->head,
273 xmit->tail,
274 UART_XMIT_SIZE));
275 memcpy(buffer + i, xmit->buf + xmit->tail, size);
276 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
277
278 i += size;
279 if (i >= UART_XMIT_SIZE)
280 break;
281 }
282
283 if (uart_tx_stopped(&s->port))
284 mxs_auart_stop_tx(&s->port);
285
286 if (i) {
287 mxs_auart_dma_tx(s, i);
288 } else {
289 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
Peter Zijlstra4e857c52014-03-17 18:06:10 +0100290 smp_mb__after_atomic();
Huang Shijiee8001632012-11-16 16:03:53 +0800291 }
292 return;
293 }
294
295
Sascha Hauer47d37d62011-01-11 15:54:54 +0100296 while (!(readl(s->port.membase + AUART_STAT) &
297 AUART_STAT_TXFF)) {
298 if (s->port.x_char) {
299 s->port.icount.tx++;
300 writel(s->port.x_char,
301 s->port.membase + AUART_DATA);
302 s->port.x_char = 0;
303 continue;
304 }
305 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
306 s->port.icount.tx++;
307 writel(xmit->buf[xmit->tail],
308 s->port.membase + AUART_DATA);
309 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100310 } else
311 break;
312 }
Uwe Kleine-Königd0758a22011-11-22 14:22:56 +0100313 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
314 uart_write_wakeup(&s->port);
315
Sascha Hauer47d37d62011-01-11 15:54:54 +0100316 if (uart_circ_empty(&(s->port.state->xmit)))
317 writel(AUART_INTR_TXIEN,
318 s->port.membase + AUART_INTR_CLR);
319 else
320 writel(AUART_INTR_TXIEN,
321 s->port.membase + AUART_INTR_SET);
322
323 if (uart_tx_stopped(&s->port))
324 mxs_auart_stop_tx(&s->port);
325}
326
327static void mxs_auart_rx_char(struct mxs_auart_port *s)
328{
329 int flag;
330 u32 stat;
331 u8 c;
332
333 c = readl(s->port.membase + AUART_DATA);
334 stat = readl(s->port.membase + AUART_STAT);
335
336 flag = TTY_NORMAL;
337 s->port.icount.rx++;
338
339 if (stat & AUART_STAT_BERR) {
340 s->port.icount.brk++;
341 if (uart_handle_break(&s->port))
342 goto out;
343 } else if (stat & AUART_STAT_PERR) {
344 s->port.icount.parity++;
345 } else if (stat & AUART_STAT_FERR) {
346 s->port.icount.frame++;
347 }
348
349 /*
350 * Mask off conditions which should be ingored.
351 */
352 stat &= s->port.read_status_mask;
353
354 if (stat & AUART_STAT_BERR) {
355 flag = TTY_BREAK;
356 } else if (stat & AUART_STAT_PERR)
357 flag = TTY_PARITY;
358 else if (stat & AUART_STAT_FERR)
359 flag = TTY_FRAME;
360
361 if (stat & AUART_STAT_OERR)
362 s->port.icount.overrun++;
363
364 if (uart_handle_sysrq_char(&s->port, c))
365 goto out;
366
367 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
368out:
369 writel(stat, s->port.membase + AUART_STAT);
370}
371
372static void mxs_auart_rx_chars(struct mxs_auart_port *s)
373{
Sascha Hauer47d37d62011-01-11 15:54:54 +0100374 u32 stat = 0;
375
376 for (;;) {
377 stat = readl(s->port.membase + AUART_STAT);
378 if (stat & AUART_STAT_RXFE)
379 break;
380 mxs_auart_rx_char(s);
381 }
382
383 writel(stat, s->port.membase + AUART_STAT);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100384 tty_flip_buffer_push(&s->port.state->port);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100385}
386
387static int mxs_auart_request_port(struct uart_port *u)
388{
389 return 0;
390}
391
392static int mxs_auart_verify_port(struct uart_port *u,
393 struct serial_struct *ser)
394{
395 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
396 return -EINVAL;
397 return 0;
398}
399
400static void mxs_auart_config_port(struct uart_port *u, int flags)
401{
402}
403
404static const char *mxs_auart_type(struct uart_port *u)
405{
406 struct mxs_auart_port *s = to_auart_port(u);
407
408 return dev_name(s->dev);
409}
410
411static void mxs_auart_release_port(struct uart_port *u)
412{
413}
414
415static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
416{
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200417 struct mxs_auart_port *s = to_auart_port(u);
418
Sascha Hauer47d37d62011-01-11 15:54:54 +0100419 u32 ctrl = readl(u->membase + AUART_CTRL2);
420
Steffen Trumtrara6833212012-12-13 14:27:43 +0100421 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
Huang Shijie00592022012-08-08 10:37:59 +0800422 if (mctrl & TIOCM_RTS) {
Peter Hurley299245a2014-09-10 15:06:24 -0400423 if (uart_cts_enabled(u))
Huang Shijie00592022012-08-08 10:37:59 +0800424 ctrl |= AUART_CTRL2_RTSEN;
Steffen Trumtrara6833212012-12-13 14:27:43 +0100425 else
426 ctrl |= AUART_CTRL2_RTS;
Huang Shijie00592022012-08-08 10:37:59 +0800427 }
428
Sascha Hauer47d37d62011-01-11 15:54:54 +0100429 writel(ctrl, u->membase + AUART_CTRL2);
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200430
431 mctrl_gpio_set(s->gpios, mctrl);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100432}
433
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200434#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
435static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
436{
437 u32 mctrl_diff;
438
439 mctrl_diff = mctrl ^ s->mctrl_prev;
440 s->mctrl_prev = mctrl;
441 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
442 s->port.state != NULL) {
443 if (mctrl_diff & TIOCM_RI)
444 s->port.icount.rng++;
445 if (mctrl_diff & TIOCM_DSR)
446 s->port.icount.dsr++;
447 if (mctrl_diff & TIOCM_CD)
448 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
449 if (mctrl_diff & TIOCM_CTS)
450 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
451
452 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
453 }
454 return mctrl;
455}
456
Sascha Hauer47d37d62011-01-11 15:54:54 +0100457static u32 mxs_auart_get_mctrl(struct uart_port *u)
458{
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200459 struct mxs_auart_port *s = to_auart_port(u);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100460 u32 stat = readl(u->membase + AUART_STAT);
Janusz Uzycki42b4eba2014-10-10 18:53:24 +0200461 u32 mctrl = 0;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100462
Sascha Hauer47d37d62011-01-11 15:54:54 +0100463 if (stat & AUART_STAT_CTS)
464 mctrl |= TIOCM_CTS;
465
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200466 return mctrl_gpio_get(s->gpios, &mctrl);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100467}
468
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200469/*
470 * Enable modem status interrupts
471 */
472static void mxs_auart_enable_ms(struct uart_port *port)
473{
474 struct mxs_auart_port *s = to_auart_port(port);
475
476 /*
477 * Interrupt should not be enabled twice
478 */
479 if (s->ms_irq_enabled)
480 return;
481
482 s->ms_irq_enabled = true;
483
484 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
485 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
486 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
487
488 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
489 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
490
491 if (s->gpio_irq[UART_GPIO_RI] >= 0)
492 enable_irq(s->gpio_irq[UART_GPIO_RI]);
493
494 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
495 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
496}
497
498/*
499 * Disable modem status interrupts
500 */
501static void mxs_auart_disable_ms(struct uart_port *port)
502{
503 struct mxs_auart_port *s = to_auart_port(port);
504
505 /*
506 * Interrupt should not be disabled twice
507 */
508 if (!s->ms_irq_enabled)
509 return;
510
511 s->ms_irq_enabled = false;
512
513 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
514 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
515 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
516
517 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
518 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
519
520 if (s->gpio_irq[UART_GPIO_RI] >= 0)
521 disable_irq(s->gpio_irq[UART_GPIO_RI]);
522
523 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
524 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
525}
526
Huang Shijiee8001632012-11-16 16:03:53 +0800527static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
528static void dma_rx_callback(void *arg)
529{
530 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100531 struct tty_port *port = &s->port.state->port;
Huang Shijiee8001632012-11-16 16:03:53 +0800532 int count;
533 u32 stat;
534
Huang Shijied7ffb932012-11-22 15:06:30 +0800535 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
536
Huang Shijiee8001632012-11-16 16:03:53 +0800537 stat = readl(s->port.membase + AUART_STAT);
538 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
539 AUART_STAT_PERR | AUART_STAT_FERR);
540
541 count = stat & AUART_STAT_RXCOUNT_MASK;
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100542 tty_insert_flip_string(port, s->rx_dma_buf, count);
Huang Shijiee8001632012-11-16 16:03:53 +0800543
544 writel(stat, s->port.membase + AUART_STAT);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100545 tty_flip_buffer_push(port);
Huang Shijiee8001632012-11-16 16:03:53 +0800546
547 /* start the next DMA for RX. */
548 mxs_auart_dma_prep_rx(s);
549}
550
551static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
552{
553 struct dma_async_tx_descriptor *desc;
554 struct scatterlist *sgl = &s->rx_sgl;
555 struct dma_chan *channel = s->rx_dma_chan;
556 u32 pio[1];
557
558 /* [1] : send PIO */
559 pio[0] = AUART_CTRL0_RXTO_ENABLE
560 | AUART_CTRL0_RXTIMEOUT(0x80)
561 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
562 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
563 1, DMA_TRANS_NONE, 0);
564 if (!desc) {
565 dev_err(s->dev, "step 1 error\n");
566 return -EINVAL;
567 }
568
569 /* [2] : send DMA request */
570 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
571 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
572 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
573 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
574 if (!desc) {
575 dev_err(s->dev, "step 2 error\n");
576 return -1;
577 }
578
579 /* [3] : submit the DMA, but do not issue it. */
580 desc->callback = dma_rx_callback;
581 desc->callback_param = s;
582 dmaengine_submit(desc);
583 dma_async_issue_pending(channel);
584 return 0;
585}
586
587static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
588{
589 if (s->tx_dma_chan) {
590 dma_release_channel(s->tx_dma_chan);
591 s->tx_dma_chan = NULL;
592 }
593 if (s->rx_dma_chan) {
594 dma_release_channel(s->rx_dma_chan);
595 s->rx_dma_chan = NULL;
596 }
597
598 kfree(s->tx_dma_buf);
599 kfree(s->rx_dma_buf);
600 s->tx_dma_buf = NULL;
601 s->rx_dma_buf = NULL;
602}
603
604static void mxs_auart_dma_exit(struct mxs_auart_port *s)
605{
606
607 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
608 s->port.membase + AUART_CTRL2_CLR);
609
610 mxs_auart_dma_exit_channel(s);
611 s->flags &= ~MXS_AUART_DMA_ENABLED;
612 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
613 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
614}
615
616static int mxs_auart_dma_init(struct mxs_auart_port *s)
617{
Huang Shijiee8001632012-11-16 16:03:53 +0800618 if (auart_dma_enabled(s))
619 return 0;
620
Huang Shijiee8001632012-11-16 16:03:53 +0800621 /* init for RX */
Shawn Guobcc20f92013-02-26 13:47:41 +0800622 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
Huang Shijiee8001632012-11-16 16:03:53 +0800623 if (!s->rx_dma_chan)
624 goto err_out;
625 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
626 if (!s->rx_dma_buf)
627 goto err_out;
628
629 /* init for TX */
Shawn Guobcc20f92013-02-26 13:47:41 +0800630 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
Huang Shijiee8001632012-11-16 16:03:53 +0800631 if (!s->tx_dma_chan)
632 goto err_out;
633 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
634 if (!s->tx_dma_buf)
635 goto err_out;
636
637 /* set the flags */
638 s->flags |= MXS_AUART_DMA_ENABLED;
639 dev_dbg(s->dev, "enabled the DMA support.");
640
Hector Palacios9987f762013-10-03 09:32:03 +0200641 /* The DMA buffer is now the FIFO the TTY subsystem can use */
642 s->port.fifosize = UART_XMIT_SIZE;
643
Huang Shijiee8001632012-11-16 16:03:53 +0800644 return 0;
645
646err_out:
647 mxs_auart_dma_exit_channel(s);
648 return -EINVAL;
649
650}
651
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200652#define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
653 UART_GPIO_RTS))
654#define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
655 UART_GPIO_CTS))
Sascha Hauer47d37d62011-01-11 15:54:54 +0100656static void mxs_auart_settermios(struct uart_port *u,
657 struct ktermios *termios,
658 struct ktermios *old)
659{
Huang Shijiee8001632012-11-16 16:03:53 +0800660 struct mxs_auart_port *s = to_auart_port(u);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100661 u32 bm, ctrl, ctrl2, div;
662 unsigned int cflag, baud;
663
664 cflag = termios->c_cflag;
665
666 ctrl = AUART_LINECTRL_FEN;
667 ctrl2 = readl(u->membase + AUART_CTRL2);
668
669 /* byte size */
670 switch (cflag & CSIZE) {
671 case CS5:
672 bm = 0;
673 break;
674 case CS6:
675 bm = 1;
676 break;
677 case CS7:
678 bm = 2;
679 break;
680 case CS8:
681 bm = 3;
682 break;
683 default:
684 return;
685 }
686
687 ctrl |= AUART_LINECTRL_WLEN(bm);
688
689 /* parity */
690 if (cflag & PARENB) {
691 ctrl |= AUART_LINECTRL_PEN;
692 if ((cflag & PARODD) == 0)
693 ctrl |= AUART_LINECTRL_EPS;
694 }
695
696 u->read_status_mask = 0;
697
698 if (termios->c_iflag & INPCK)
699 u->read_status_mask |= AUART_STAT_PERR;
Peter Hurleyef8b9dd2014-06-16 08:10:41 -0400700 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
Sascha Hauer47d37d62011-01-11 15:54:54 +0100701 u->read_status_mask |= AUART_STAT_BERR;
702
703 /*
704 * Characters to ignore
705 */
706 u->ignore_status_mask = 0;
707 if (termios->c_iflag & IGNPAR)
708 u->ignore_status_mask |= AUART_STAT_PERR;
709 if (termios->c_iflag & IGNBRK) {
710 u->ignore_status_mask |= AUART_STAT_BERR;
711 /*
712 * If we're ignoring parity and break indicators,
713 * ignore overruns too (for real raw support).
714 */
715 if (termios->c_iflag & IGNPAR)
716 u->ignore_status_mask |= AUART_STAT_OERR;
717 }
718
719 /*
720 * ignore all characters if CREAD is not set
721 */
722 if (cflag & CREAD)
723 ctrl2 |= AUART_CTRL2_RXE;
724 else
725 ctrl2 &= ~AUART_CTRL2_RXE;
726
727 /* figure out the stop bits requested */
728 if (cflag & CSTOPB)
729 ctrl |= AUART_LINECTRL_STP2;
730
731 /* figure out the hardware flow control settings */
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200732 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
Huang Shijiee8001632012-11-16 16:03:53 +0800733 if (cflag & CRTSCTS) {
734 /*
735 * The DMA has a bug(see errata:2836) in mx23.
736 * So we can not implement the DMA for auart in mx23,
737 * we can only implement the DMA support for auart
738 * in mx28.
739 */
Huang Shijieafab2202013-08-03 10:09:15 -0400740 if (is_imx28_auart(s)
Huang Shijie8418e672013-08-03 10:09:14 -0400741 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
Huang Shijiee8001632012-11-16 16:03:53 +0800742 if (!mxs_auart_dma_init(s))
743 /* enable DMA tranfer */
744 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
745 | AUART_CTRL2_DMAONERR;
746 }
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200747 /* Even if RTS is GPIO line RTSEN can be enabled because
748 * the pinctrl configuration decides about RTS pin function */
749 ctrl2 |= AUART_CTRL2_RTSEN;
750 if (CTS_AT_AUART())
751 ctrl2 |= AUART_CTRL2_CTSEN;
Huang Shijiee8001632012-11-16 16:03:53 +0800752 }
Sascha Hauer47d37d62011-01-11 15:54:54 +0100753
754 /* set baud rate */
755 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
756 div = u->uartclk * 32 / baud;
757 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
758 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
759
760 writel(ctrl, u->membase + AUART_LINECTRL);
761 writel(ctrl2, u->membase + AUART_CTRL2);
Lothar Waßmann8b979f72012-05-03 11:37:12 +0200762
763 uart_update_timeout(u, termios->c_cflag, baud);
Huang Shijiee8001632012-11-16 16:03:53 +0800764
765 /* prepare for the DMA RX. */
766 if (auart_dma_enabled(s) &&
767 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
768 if (!mxs_auart_dma_prep_rx(s)) {
769 /* Disable the normal RX interrupt. */
Huang Shijiea5919442012-11-22 15:06:29 +0800770 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
771 u->membase + AUART_INTR_CLR);
Huang Shijiee8001632012-11-16 16:03:53 +0800772 } else {
773 mxs_auart_dma_exit(s);
774 dev_err(s->dev, "We can not start up the DMA.\n");
775 }
776 }
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200777
778 /* CTS flow-control and modem-status interrupts */
779 if (UART_ENABLE_MS(u, termios->c_cflag))
780 mxs_auart_enable_ms(u);
781 else
782 mxs_auart_disable_ms(u);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100783}
784
Fabio Estevamf3006e42014-11-12 20:32:49 -0200785static void mxs_auart_set_ldisc(struct uart_port *port,
786 struct ktermios *termios)
Janusz Uzycki36a26272014-10-10 18:53:27 +0200787{
Fabio Estevamf3006e42014-11-12 20:32:49 -0200788 if (termios->c_line == N_PPS) {
Janusz Uzycki36a26272014-10-10 18:53:27 +0200789 port->flags |= UPF_HARDPPS_CD;
790 mxs_auart_enable_ms(port);
791 } else {
792 port->flags &= ~UPF_HARDPPS_CD;
793 }
794}
795
Sascha Hauer47d37d62011-01-11 15:54:54 +0100796static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
797{
Uwe Kleine-Königd970d7f2013-07-04 11:28:51 +0200798 u32 istat;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100799 struct mxs_auart_port *s = context;
Janusz Uzycki08f937f2014-11-14 23:24:33 +0100800 u32 mctrl_temp = s->mctrl_prev;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100801 u32 stat = readl(s->port.membase + AUART_STAT);
802
Uwe Kleine-Königd970d7f2013-07-04 11:28:51 +0200803 istat = readl(s->port.membase + AUART_INTR);
804
805 /* ack irq */
806 writel(istat & (AUART_INTR_RTIS
807 | AUART_INTR_TXIS
808 | AUART_INTR_RXIS
809 | AUART_INTR_CTSMIS),
810 s->port.membase + AUART_INTR_CLR);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100811
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200812 /*
813 * Dealing with GPIO interrupt
814 */
815 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
816 irq == s->gpio_irq[UART_GPIO_DCD] ||
817 irq == s->gpio_irq[UART_GPIO_DSR] ||
818 irq == s->gpio_irq[UART_GPIO_RI])
819 mxs_auart_modem_status(s,
Janusz Uzycki08f937f2014-11-14 23:24:33 +0100820 mctrl_gpio_get(s->gpios, &mctrl_temp));
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200821
Sascha Hauer47d37d62011-01-11 15:54:54 +0100822 if (istat & AUART_INTR_CTSMIS) {
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200823 if (CTS_AT_AUART() && s->ms_irq_enabled)
Janusz Uzycki7c573d72014-10-10 18:53:25 +0200824 uart_handle_cts_change(&s->port,
825 stat & AUART_STAT_CTS);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100826 writel(AUART_INTR_CTSMIS,
827 s->port.membase + AUART_INTR_CLR);
828 istat &= ~AUART_INTR_CTSMIS;
829 }
830
831 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
Huang Shijiea5919442012-11-22 15:06:29 +0800832 if (!auart_dma_enabled(s))
833 mxs_auart_rx_chars(s);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100834 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
835 }
836
837 if (istat & AUART_INTR_TXIS) {
838 mxs_auart_tx_chars(s);
839 istat &= ~AUART_INTR_TXIS;
840 }
841
Sascha Hauer47d37d62011-01-11 15:54:54 +0100842 return IRQ_HANDLED;
843}
844
845static void mxs_auart_reset(struct uart_port *u)
846{
847 int i;
848 unsigned int reg;
849
850 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
851
852 for (i = 0; i < 10000; i++) {
853 reg = readl(u->membase + AUART_CTRL0);
854 if (!(reg & AUART_CTRL0_SFTRST))
855 break;
856 udelay(3);
857 }
858 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
859}
860
861static int mxs_auart_startup(struct uart_port *u)
862{
Fabio Estevam9bbc3dc2013-12-02 01:17:58 -0200863 int ret;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100864 struct mxs_auart_port *s = to_auart_port(u);
865
Fabio Estevam9bbc3dc2013-12-02 01:17:58 -0200866 ret = clk_prepare_enable(s->clk);
867 if (ret)
868 return ret;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100869
870 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
871
872 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
873
874 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
875 u->membase + AUART_INTR);
876
Hector Palacios9987f762013-10-03 09:32:03 +0200877 /* Reset FIFO size (it could have changed if DMA was enabled) */
878 u->fifosize = MXS_AUART_FIFO_SIZE;
879
Sascha Hauer47d37d62011-01-11 15:54:54 +0100880 /*
881 * Enable fifo so all four bytes of a DMA word are written to
882 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
883 */
884 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
885
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200886 /* get initial status of modem lines */
887 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
888
889 s->ms_irq_enabled = false;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100890 return 0;
891}
892
893static void mxs_auart_shutdown(struct uart_port *u)
894{
895 struct mxs_auart_port *s = to_auart_port(u);
896
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200897 mxs_auart_disable_ms(u);
898
Huang Shijiee8001632012-11-16 16:03:53 +0800899 if (auart_dma_enabled(s))
900 mxs_auart_dma_exit(s);
901
Sascha Hauer47d37d62011-01-11 15:54:54 +0100902 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
903
Sascha Hauer47d37d62011-01-11 15:54:54 +0100904 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
905 u->membase + AUART_INTR_CLR);
906
Huang Shijie851b7142012-09-06 22:38:40 -0400907 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
908
Shawn Guoa4813772011-12-20 14:10:29 +0800909 clk_disable_unprepare(s->clk);
Sascha Hauer47d37d62011-01-11 15:54:54 +0100910}
911
912static unsigned int mxs_auart_tx_empty(struct uart_port *u)
913{
Janusz Uzycki2b310ec2014-11-18 18:37:13 +0100914 if ((readl(u->membase + AUART_STAT) &
915 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
Sascha Hauer47d37d62011-01-11 15:54:54 +0100916 return TIOCSER_TEMT;
Janusz Uzycki2b310ec2014-11-18 18:37:13 +0100917
918 return 0;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100919}
920
921static void mxs_auart_start_tx(struct uart_port *u)
922{
923 struct mxs_auart_port *s = to_auart_port(u);
924
925 /* enable transmitter */
926 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
927
928 mxs_auart_tx_chars(s);
929}
930
931static void mxs_auart_stop_tx(struct uart_port *u)
932{
933 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
934}
935
936static void mxs_auart_stop_rx(struct uart_port *u)
937{
938 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
939}
940
941static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
942{
943 if (ctl)
944 writel(AUART_LINECTRL_BRK,
945 u->membase + AUART_LINECTRL_SET);
946 else
947 writel(AUART_LINECTRL_BRK,
948 u->membase + AUART_LINECTRL_CLR);
949}
950
Sascha Hauer47d37d62011-01-11 15:54:54 +0100951static struct uart_ops mxs_auart_ops = {
952 .tx_empty = mxs_auart_tx_empty,
953 .start_tx = mxs_auart_start_tx,
954 .stop_tx = mxs_auart_stop_tx,
955 .stop_rx = mxs_auart_stop_rx,
Janusz Uzyckif9e42392014-10-10 18:53:26 +0200956 .enable_ms = mxs_auart_enable_ms,
Sascha Hauer47d37d62011-01-11 15:54:54 +0100957 .break_ctl = mxs_auart_break_ctl,
958 .set_mctrl = mxs_auart_set_mctrl,
959 .get_mctrl = mxs_auart_get_mctrl,
960 .startup = mxs_auart_startup,
961 .shutdown = mxs_auart_shutdown,
962 .set_termios = mxs_auart_settermios,
Janusz Uzycki36a26272014-10-10 18:53:27 +0200963 .set_ldisc = mxs_auart_set_ldisc,
Sascha Hauer47d37d62011-01-11 15:54:54 +0100964 .type = mxs_auart_type,
965 .release_port = mxs_auart_release_port,
966 .request_port = mxs_auart_request_port,
967 .config_port = mxs_auart_config_port,
968 .verify_port = mxs_auart_verify_port,
969};
970
971static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
972
973#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
974static void mxs_auart_console_putchar(struct uart_port *port, int ch)
975{
976 unsigned int to = 1000;
977
978 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
979 if (!to--)
980 break;
981 udelay(1);
982 }
983
984 writel(ch, port->membase + AUART_DATA);
985}
986
987static void
988auart_console_write(struct console *co, const char *str, unsigned int count)
989{
990 struct mxs_auart_port *s;
991 struct uart_port *port;
992 unsigned int old_ctrl0, old_ctrl2;
Uwe Kleine-König079a0362013-06-28 11:49:41 +0200993 unsigned int to = 20000;
Sascha Hauer47d37d62011-01-11 15:54:54 +0100994
Wolfram Sang4829e762013-04-19 21:12:17 +0200995 if (co->index >= MXS_AUART_PORTS || co->index < 0)
Sascha Hauer47d37d62011-01-11 15:54:54 +0100996 return;
997
998 s = auart_port[co->index];
999 port = &s->port;
1000
1001 clk_enable(s->clk);
1002
1003 /* First save the CR then disable the interrupts */
1004 old_ctrl2 = readl(port->membase + AUART_CTRL2);
1005 old_ctrl0 = readl(port->membase + AUART_CTRL0);
1006
1007 writel(AUART_CTRL0_CLKGATE,
1008 port->membase + AUART_CTRL0_CLR);
1009 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
1010 port->membase + AUART_CTRL2_SET);
1011
1012 uart_console_write(port, str, count, mxs_auart_console_putchar);
1013
Uwe Kleine-König079a0362013-06-28 11:49:41 +02001014 /* Finally, wait for transmitter to become empty ... */
Sascha Hauer47d37d62011-01-11 15:54:54 +01001015 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
Uwe Kleine-König079a0362013-06-28 11:49:41 +02001016 udelay(1);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001017 if (!to--)
1018 break;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001019 }
1020
Uwe Kleine-König079a0362013-06-28 11:49:41 +02001021 /*
1022 * ... and restore the TCR if we waited long enough for the transmitter
1023 * to be idle. This might keep the transmitter enabled although it is
1024 * unused, but that is better than to disable it while it is still
1025 * transmitting.
1026 */
1027 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
1028 writel(old_ctrl0, port->membase + AUART_CTRL0);
1029 writel(old_ctrl2, port->membase + AUART_CTRL2);
1030 }
Sascha Hauer47d37d62011-01-11 15:54:54 +01001031
1032 clk_disable(s->clk);
1033}
1034
1035static void __init
1036auart_console_get_options(struct uart_port *port, int *baud,
1037 int *parity, int *bits)
1038{
1039 unsigned int lcr_h, quot;
1040
1041 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
1042 return;
1043
1044 lcr_h = readl(port->membase + AUART_LINECTRL);
1045
1046 *parity = 'n';
1047 if (lcr_h & AUART_LINECTRL_PEN) {
1048 if (lcr_h & AUART_LINECTRL_EPS)
1049 *parity = 'e';
1050 else
1051 *parity = 'o';
1052 }
1053
1054 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1055 *bits = 7;
1056 else
1057 *bits = 8;
1058
1059 quot = ((readl(port->membase + AUART_LINECTRL)
1060 & AUART_LINECTRL_BAUD_DIVINT_MASK))
1061 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1062 quot |= ((readl(port->membase + AUART_LINECTRL)
1063 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1064 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1065 if (quot == 0)
1066 quot = 1;
1067
1068 *baud = (port->uartclk << 2) / quot;
1069}
1070
1071static int __init
1072auart_console_setup(struct console *co, char *options)
1073{
1074 struct mxs_auart_port *s;
1075 int baud = 9600;
1076 int bits = 8;
1077 int parity = 'n';
1078 int flow = 'n';
1079 int ret;
1080
1081 /*
1082 * Check whether an invalid uart number has been specified, and
1083 * if so, search for the first available port that does have
1084 * console support.
1085 */
1086 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1087 co->index = 0;
1088 s = auart_port[co->index];
1089 if (!s)
1090 return -ENODEV;
1091
Fabio Estevam9bbc3dc2013-12-02 01:17:58 -02001092 ret = clk_prepare_enable(s->clk);
1093 if (ret)
1094 return ret;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001095
1096 if (options)
1097 uart_parse_options(options, &baud, &parity, &bits, &flow);
1098 else
1099 auart_console_get_options(&s->port, &baud, &parity, &bits);
1100
1101 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1102
Shawn Guoa4813772011-12-20 14:10:29 +08001103 clk_disable_unprepare(s->clk);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001104
1105 return ret;
1106}
1107
1108static struct console auart_console = {
1109 .name = "ttyAPP",
1110 .write = auart_console_write,
1111 .device = uart_console_device,
1112 .setup = auart_console_setup,
1113 .flags = CON_PRINTBUFFER,
1114 .index = -1,
1115 .data = &auart_driver,
1116};
1117#endif
1118
1119static struct uart_driver auart_driver = {
1120 .owner = THIS_MODULE,
1121 .driver_name = "ttyAPP",
1122 .dev_name = "ttyAPP",
1123 .major = 0,
1124 .minor = 0,
1125 .nr = MXS_AUART_PORTS,
1126#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1127 .cons = &auart_console,
1128#endif
1129};
1130
Fabio Estevam1ea66072012-06-18 10:06:09 -03001131/*
1132 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1133 * could successfully get all information from dt or a negative errno.
1134 */
1135static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1136 struct platform_device *pdev)
1137{
1138 struct device_node *np = pdev->dev.of_node;
1139 int ret;
1140
1141 if (!np)
1142 /* no device tree device */
1143 return 1;
1144
1145 ret = of_alias_get_id(np, "serial");
1146 if (ret < 0) {
1147 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1148 return ret;
1149 }
1150 s->port.line = ret;
1151
Huang Shijie8418e672013-08-03 10:09:14 -04001152 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1153 set_bit(MXS_AUART_RTSCTS, &s->flags);
1154
Fabio Estevam1ea66072012-06-18 10:06:09 -03001155 return 0;
1156}
1157
Janusz Uzycki7c573d72014-10-10 18:53:25 +02001158static bool mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1159{
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001160 enum mctrl_gpio_idx i;
1161 struct gpio_desc *gpiod;
1162
Janusz Uzycki7c573d72014-10-10 18:53:25 +02001163 s->gpios = mctrl_gpio_init(dev, 0);
1164 if (IS_ERR_OR_NULL(s->gpios))
1165 return false;
1166
1167 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1168 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1169 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1170 dev_warn(dev,
1171 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1172 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1173 }
1174
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001175 for (i = 0; i < UART_GPIO_MAX; i++) {
1176 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1177 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1178 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1179 else
1180 s->gpio_irq[i] = -EINVAL;
1181 }
1182
Janusz Uzycki7c573d72014-10-10 18:53:25 +02001183 return true;
1184}
1185
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001186static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1187{
1188 enum mctrl_gpio_idx i;
1189
1190 for (i = 0; i < UART_GPIO_MAX; i++)
1191 if (s->gpio_irq[i] >= 0)
1192 free_irq(s->gpio_irq[i], s);
1193}
1194
1195static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1196{
1197 int *irq = s->gpio_irq;
1198 enum mctrl_gpio_idx i;
1199 int err = 0;
1200
1201 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1202 if (irq[i] < 0)
1203 continue;
1204
1205 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1206 err = request_irq(irq[i], mxs_auart_irq_handle,
1207 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1208 if (err)
1209 dev_err(s->dev, "%s - Can't get %d irq\n",
1210 __func__, irq[i]);
1211 }
1212
1213 /*
1214 * If something went wrong, rollback.
1215 */
1216 while (err && (--i >= 0))
1217 if (irq[i] >= 0)
1218 free_irq(irq[i], s);
1219
1220 return err;
1221}
1222
Bill Pemberton9671f092012-11-19 13:21:50 -05001223static int mxs_auart_probe(struct platform_device *pdev)
Sascha Hauer47d37d62011-01-11 15:54:54 +01001224{
Huang Shijief4b1f03b2012-11-16 16:03:52 +08001225 const struct of_device_id *of_id =
1226 of_match_device(mxs_auart_dt_ids, &pdev->dev);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001227 struct mxs_auart_port *s;
1228 u32 version;
Fabio Estevam5f9ba5b2015-01-14 14:39:09 -02001229 int ret, irq;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001230 struct resource *r;
1231
Fabio Estevam46778bc2014-11-27 17:08:31 -02001232 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
Fabio Estevam11387b02014-11-27 17:08:30 -02001233 if (!s)
1234 return -ENOMEM;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001235
Fabio Estevam1ea66072012-06-18 10:06:09 -03001236 ret = serial_mxs_probe_dt(s, pdev);
1237 if (ret > 0)
1238 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1239 else if (ret < 0)
Fabio Estevam46778bc2014-11-27 17:08:31 -02001240 return ret;
Fabio Estevam1ea66072012-06-18 10:06:09 -03001241
Huang Shijief4b1f03b2012-11-16 16:03:52 +08001242 if (of_id) {
1243 pdev->id_entry = of_id->data;
1244 s->devtype = pdev->id_entry->driver_data;
1245 }
1246
Fabio Estevam75beb262014-11-27 17:08:32 -02001247 s->clk = devm_clk_get(&pdev->dev, NULL);
Fabio Estevam46778bc2014-11-27 17:08:31 -02001248 if (IS_ERR(s->clk))
1249 return PTR_ERR(s->clk);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001250
1251 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Fabio Estevam75beb262014-11-27 17:08:32 -02001252 if (!r)
1253 return -ENXIO;
1254
Sascha Hauer47d37d62011-01-11 15:54:54 +01001255
1256 s->port.mapbase = r->start;
1257 s->port.membase = ioremap(r->start, resource_size(r));
1258 s->port.ops = &mxs_auart_ops;
1259 s->port.iotype = UPIO_MEM;
Hector Palacios9987f762013-10-03 09:32:03 +02001260 s->port.fifosize = MXS_AUART_FIFO_SIZE;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001261 s->port.uartclk = clk_get_rate(s->clk);
1262 s->port.type = PORT_IMX;
Wolfram Sang4c24f2c2013-04-19 21:06:20 +02001263 s->port.dev = s->dev = &pdev->dev;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001264
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001265 s->mctrl_prev = 0;
1266
Fabio Estevam6960cd42015-01-14 14:39:07 -02001267 irq = platform_get_irq(pdev, 0);
Fabio Estevam99c932c2015-01-14 14:39:08 -02001268 if (irq < 0)
1269 return irq;
1270
Fabio Estevam6960cd42015-01-14 14:39:07 -02001271 s->port.irq = irq;
1272 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
Fabio Estevam9e5df9f2014-11-27 17:08:33 -02001273 dev_name(&pdev->dev), s);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001274 if (ret)
Fabio Estevam75beb262014-11-27 17:08:32 -02001275 return ret;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001276
1277 platform_set_drvdata(pdev, s);
1278
Janusz Uzycki7c573d72014-10-10 18:53:25 +02001279 if (!mxs_auart_init_gpios(s, &pdev->dev))
1280 dev_err(&pdev->dev,
1281 "Failed to initialize GPIOs. The serial port may not work as expected\n");
1282
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001283 /*
1284 * Get the GPIO lines IRQ
1285 */
1286 ret = mxs_auart_request_gpio_irq(s);
1287 if (ret)
Fabio Estevam9e5df9f2014-11-27 17:08:33 -02001288 return ret;
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001289
Fabio Estevam1ea66072012-06-18 10:06:09 -03001290 auart_port[s->port.line] = s;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001291
1292 mxs_auart_reset(&s->port);
1293
1294 ret = uart_add_one_port(&auart_driver, &s->port);
1295 if (ret)
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001296 goto out_free_gpio_irq;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001297
1298 version = readl(s->port.membase + AUART_VERSION);
1299 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1300 (version >> 24) & 0xff,
1301 (version >> 16) & 0xff, version & 0xffff);
1302
1303 return 0;
1304
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001305out_free_gpio_irq:
1306 mxs_auart_free_gpio_irq(s);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001307 auart_port[pdev->id] = NULL;
Sascha Hauer47d37d62011-01-11 15:54:54 +01001308 return ret;
1309}
1310
Bill Pembertonae8d8a12012-11-19 13:26:18 -05001311static int mxs_auart_remove(struct platform_device *pdev)
Sascha Hauer47d37d62011-01-11 15:54:54 +01001312{
1313 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1314
1315 uart_remove_one_port(&auart_driver, &s->port);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001316 auart_port[pdev->id] = NULL;
Janusz Uzyckif9e42392014-10-10 18:53:26 +02001317 mxs_auart_free_gpio_irq(s);
Sascha Hauer47d37d62011-01-11 15:54:54 +01001318
1319 return 0;
1320}
1321
1322static struct platform_driver mxs_auart_driver = {
1323 .probe = mxs_auart_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -05001324 .remove = mxs_auart_remove,
Sascha Hauer47d37d62011-01-11 15:54:54 +01001325 .driver = {
1326 .name = "mxs-auart",
Fabio Estevam1ea66072012-06-18 10:06:09 -03001327 .of_match_table = mxs_auart_dt_ids,
Sascha Hauer47d37d62011-01-11 15:54:54 +01001328 },
1329};
1330
1331static int __init mxs_auart_init(void)
1332{
1333 int r;
1334
1335 r = uart_register_driver(&auart_driver);
1336 if (r)
1337 goto out;
1338
1339 r = platform_driver_register(&mxs_auart_driver);
1340 if (r)
1341 goto out_err;
1342
1343 return 0;
1344out_err:
1345 uart_unregister_driver(&auart_driver);
1346out:
1347 return r;
1348}
1349
1350static void __exit mxs_auart_exit(void)
1351{
1352 platform_driver_unregister(&mxs_auart_driver);
1353 uart_unregister_driver(&auart_driver);
1354}
1355
1356module_init(mxs_auart_init);
1357module_exit(mxs_auart_exit);
1358MODULE_LICENSE("GPL");
1359MODULE_DESCRIPTION("Freescale MXS application uart driver");
Fabio Estevam1ea66072012-06-18 10:06:09 -03001360MODULE_ALIAS("platform:mxs-auart");