Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 2 | * drivers/net/ibm_emac/ibm_emac_mal.c |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 4 | * Memory Access Layer (MAL) support |
| 5 | * |
| 6 | * Copyright (c) 2004, 2005 Zultys Technologies. |
| 7 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 9 | * Based on original work by |
| 10 | * Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
| 11 | * David Gibson <hermes@gibson.dropbear.id.au>, |
| 12 | * |
| 13 | * Armin Kuster <akuster@mvista.com> |
| 14 | * Copyright 2002 MontaVista Softare Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify it |
| 17 | * under the terms of the GNU General Public License as published by the |
| 18 | * Free Software Foundation; either version 2 of the License, or (at your |
| 19 | * option) any later version. |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 20 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/config.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/netdevice.h> |
| 27 | #include <linux/init.h> |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 28 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <linux/dma-mapping.h> |
| 30 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include <asm/ocp.h> |
| 32 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 33 | #include "ibm_emac_core.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include "ibm_emac_mal.h" |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 35 | #include "ibm_emac_debug.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 37 | int __init mal_register_commac(struct ibm_ocp_mal *mal, |
| 38 | struct mal_commac *commac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | { |
| 40 | unsigned long flags; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 41 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 43 | MAL_DBG("%d: reg(%08x, %08x)" NL, mal->def->index, |
| 44 | commac->tx_chan_mask, commac->rx_chan_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 46 | /* Don't let multiple commacs claim the same channel(s) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | if ((mal->tx_chan_mask & commac->tx_chan_mask) || |
| 48 | (mal->rx_chan_mask & commac->rx_chan_mask)) { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 49 | local_irq_restore(flags); |
| 50 | printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n", |
| 51 | mal->def->index); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | return -EBUSY; |
| 53 | } |
| 54 | |
| 55 | mal->tx_chan_mask |= commac->tx_chan_mask; |
| 56 | mal->rx_chan_mask |= commac->rx_chan_mask; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 57 | list_add(&commac->list, &mal->list); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 59 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | return 0; |
| 61 | } |
| 62 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 63 | void __exit mal_unregister_commac(struct ibm_ocp_mal *mal, |
| 64 | struct mal_commac *commac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | { |
| 66 | unsigned long flags; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 67 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 69 | MAL_DBG("%d: unreg(%08x, %08x)" NL, mal->def->index, |
| 70 | commac->tx_chan_mask, commac->rx_chan_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | |
| 72 | mal->tx_chan_mask &= ~commac->tx_chan_mask; |
| 73 | mal->rx_chan_mask &= ~commac->rx_chan_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | list_del_init(&commac->list); |
| 75 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 76 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size) |
| 80 | { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 81 | struct ocp_func_mal_data *maldata = mal->def->additions; |
| 82 | BUG_ON(channel < 0 || channel >= maldata->num_rx_chans || |
| 83 | size > MAL_MAX_RX_SIZE); |
| 84 | |
| 85 | MAL_DBG("%d: set_rbcs(%d, %lu)" NL, mal->def->index, channel, size); |
| 86 | |
| 87 | if (size & 0xf) { |
| 88 | printk(KERN_WARNING |
| 89 | "mal%d: incorrect RX size %lu for the channel %d\n", |
| 90 | mal->def->index, size, channel); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | return -EINVAL; |
| 92 | } |
| 93 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 94 | set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | return 0; |
| 96 | } |
| 97 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 98 | int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel) |
| 99 | { |
| 100 | struct ocp_func_mal_data *maldata = mal->def->additions; |
| 101 | BUG_ON(channel < 0 || channel >= maldata->num_tx_chans); |
| 102 | return channel * NUM_TX_BUFF; |
| 103 | } |
| 104 | |
| 105 | int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel) |
| 106 | { |
| 107 | struct ocp_func_mal_data *maldata = mal->def->additions; |
| 108 | BUG_ON(channel < 0 || channel >= maldata->num_rx_chans); |
| 109 | return maldata->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF; |
| 110 | } |
| 111 | |
| 112 | void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel) |
| 113 | { |
| 114 | local_bh_disable(); |
| 115 | MAL_DBG("%d: enable_tx(%d)" NL, mal->def->index, channel); |
| 116 | set_mal_dcrn(mal, MAL_TXCASR, |
| 117 | get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel)); |
| 118 | local_bh_enable(); |
| 119 | } |
| 120 | |
| 121 | void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel) |
| 122 | { |
| 123 | set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel)); |
| 124 | MAL_DBG("%d: disable_tx(%d)" NL, mal->def->index, channel); |
| 125 | } |
| 126 | |
| 127 | void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel) |
| 128 | { |
| 129 | local_bh_disable(); |
| 130 | MAL_DBG("%d: enable_rx(%d)" NL, mal->def->index, channel); |
| 131 | set_mal_dcrn(mal, MAL_RXCASR, |
| 132 | get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel)); |
| 133 | local_bh_enable(); |
| 134 | } |
| 135 | |
| 136 | void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel) |
| 137 | { |
| 138 | set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); |
| 139 | MAL_DBG("%d: disable_rx(%d)" NL, mal->def->index, channel); |
| 140 | } |
| 141 | |
| 142 | void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac) |
| 143 | { |
| 144 | local_bh_disable(); |
| 145 | MAL_DBG("%d: poll_add(%p)" NL, mal->def->index, commac); |
| 146 | list_add_tail(&commac->poll_list, &mal->poll_list); |
| 147 | local_bh_enable(); |
| 148 | } |
| 149 | |
| 150 | void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac) |
| 151 | { |
| 152 | local_bh_disable(); |
| 153 | MAL_DBG("%d: poll_del(%p)" NL, mal->def->index, commac); |
| 154 | list_del(&commac->poll_list); |
| 155 | local_bh_enable(); |
| 156 | } |
| 157 | |
| 158 | /* synchronized by mal_poll() */ |
| 159 | static inline void mal_enable_eob_irq(struct ibm_ocp_mal *mal) |
| 160 | { |
| 161 | MAL_DBG2("%d: enable_irq" NL, mal->def->index); |
| 162 | set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE); |
| 163 | } |
| 164 | |
| 165 | /* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */ |
| 166 | static inline void mal_disable_eob_irq(struct ibm_ocp_mal *mal) |
| 167 | { |
| 168 | set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE); |
| 169 | MAL_DBG2("%d: disable_irq" NL, mal->def->index); |
| 170 | } |
| 171 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | static irqreturn_t mal_serr(int irq, void *dev_instance, struct pt_regs *regs) |
| 173 | { |
| 174 | struct ibm_ocp_mal *mal = dev_instance; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 175 | u32 esr = get_mal_dcrn(mal, MAL_ESR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | |
| 177 | /* Clear the error status register */ |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 178 | set_mal_dcrn(mal, MAL_ESR, esr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 180 | MAL_DBG("%d: SERR %08x" NL, mal->def->index, esr); |
| 181 | |
| 182 | if (esr & MAL_ESR_EVB) { |
| 183 | if (esr & MAL_ESR_DE) { |
| 184 | /* We ignore Descriptor error, |
| 185 | * TXDE or RXDE interrupt will be generated anyway. |
| 186 | */ |
| 187 | return IRQ_HANDLED; |
| 188 | } |
| 189 | |
| 190 | if (esr & MAL_ESR_PEIN) { |
| 191 | /* PLB error, it's probably buggy hardware or |
| 192 | * incorrect physical address in BD (i.e. bug) |
| 193 | */ |
| 194 | if (net_ratelimit()) |
| 195 | printk(KERN_ERR |
| 196 | "mal%d: system error, PLB (ESR = 0x%08x)\n", |
| 197 | mal->def->index, esr); |
| 198 | return IRQ_HANDLED; |
| 199 | } |
| 200 | |
| 201 | /* OPB error, it's probably buggy hardware or incorrect EBC setup */ |
| 202 | if (net_ratelimit()) |
| 203 | printk(KERN_ERR |
| 204 | "mal%d: system error, OPB (ESR = 0x%08x)\n", |
| 205 | mal->def->index, esr); |
| 206 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | return IRQ_HANDLED; |
| 208 | } |
| 209 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 210 | static inline void mal_schedule_poll(struct ibm_ocp_mal *mal) |
| 211 | { |
| 212 | if (likely(netif_rx_schedule_prep(&mal->poll_dev))) { |
| 213 | MAL_DBG2("%d: schedule_poll" NL, mal->def->index); |
| 214 | mal_disable_eob_irq(mal); |
| 215 | __netif_rx_schedule(&mal->poll_dev); |
| 216 | } else |
| 217 | MAL_DBG2("%d: already in poll" NL, mal->def->index); |
| 218 | } |
| 219 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | static irqreturn_t mal_txeob(int irq, void *dev_instance, struct pt_regs *regs) |
| 221 | { |
| 222 | struct ibm_ocp_mal *mal = dev_instance; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 223 | u32 r = get_mal_dcrn(mal, MAL_TXEOBISR); |
| 224 | MAL_DBG2("%d: txeob %08x" NL, mal->def->index, r); |
| 225 | mal_schedule_poll(mal); |
| 226 | set_mal_dcrn(mal, MAL_TXEOBISR, r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | return IRQ_HANDLED; |
| 228 | } |
| 229 | |
| 230 | static irqreturn_t mal_rxeob(int irq, void *dev_instance, struct pt_regs *regs) |
| 231 | { |
| 232 | struct ibm_ocp_mal *mal = dev_instance; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 233 | u32 r = get_mal_dcrn(mal, MAL_RXEOBISR); |
| 234 | MAL_DBG2("%d: rxeob %08x" NL, mal->def->index, r); |
| 235 | mal_schedule_poll(mal); |
| 236 | set_mal_dcrn(mal, MAL_RXEOBISR, r); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | return IRQ_HANDLED; |
| 238 | } |
| 239 | |
| 240 | static irqreturn_t mal_txde(int irq, void *dev_instance, struct pt_regs *regs) |
| 241 | { |
| 242 | struct ibm_ocp_mal *mal = dev_instance; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 243 | u32 deir = get_mal_dcrn(mal, MAL_TXDEIR); |
| 244 | set_mal_dcrn(mal, MAL_TXDEIR, deir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 246 | MAL_DBG("%d: txde %08x" NL, mal->def->index, deir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 248 | if (net_ratelimit()) |
| 249 | printk(KERN_ERR |
| 250 | "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n", |
| 251 | mal->def->index, deir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | |
| 253 | return IRQ_HANDLED; |
| 254 | } |
| 255 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | static irqreturn_t mal_rxde(int irq, void *dev_instance, struct pt_regs *regs) |
| 257 | { |
| 258 | struct ibm_ocp_mal *mal = dev_instance; |
| 259 | struct list_head *l; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 260 | u32 deir = get_mal_dcrn(mal, MAL_RXDEIR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 262 | MAL_DBG("%d: rxde %08x" NL, mal->def->index, deir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 264 | list_for_each(l, &mal->list) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | struct mal_commac *mc = list_entry(l, struct mal_commac, list); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | if (deir & mc->rx_chan_mask) { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 267 | mc->rx_stopped = 1; |
| 268 | mc->ops->rxde(mc->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | } |
| 270 | } |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 271 | |
| 272 | mal_schedule_poll(mal); |
| 273 | set_mal_dcrn(mal, MAL_RXDEIR, deir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | |
| 275 | return IRQ_HANDLED; |
| 276 | } |
| 277 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 278 | static int mal_poll(struct net_device *ndev, int *budget) |
| 279 | { |
| 280 | struct ibm_ocp_mal *mal = ndev->priv; |
| 281 | struct list_head *l; |
| 282 | int rx_work_limit = min(ndev->quota, *budget), received = 0, done; |
| 283 | |
| 284 | MAL_DBG2("%d: poll(%d) %d ->" NL, mal->def->index, *budget, |
| 285 | rx_work_limit); |
| 286 | again: |
| 287 | /* Process TX skbs */ |
| 288 | list_for_each(l, &mal->poll_list) { |
| 289 | struct mal_commac *mc = |
| 290 | list_entry(l, struct mal_commac, poll_list); |
| 291 | mc->ops->poll_tx(mc->dev); |
| 292 | } |
| 293 | |
| 294 | /* Process RX skbs. |
| 295 | * We _might_ need something more smart here to enforce polling fairness. |
| 296 | */ |
| 297 | list_for_each(l, &mal->poll_list) { |
| 298 | struct mal_commac *mc = |
| 299 | list_entry(l, struct mal_commac, poll_list); |
| 300 | int n = mc->ops->poll_rx(mc->dev, rx_work_limit); |
| 301 | if (n) { |
| 302 | received += n; |
| 303 | rx_work_limit -= n; |
| 304 | if (rx_work_limit <= 0) { |
| 305 | done = 0; |
| 306 | goto more_work; // XXX What if this is the last one ? |
| 307 | } |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | /* We need to disable IRQs to protect from RXDE IRQ here */ |
| 312 | local_irq_disable(); |
| 313 | __netif_rx_complete(ndev); |
| 314 | mal_enable_eob_irq(mal); |
| 315 | local_irq_enable(); |
| 316 | |
| 317 | done = 1; |
| 318 | |
| 319 | /* Check for "rotting" packet(s) */ |
| 320 | list_for_each(l, &mal->poll_list) { |
| 321 | struct mal_commac *mc = |
| 322 | list_entry(l, struct mal_commac, poll_list); |
| 323 | if (unlikely(mc->ops->peek_rx(mc->dev) || mc->rx_stopped)) { |
| 324 | MAL_DBG2("%d: rotting packet" NL, mal->def->index); |
| 325 | if (netif_rx_reschedule(ndev, received)) |
| 326 | mal_disable_eob_irq(mal); |
| 327 | else |
| 328 | MAL_DBG2("%d: already in poll list" NL, |
| 329 | mal->def->index); |
| 330 | |
| 331 | if (rx_work_limit > 0) |
| 332 | goto again; |
| 333 | else |
| 334 | goto more_work; |
| 335 | } |
| 336 | mc->ops->poll_tx(mc->dev); |
| 337 | } |
| 338 | |
| 339 | more_work: |
| 340 | ndev->quota -= received; |
| 341 | *budget -= received; |
| 342 | |
| 343 | MAL_DBG2("%d: poll() %d <- %d" NL, mal->def->index, *budget, |
| 344 | done ? 0 : 1); |
| 345 | return done ? 0 : 1; |
| 346 | } |
| 347 | |
| 348 | static void mal_reset(struct ibm_ocp_mal *mal) |
| 349 | { |
| 350 | int n = 10; |
| 351 | MAL_DBG("%d: reset" NL, mal->def->index); |
| 352 | |
| 353 | set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR); |
| 354 | |
| 355 | /* Wait for reset to complete (1 system clock) */ |
| 356 | while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n) |
| 357 | --n; |
| 358 | |
| 359 | if (unlikely(!n)) |
| 360 | printk(KERN_ERR "mal%d: reset timeout\n", mal->def->index); |
| 361 | } |
| 362 | |
| 363 | int mal_get_regs_len(struct ibm_ocp_mal *mal) |
| 364 | { |
| 365 | return sizeof(struct emac_ethtool_regs_subhdr) + |
| 366 | sizeof(struct ibm_mal_regs); |
| 367 | } |
| 368 | |
| 369 | void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf) |
| 370 | { |
| 371 | struct emac_ethtool_regs_subhdr *hdr = buf; |
| 372 | struct ibm_mal_regs *regs = (struct ibm_mal_regs *)(hdr + 1); |
| 373 | struct ocp_func_mal_data *maldata = mal->def->additions; |
| 374 | int i; |
| 375 | |
| 376 | hdr->version = MAL_VERSION; |
| 377 | hdr->index = mal->def->index; |
| 378 | |
| 379 | regs->tx_count = maldata->num_tx_chans; |
| 380 | regs->rx_count = maldata->num_rx_chans; |
| 381 | |
| 382 | regs->cfg = get_mal_dcrn(mal, MAL_CFG); |
| 383 | regs->esr = get_mal_dcrn(mal, MAL_ESR); |
| 384 | regs->ier = get_mal_dcrn(mal, MAL_IER); |
| 385 | regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR); |
| 386 | regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR); |
| 387 | regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR); |
| 388 | regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR); |
| 389 | regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR); |
| 390 | regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR); |
| 391 | regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR); |
| 392 | regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR); |
| 393 | |
| 394 | for (i = 0; i < regs->tx_count; ++i) |
| 395 | regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i)); |
| 396 | |
| 397 | for (i = 0; i < regs->rx_count; ++i) { |
| 398 | regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i)); |
| 399 | regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i)); |
| 400 | } |
| 401 | return regs + 1; |
| 402 | } |
| 403 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | static int __init mal_probe(struct ocp_device *ocpdev) |
| 405 | { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 406 | struct ibm_ocp_mal *mal; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | struct ocp_func_mal_data *maldata; |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 408 | int err = 0, i, bd_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 410 | MAL_DBG("%d: probe" NL, ocpdev->def->index); |
| 411 | |
| 412 | maldata = ocpdev->def->additions; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | if (maldata == NULL) { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 414 | printk(KERN_ERR "mal%d: missing additional data!\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | ocpdev->def->index); |
| 416 | return -ENODEV; |
| 417 | } |
| 418 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 419 | mal = kzalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL); |
| 420 | if (!mal) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | printk(KERN_ERR |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 422 | "mal%d: out of memory allocating MAL structure!\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | ocpdev->def->index); |
| 424 | return -ENOMEM; |
| 425 | } |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 426 | mal->dcrbase = maldata->dcr_base; |
| 427 | mal->def = ocpdev->def; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 429 | INIT_LIST_HEAD(&mal->poll_list); |
| 430 | set_bit(__LINK_STATE_START, &mal->poll_dev.state); |
| 431 | mal->poll_dev.weight = CONFIG_IBM_EMAC_POLL_WEIGHT; |
| 432 | mal->poll_dev.poll = mal_poll; |
| 433 | mal->poll_dev.priv = mal; |
| 434 | atomic_set(&mal->poll_dev.refcnt, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 436 | INIT_LIST_HEAD(&mal->list); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 438 | /* Load power-on reset defaults */ |
| 439 | mal_reset(mal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | |
| 441 | /* Set the MAL configuration register */ |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 442 | set_mal_dcrn(mal, MAL_CFG, MAL_CFG_DEFAULT | MAL_CFG_PLBB | |
| 443 | MAL_CFG_OPBBL | MAL_CFG_LEA); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 445 | mal_enable_eob_irq(mal); |
| 446 | |
| 447 | /* Allocate space for BD rings */ |
| 448 | BUG_ON(maldata->num_tx_chans <= 0 || maldata->num_tx_chans > 32); |
| 449 | BUG_ON(maldata->num_rx_chans <= 0 || maldata->num_rx_chans > 32); |
| 450 | bd_size = sizeof(struct mal_descriptor) * |
| 451 | (NUM_TX_BUFF * maldata->num_tx_chans + |
| 452 | NUM_RX_BUFF * maldata->num_rx_chans); |
| 453 | mal->bd_virt = |
| 454 | dma_alloc_coherent(&ocpdev->dev, bd_size, &mal->bd_dma, GFP_KERNEL); |
| 455 | |
| 456 | if (!mal->bd_virt) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | printk(KERN_ERR |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 458 | "mal%d: out of memory allocating RX/TX descriptors!\n", |
| 459 | mal->def->index); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | err = -ENOMEM; |
| 461 | goto fail; |
| 462 | } |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 463 | memset(mal->bd_virt, 0, bd_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 465 | for (i = 0; i < maldata->num_tx_chans; ++i) |
| 466 | set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma + |
| 467 | sizeof(struct mal_descriptor) * |
| 468 | mal_tx_bd_offset(mal, i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 470 | for (i = 0; i < maldata->num_rx_chans; ++i) |
| 471 | set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma + |
| 472 | sizeof(struct mal_descriptor) * |
| 473 | mal_rx_bd_offset(mal, i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | |
| 475 | err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal); |
| 476 | if (err) |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 477 | goto fail2; |
| 478 | err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE", mal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | if (err) |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 480 | goto fail3; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal); |
| 482 | if (err) |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 483 | goto fail4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal); |
| 485 | if (err) |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 486 | goto fail5; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal); |
| 488 | if (err) |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 489 | goto fail6; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 491 | /* Enable all MAL SERR interrupt sources */ |
| 492 | set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 494 | /* Advertise this instance to the rest of the world */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | ocp_set_drvdata(ocpdev, mal); |
| 496 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 497 | mal_dbg_register(mal->def->index, mal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 499 | printk(KERN_INFO "mal%d: initialized, %d TX channels, %d RX channels\n", |
| 500 | mal->def->index, maldata->num_tx_chans, maldata->num_rx_chans); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | return 0; |
| 502 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 503 | fail6: |
| 504 | free_irq(maldata->rxde_irq, mal); |
| 505 | fail5: |
| 506 | free_irq(maldata->txeob_irq, mal); |
| 507 | fail4: |
| 508 | free_irq(maldata->txde_irq, mal); |
| 509 | fail3: |
| 510 | free_irq(maldata->serr_irq, mal); |
| 511 | fail2: |
| 512 | dma_free_coherent(&ocpdev->dev, bd_size, mal->bd_virt, mal->bd_dma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | fail: |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 514 | kfree(mal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | return err; |
| 516 | } |
| 517 | |
| 518 | static void __exit mal_remove(struct ocp_device *ocpdev) |
| 519 | { |
| 520 | struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev); |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 521 | struct ocp_func_mal_data *maldata = mal->def->additions; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 523 | MAL_DBG("%d: remove" NL, mal->def->index); |
| 524 | |
| 525 | /* Syncronize with scheduled polling, |
| 526 | stolen from net/core/dev.c:dev_close() |
| 527 | */ |
| 528 | clear_bit(__LINK_STATE_START, &mal->poll_dev.state); |
| 529 | netif_poll_disable(&mal->poll_dev); |
| 530 | |
| 531 | if (!list_empty(&mal->list)) { |
| 532 | /* This is *very* bad */ |
| 533 | printk(KERN_EMERG |
| 534 | "mal%d: commac list is not empty on remove!\n", |
| 535 | mal->def->index); |
| 536 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | |
| 538 | ocp_set_drvdata(ocpdev, NULL); |
| 539 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | free_irq(maldata->serr_irq, mal); |
| 541 | free_irq(maldata->txde_irq, mal); |
| 542 | free_irq(maldata->txeob_irq, mal); |
| 543 | free_irq(maldata->rxde_irq, mal); |
| 544 | free_irq(maldata->rxeob_irq, mal); |
| 545 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 546 | mal_reset(mal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 548 | mal_dbg_register(mal->def->index, NULL); |
| 549 | |
| 550 | dma_free_coherent(&ocpdev->dev, |
| 551 | sizeof(struct mal_descriptor) * |
| 552 | (NUM_TX_BUFF * maldata->num_tx_chans + |
| 553 | NUM_RX_BUFF * maldata->num_rx_chans), mal->bd_virt, |
| 554 | mal->bd_dma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | |
| 556 | kfree(mal); |
| 557 | } |
| 558 | |
| 559 | /* Structure for a device driver */ |
| 560 | static struct ocp_device_id mal_ids[] = { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 561 | { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_MAL }, |
| 562 | { .vendor = OCP_VENDOR_INVALID} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | }; |
| 564 | |
| 565 | static struct ocp_driver mal_driver = { |
| 566 | .name = "mal", |
| 567 | .id_table = mal_ids, |
| 568 | |
| 569 | .probe = mal_probe, |
| 570 | .remove = mal_remove, |
| 571 | }; |
| 572 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 573 | int __init mal_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 575 | MAL_DBG(": init" NL); |
| 576 | return ocp_register_driver(&mal_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | } |
| 578 | |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 579 | void __exit mal_exit(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | { |
Eugene Surovegin | 37448f7 | 2005-10-10 16:58:14 -0700 | [diff] [blame] | 581 | MAL_DBG(": exit" NL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | ocp_unregister_driver(&mal_driver); |
| 583 | } |