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gerrit-public.fairphone.software / kernel / msm-4.9 / 5fb379ee67a7ec55ff65b467b472f3d69b60ba16 / . / drivers / net / benet / be_hw.h
blob: b02e805c1db37c8e645510b6b479905b74d19e56 [file] [log] [blame]
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700[diff] [blame]1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/********* Mailbox door bell *************/
19/* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
26 * queue entry.
27 */
28#define MPU_MAILBOX_DB_OFFSET 0x160
29#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
31
32#define MPU_EP_CONTROL 0
33
34/********** MPU semphore ******************/
35#define MPU_EP_SEMAPHORE_OFFSET 0xac
36#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37#define EP_SEMAPHORE_POST_ERR_MASK 0x1
38#define EP_SEMAPHORE_POST_ERR_SHIFT 31
39/* MPU semphore POST stage values */
40#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
41#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
42#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
43#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
44
45/********* Memory BAR register ************/
46#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
47/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
48 * Disable" may still globally block interrupts in addition to individual
49 * interrupt masks; a mechanism for the device driver to block all interrupts
50 * atomically without having to arbitrate for the PCI Interrupt Disable bit
51 * with the OS.
52 */
53#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
54/* PCI physical function number */
55#define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */
56#define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26
57
58/********* Event Q door bell *************/
59#define DB_EQ_OFFSET DB_CQ_OFFSET
60#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
61/* Clear the interrupt for this eq */
62#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
63/* Must be 1 */
Sathya Perla5fb379e2009-06-18 00:02:59 +0000[diff] [blame^]64#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700[diff] [blame]65/* Number of event entries processed */
66#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
67/* Rearm bit */
68#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
69
70/********* Compl Q door bell *************/
71#define DB_CQ_OFFSET 0x120
72#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
73/* Number of event entries processed */
74#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
75/* Rearm bit */
76#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
77
78/********** TX ULP door bell *************/
79#define DB_TXULP1_OFFSET 0x60
80#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
81/* Number of tx entries posted */
82#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
83#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
84
85/********** RQ(erx) door bell ************/
86#define DB_RQ_OFFSET 0x100
87#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
88/* Number of rx frags posted */
89#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
90
Sathya Perla5fb379e2009-06-18 00:02:59 +0000[diff] [blame^]91/********** MCC door bell ************/
92#define DB_MCCQ_OFFSET 0x140
93#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
94/* Number of entries posted */
95#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
96
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700[diff] [blame]97/*
98 * BE descriptors: host memory data structures whose formats
99 * are hardwired in BE silicon.
100 */
101/* Event Queue Descriptor */
102#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
103#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
104#define EQ_ENTRY_RES_ID_SHIFT 16
105struct be_eq_entry {
106 u32 evt;
107};
108
109/* TX Queue Descriptor */
110#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
111struct be_eth_wrb {
112 u32 frag_pa_hi; /* dword 0 */
113 u32 frag_pa_lo; /* dword 1 */
114 u32 rsvd0; /* dword 2 */
115 u32 frag_len; /* dword 3: bits 0 - 15 */
116} __packed;
117
118/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
119 * actual structure is defined as a byte : used to calculate
120 * offset/shift/mask of each field */
121struct amap_eth_hdr_wrb {
122 u8 rsvd0[32]; /* dword 0 */
123 u8 rsvd1[32]; /* dword 1 */
124 u8 complete; /* dword 2 */
125 u8 event;
126 u8 crc;
127 u8 forward;
128 u8 ipsec;
129 u8 mgmt;
130 u8 ipcs;
131 u8 udpcs;
132 u8 tcpcs;
133 u8 lso;
134 u8 vlan;
135 u8 gso[2];
136 u8 num_wrb[5];
137 u8 lso_mss[14];
138 u8 len[16]; /* dword 3 */
139 u8 vlan_tag[16];
140} __packed;
141
142struct be_eth_hdr_wrb {
143 u32 dw[4];
144};
145
146/* TX Compl Queue Descriptor */
147
148/* Pseudo amap definition for eth_tx_compl in which each bit of the
149 * actual structure is defined as a byte: used to calculate
150 * offset/shift/mask of each field */
151struct amap_eth_tx_compl {
152 u8 wrb_index[16]; /* dword 0 */
153 u8 ct[2]; /* dword 0 */
154 u8 port[2]; /* dword 0 */
155 u8 rsvd0[8]; /* dword 0 */
156 u8 status[4]; /* dword 0 */
157 u8 user_bytes[16]; /* dword 1 */
158 u8 nwh_bytes[8]; /* dword 1 */
159 u8 lso; /* dword 1 */
160 u8 cast_enc[2]; /* dword 1 */
161 u8 rsvd1[5]; /* dword 1 */
162 u8 rsvd2[32]; /* dword 2 */
163 u8 pkts[16]; /* dword 3 */
164 u8 ringid[11]; /* dword 3 */
165 u8 hash_val[4]; /* dword 3 */
166 u8 valid; /* dword 3 */
167} __packed;
168
169struct be_eth_tx_compl {
170 u32 dw[4];
171};
172
173/* RX Queue Descriptor */
174struct be_eth_rx_d {
175 u32 fragpa_hi;
176 u32 fragpa_lo;
177};
178
179/* RX Compl Queue Descriptor */
180
181/* Pseudo amap definition for eth_rx_compl in which each bit of the
182 * actual structure is defined as a byte: used to calculate
183 * offset/shift/mask of each field */
184struct amap_eth_rx_compl {
185 u8 vlan_tag[16]; /* dword 0 */
186 u8 pktsize[14]; /* dword 0 */
187 u8 port; /* dword 0 */
188 u8 ip_opt; /* dword 0 */
189 u8 err; /* dword 1 */
190 u8 rsshp; /* dword 1 */
191 u8 ipf; /* dword 1 */
192 u8 tcpf; /* dword 1 */
193 u8 udpf; /* dword 1 */
194 u8 ipcksm; /* dword 1 */
195 u8 l4_cksm; /* dword 1 */
196 u8 ip_version; /* dword 1 */
197 u8 macdst[6]; /* dword 1 */
198 u8 vtp; /* dword 1 */
199 u8 rsvd0; /* dword 1 */
200 u8 fragndx[10]; /* dword 1 */
201 u8 ct[2]; /* dword 1 */
202 u8 sw; /* dword 1 */
203 u8 numfrags[3]; /* dword 1 */
204 u8 rss_flush; /* dword 2 */
205 u8 cast_enc[2]; /* dword 2 */
206 u8 qnq; /* dword 2 */
207 u8 rss_bank; /* dword 2 */
208 u8 rsvd1[23]; /* dword 2 */
209 u8 lro_pkt; /* dword 2 */
210 u8 rsvd2[2]; /* dword 2 */
211 u8 valid; /* dword 2 */
212 u8 rsshash[32]; /* dword 3 */
213} __packed;
214
215struct be_eth_rx_compl {
216 u32 dw[4];
217};