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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
Paul Walmsleyd8a94452009-12-08 16:21:29 -07004 * Copyright (C) 2005-2009 Texas Instruments, Inc.
Paul Walmsley530e5442011-02-25 15:39:28 -07005 * Copyright (C) 2004-2011 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
Paul Walmsley12706c52011-07-10 05:57:06 -060019#include <linux/kernel.h>
Paul Walmsleya135eaa2012-09-27 10:33:34 -060020#include <linux/list.h>
Paul Walmsley12706c52011-07-10 05:57:06 -060021
Paul Walmsleye10dd622012-09-27 10:33:35 -060022#include <linux/clkdev.h>
Mike Turquettef9ae32a2012-11-07 13:14:47 -080023#include <linux/clk-provider.h>
Paul Walmsleye10dd622012-09-27 10:33:35 -060024
25struct omap_clk {
26 u16 cpu;
27 struct clk_lookup lk;
28};
29
30#define CLK(dev, con, ck, cp) \
31 { \
32 .cpu = cp, \
33 .lk = { \
34 .dev_id = dev, \
35 .con_id = con, \
36 .clk = ck, \
37 }, \
38 }
39
40/* Platform flags for the clkdev-OMAP integration code */
41#define CK_242X (1 << 0)
42#define CK_243X (1 << 1) /* 243x, 253x */
43#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
44#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
45#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
46#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
47#define CK_443X (1 << 6)
48#define CK_TI816X (1 << 7)
49#define CK_446X (1 << 8)
50#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
51
52
53#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
54#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
55
Rajendra Nayakb5a23662012-11-10 16:58:40 -070056struct clockdomain;
57#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
58
Paul Walmsley8c725dc2012-09-16 10:45:54 -060059#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
60 static struct clk _name = { \
61 .name = #_name, \
62 .hw = &_name##_hw.hw, \
63 .parent_names = _parent_array_name, \
64 .num_parents = ARRAY_SIZE(_parent_array_name), \
65 .ops = &_clkops_name, \
66 };
67
Afzal Mohammed601155b2013-01-23 17:12:05 +053068#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
69 _clkops_name, _flags) \
70 static struct clk _name = { \
71 .name = #_name, \
72 .hw = &_name##_hw.hw, \
73 .parent_names = _parent_array_name, \
74 .num_parents = ARRAY_SIZE(_parent_array_name), \
75 .ops = &_clkops_name, \
76 .flags = _flags, \
77 };
78
Paul Walmsley8c725dc2012-09-16 10:45:54 -060079#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
80 static struct clk_hw_omap _name##_hw = { \
81 .hw = { \
82 .clk = &_name, \
83 }, \
84 .clkdm_name = _clkdm_name, \
85 };
86
87#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
88 _clksel_reg, _clksel_mask, \
89 _parent_names, _ops) \
90 static struct clk _name; \
91 static struct clk_hw_omap _name##_hw = { \
92 .hw = { \
93 .clk = &_name, \
94 }, \
95 .clksel = _clksel, \
96 .clksel_reg = _clksel_reg, \
97 .clksel_mask = _clksel_mask, \
98 .clkdm_name = _clkdm_name, \
99 }; \
100 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
101
102#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
103 _clksel_reg, _clksel_mask, \
104 _enable_reg, _enable_bit, \
105 _hwops, _parent_names, _ops) \
106 static struct clk _name; \
107 static struct clk_hw_omap _name##_hw = { \
108 .hw = { \
109 .clk = &_name, \
110 }, \
111 .ops = _hwops, \
112 .enable_reg = _enable_reg, \
113 .enable_bit = _enable_bit, \
114 .clksel = _clksel, \
115 .clksel_reg = _clksel_reg, \
116 .clksel_mask = _clksel_mask, \
117 .clkdm_name = _clkdm_name, \
118 }; \
119 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
120
121#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
122 _parent_ptr, _flags, \
123 _clksel_reg, _clksel_mask) \
124 static const struct clksel _name##_div[] = { \
125 { \
126 .parent = _parent_ptr, \
127 .rates = div31_1to31_rates \
128 }, \
129 { .parent = NULL }, \
130 }; \
131 static struct clk _name; \
132 static const char *_name##_parent_names[] = { \
133 _parent_name, \
134 }; \
135 static struct clk_hw_omap _name##_hw = { \
136 .hw = { \
137 .clk = &_name, \
138 }, \
139 .clksel = _name##_div, \
140 .clksel_reg = _clksel_reg, \
141 .clksel_mask = _clksel_mask, \
142 .ops = &clkhwops_omap4_dpllmx, \
143 }; \
144 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
145
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600146/* struct clksel_rate.flags possibilities */
147#define RATE_IN_242X (1 << 0)
148#define RATE_IN_243X (1 << 1)
149#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
150#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
151#define RATE_IN_36XX (1 << 4)
152#define RATE_IN_4430 (1 << 5)
153#define RATE_IN_TI816X (1 << 6)
154#define RATE_IN_4460 (1 << 7)
155#define RATE_IN_AM33XX (1 << 8)
156#define RATE_IN_TI814X (1 << 9)
157
158#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
159#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
160#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
161#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
162
163/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
164#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
165
166
167/**
168 * struct clksel_rate - register bitfield values corresponding to clk divisors
169 * @val: register bitfield value (shifted to bit 0)
170 * @div: clock divisor corresponding to @val
171 * @flags: (see "struct clksel_rate.flags possibilities" above)
172 *
173 * @val should match the value of a read from struct clk.clksel_reg
174 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
175 *
176 * @div is the divisor that should be applied to the parent clock's rate
177 * to produce the current clock's rate.
178 */
179struct clksel_rate {
180 u32 val;
181 u8 div;
182 u16 flags;
183};
184
185/**
186 * struct clksel - available parent clocks, and a pointer to their divisors
187 * @parent: struct clk * to a possible parent clock
188 * @rates: available divisors for this parent clock
189 *
190 * A struct clksel is always associated with one or more struct clks
191 * and one or more struct clksel_rates.
192 */
193struct clksel {
194 struct clk *parent;
195 const struct clksel_rate *rates;
196};
197
198/**
199 * struct dpll_data - DPLL registers and integration data
200 * @mult_div1_reg: register containing the DPLL M and N bitfields
201 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
202 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
203 * @clk_bypass: struct clk pointer to the clock's bypass clock input
204 * @clk_ref: struct clk pointer to the clock's reference clock input
205 * @control_reg: register containing the DPLL mode bitfield
206 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
207 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
208 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700209 * @last_rounded_m4xen: cache of the last M4X result of
210 * omap4_dpll_regm4xen_round_rate()
211 * @last_rounded_lpmode: cache of the last lpmode result of
212 * omap4_dpll_lpmode_recalc()
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600213 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
214 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
215 * @min_divider: minimum valid non-bypass divider value (actual)
216 * @max_divider: maximum valid non-bypass divider value (actual)
217 * @modes: possible values of @enable_mask
218 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
219 * @idlest_reg: register containing the DPLL idle status bitfield
220 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
221 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
222 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700223 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
224 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600225 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
226 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
227 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
228 * @flags: DPLL type/features (see below)
229 *
230 * Possible values for @flags:
231 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
232 *
233 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
234 *
235 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
236 * correct to only have one @clk_bypass pointer.
237 *
238 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
239 * @last_rounded_n) should be separated from the runtime-fixed fields
240 * and placed into a different structure, so that the runtime-fixed data
241 * can be placed into read-only space.
242 */
243struct dpll_data {
244 void __iomem *mult_div1_reg;
245 u32 mult_mask;
246 u32 div1_mask;
247 struct clk *clk_bypass;
248 struct clk *clk_ref;
249 void __iomem *control_reg;
250 u32 enable_mask;
251 unsigned long last_rounded_rate;
252 u16 last_rounded_m;
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700253 u8 last_rounded_m4xen;
254 u8 last_rounded_lpmode;
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600255 u16 max_multiplier;
256 u8 last_rounded_n;
257 u8 min_divider;
258 u16 max_divider;
259 u8 modes;
260 void __iomem *autoidle_reg;
261 void __iomem *idlest_reg;
262 u32 autoidle_mask;
263 u32 freqsel_mask;
264 u32 idlest_mask;
265 u32 dco_mask;
266 u32 sddiv_mask;
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700267 u32 lpmode_mask;
268 u32 m4xen_mask;
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600269 u8 auto_recal_bit;
270 u8 recal_en_bit;
271 u8 recal_st_bit;
272 u8 flags;
273};
274
275/*
276 * struct clk.flags possibilities
277 *
278 * XXX document the rest of the clock flags here
279 *
280 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
281 * bits share the same register. This flag allows the
282 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
283 * should be used. This is a temporary solution - a better approach
284 * would be to associate clock type-specific data with the clock,
285 * similar to the struct dpll_data approach.
286 */
287#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
288#define CLOCK_IDLE_CONTROL (1 << 1)
289#define CLOCK_NO_IDLE_PARENT (1 << 2)
290#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
291#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
292#define CLOCK_CLKOUTX2 (1 << 5)
293
Rajendra Nayakb5a23662012-11-10 16:58:40 -0700294/**
295 * struct clk_hw_omap - OMAP struct clk
296 * @node: list_head connecting this clock into the full clock list
297 * @enable_reg: register to write to enable the clock (see @enable_bit)
298 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
299 * @flags: see "struct clk.flags possibilities" above
300 * @clksel_reg: for clksel clks, register va containing src/divisor select
301 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
302 * @clksel: for clksel clks, pointer to struct clksel for this clock
303 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
304 * @clkdm_name: clockdomain name that this clock is contained in
305 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
306 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
307 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
308 *
309 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
310 * clock code converted to use clksel.
311 *
312 */
313
314struct clk_hw_omap_ops;
315
316struct clk_hw_omap {
317 struct clk_hw hw;
318 struct list_head node;
319 unsigned long fixed_rate;
320 u8 fixed_div;
321 void __iomem *enable_reg;
322 u8 enable_bit;
323 u8 flags;
324 void __iomem *clksel_reg;
325 u32 clksel_mask;
326 const struct clksel *clksel;
327 struct dpll_data *dpll_data;
328 const char *clkdm_name;
329 struct clockdomain *clkdm;
330 const struct clk_hw_omap_ops *ops;
331};
332
333struct clk_hw_omap_ops {
334 void (*find_idlest)(struct clk_hw_omap *oclk,
335 void __iomem **idlest_reg,
336 u8 *idlest_bit, u8 *idlest_val);
337 void (*find_companion)(struct clk_hw_omap *oclk,
338 void __iomem **other_reg,
339 u8 *other_bit);
340 void (*allow_idle)(struct clk_hw_omap *oclk);
341 void (*deny_idle)(struct clk_hw_omap *oclk);
342};
343
344unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
345 unsigned long parent_rate);
Paul Walmsley543d9372008-03-18 10:22:06 +0200346
Russell Kingc0bf3132009-02-19 13:29:22 +0000347/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
348#define CORE_CLK_SRC_32K 0x0
349#define CORE_CLK_SRC_DPLL 0x1
350#define CORE_CLK_SRC_DPLL_X2 0x2
351
352/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
353#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
354#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
355#define OMAP2XXX_EN_DPLL_LOCKED 0x3
356
357/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
358#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
359#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
360#define OMAP3XXX_EN_DPLL_LOCKED 0x7
361
Rajendra Nayak16975a72009-12-08 18:47:16 -0700362/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
363#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
364#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
365#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
366#define OMAP4XXX_EN_DPLL_LOCKED 0x7
367
Rajendra Nayaka1391d22009-12-08 18:47:16 -0700368/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
369#define DPLL_LOW_POWER_STOP 0x1
370#define DPLL_LOW_POWER_BYPASS 0x5
371#define DPLL_LOCKED 0x7
372
Richard Woodruff358965d2010-02-22 22:09:08 -0700373/* DPLL Type and DCO Selection Flags */
374#define DPLL_J_TYPE 0x1
Richard Woodruff358965d2010-02-22 22:09:08 -0700375
Mike Turquette32cc0022012-11-10 16:58:41 -0700376long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
377 unsigned long *parent_rate);
378unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
379int omap3_noncore_dpll_enable(struct clk_hw *hw);
380void omap3_noncore_dpll_disable(struct clk_hw *hw);
381int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
382 unsigned long parent_rate);
383u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
384void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
385void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
386unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
387 unsigned long parent_rate);
388int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
389void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
390void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
391unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
392 unsigned long parent_rate);
393long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
394 unsigned long target_rate,
395 unsigned long *parent_rate);
Paul Walmsley543d9372008-03-18 10:22:06 +0200396
Mike Turquette32cc0022012-11-10 16:58:41 -0700397void omap2_init_clk_clkdm(struct clk_hw *clk);
Paul Walmsley12706c52011-07-10 05:57:06 -0600398void __init omap2_clk_disable_clkdm_control(void);
Paul Walmsley435699d2010-05-18 18:40:24 -0600399
400/* clkt_clksel.c public functions */
Mike Turquette32cc0022012-11-10 16:58:41 -0700401u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
402 unsigned long target_rate,
403 u32 *new_div);
404u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
405unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
406long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
407 unsigned long *parent_rate);
408int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
409 unsigned long parent_rate);
410int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
Paul Walmsley435699d2010-05-18 18:40:24 -0600411
Paul Walmsley530e5442011-02-25 15:39:28 -0700412/* clkt_iclk.c public functions */
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530413extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
414extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
Paul Walmsley530e5442011-02-25 15:39:28 -0700415
Mike Turquette32cc0022012-11-10 16:58:41 -0700416u8 omap2_init_dpll_parent(struct clk_hw *hw);
417unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
Paul Walmsley435699d2010-05-18 18:40:24 -0600418
Mike Turquette32cc0022012-11-10 16:58:41 -0700419int omap2_dflt_clk_enable(struct clk_hw *hw);
420void omap2_dflt_clk_disable(struct clk_hw *hw);
421int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
422void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
423 void __iomem **other_reg,
424 u8 *other_bit);
425void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
426 void __iomem **idlest_reg,
427 u8 *idlest_bit, u8 *idlest_val);
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530428void omap2_init_clk_hw_omap_clocks(struct clk *clk);
429int omap2_clk_enable_autoidle_all(void);
430int omap2_clk_disable_autoidle_all(void);
Rajendra Nayak85774132012-06-01 14:02:49 +0530431void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
Paul Walmsley4d30e822010-02-22 22:09:36 -0700432int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
433void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
434 const char *core_ck_name,
435 const char *mpu_ck_name);
Paul Walmsley543d9372008-03-18 10:22:06 +0200436
Afzal Mohammed99541192011-12-13 10:46:43 -0800437extern u16 cpu_mask;
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700438
Russell Kingb36ee722008-11-04 17:59:52 +0000439extern const struct clkops clkops_omap2_dflt_wait;
Santosh Shilimkar7c43d542010-02-22 22:09:40 -0700440extern const struct clkops clkops_dummy;
Russell Kingbc51da42008-11-04 18:59:32 +0000441extern const struct clkops clkops_omap2_dflt;
Russell Kingb36ee722008-11-04 17:59:52 +0000442
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700443extern struct clk_functions omap2_clk_functions;
444
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700445extern const struct clksel_rate gpt_32k_rates[];
446extern const struct clksel_rate gpt_sys_rates[];
447extern const struct clksel_rate gfx_l3_rates[];
Paul Walmsley22411392011-02-25 15:52:04 -0700448extern const struct clksel_rate dsp_ick_rates[];
Rajendra Nayakcb268672012-11-06 15:41:08 -0700449extern struct clk dummy_ck;
Paul Walmsley543d9372008-03-18 10:22:06 +0200450
Mike Turquette32cc0022012-11-10 16:58:41 -0700451extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
452extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
453extern const struct clk_hw_omap_ops clkhwops_wait;
454extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530455extern const struct clk_hw_omap_ops clkhwops_iclk;
456extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
457extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
458extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
459extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
460extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
461extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
462extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
463extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
464extern const struct clk_hw_omap_ops clkhwops_apll54;
465extern const struct clk_hw_omap_ops clkhwops_apll96;
466extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
467extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
Paul Walmsley657ebfa2010-02-22 22:09:20 -0700468
Paul Walmsley571efa02012-05-29 15:26:40 +0530469/* clksel_rate blocks shared between OMAP44xx and AM33xx */
470extern const struct clksel_rate div_1_0_rates[];
Rajendra Nayakcb268672012-11-06 15:41:08 -0700471extern const struct clksel_rate div3_1to4_rates[];
Paul Walmsley571efa02012-05-29 15:26:40 +0530472extern const struct clksel_rate div_1_1_rates[];
473extern const struct clksel_rate div_1_2_rates[];
474extern const struct clksel_rate div_1_3_rates[];
475extern const struct clksel_rate div_1_4_rates[];
476extern const struct clksel_rate div31_1to31_rates[];
477
Vaibhav Hiremathe30384a2012-05-29 15:26:41 +0530478extern int am33xx_clk_init(void);
479
Mike Turquette32cc0022012-11-10 16:58:41 -0700480extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
481extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
Mike Turquette32cc0022012-11-10 16:58:41 -0700482
Paul Walmsley543d9372008-03-18 10:22:06 +0200483#endif