| Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This is a direct copy of the ev96100.h file, with a global |
| 3 | * search and replace. The numbers are the same. |
| 4 | * |
| 5 | * The reason I'm duplicating this is so that the 64120/96100 |
| 6 | * defines won't be confusing in the source code. |
| 7 | */ |
| 8 | #ifndef __ASM_MIPS_GT64120_H |
| 9 | #define __ASM_MIPS_GT64120_H |
| 10 | |
| 11 | /* |
| 12 | * This is the CPU physical memory map of PPMC Board: |
| 13 | * |
| 14 | * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) |
| 15 | * 0x1C000000-0x1C000000 - LED (CS0) |
| 16 | * 0x1C800000-0x1C800007 - UART 16550 port (CS1) |
| 17 | * 0x1F000000-0x1F000000 - MailBox (CS3) |
| 18 | * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) |
| 19 | */ |
| 20 | |
| 21 | #define WRPPMC_SDRAM_SCS0_BASE 0x00000000 |
| 22 | #define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 |
| 23 | |
| 24 | #define WRPPMC_UART16550_BASE 0x1C800000 |
| 25 | #define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ |
| 26 | |
| 27 | #define WRPPMC_LED_BASE 0x1C000000 |
| 28 | #define WRPPMC_MBOX_BASE 0x1F000000 |
| 29 | |
| 30 | #define WRPPMC_BOOTROM_BASE 0x1FC00000 |
| 31 | #define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ |
| 32 | |
| 33 | #define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ |
| 34 | #define WRPPMC_UART16550_IRQ 6 |
| 35 | #define WRPPMC_PCI_INTA_IRQ 3 |
| 36 | |
| 37 | /* |
| 38 | * PCI Bus I/O and Memory resources allocation |
| 39 | * |
| 40 | * NOTE: We only have PCI_0 hose interface |
| 41 | */ |
| 42 | #define GT_PCI_MEM_BASE 0x13000000UL |
| 43 | #define GT_PCI_MEM_SIZE 0x02000000UL |
| 44 | #define GT_PCI_IO_BASE 0x11000000UL |
| 45 | #define GT_PCI_IO_SIZE 0x02000000UL |
| 46 | #define GT_ISA_IO_BASE PCI_IO_BASE |
| 47 | |
| 48 | /* |
| 49 | * PCI interrupts will come in on either the INTA or INTD interrups lines, |
| 50 | * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our |
| 51 | * boards, they all either come in on IntD or they all come in on IntA, they |
| 52 | * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the |
| 53 | * "requested" interrupt numbers and go through the list whenever we get an |
| 54 | * IntA/D. |
| 55 | * |
| 56 | * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and |
| 57 | * INTD is 11. |
| 58 | */ |
| 59 | #define GT_TIMER 4 |
| 60 | #define GT_INTA 2 |
| 61 | #define GT_INTD 5 |
| 62 | |
| 63 | #ifndef __ASSEMBLY__ |
| 64 | |
| 65 | /* |
| 66 | * GT64120 internal register space base address |
| 67 | */ |
| 68 | extern unsigned long gt64120_base; |
| 69 | |
| 70 | #define GT64120_BASE (gt64120_base) |
| 71 | |
| 72 | /* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ |
| 73 | #undef WRPPMC_EARLY_DEBUG |
| 74 | |
| 75 | #ifdef WRPPMC_EARLY_DEBUG |
| 76 | extern void wrppmc_led_on(int mask); |
| 77 | extern void wrppmc_led_off(int mask); |
| 78 | extern void wrppmc_early_printk(const char *fmt, ...); |
| 79 | #else |
| 80 | #define wrppmc_early_printk(fmt, ...) do {} while (0) |
| 81 | #endif /* WRPPMC_EARLY_DEBUG */ |
| 82 | |
| 83 | #endif /* __ASSEMBLY__ */ |
| 84 | #endif /* __ASM_MIPS_GT64120_H */ |