| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h |
| 3 | * |
| 4 | * Interface for smsc fdc48m81x Super IO chip |
| 5 | * |
| 6 | * Author: MontaVista Software, Inc. source@mvista.com |
| 7 | * |
| 8 | * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under |
| 9 | * the terms of the GNU General Public License version 2. This program |
| 10 | * is licensed "as is" without any warranty of any kind, whether express |
| 11 | * or implied. |
| 12 | * |
| 13 | * Copyright (C) 2004 MontaVista Software Inc. |
| 14 | * Manish Lachwani, mlachwani@mvista.com |
| 15 | */ |
| 16 | |
| 17 | #ifndef _SMSC_FDC37M81X_H_ |
| 18 | #define _SMSC_FDC37M81X_H_ |
| 19 | |
| 20 | /* Common Registers */ |
| 21 | #define SMSC_FDC37M81X_CONFIG_INDEX 0x00 |
| 22 | #define SMSC_FDC37M81X_CONFIG_DATA 0x01 |
| 23 | #define SMSC_FDC37M81X_CONF 0x02 |
| 24 | #define SMSC_FDC37M81X_INDEX 0x03 |
| 25 | #define SMSC_FDC37M81X_DNUM 0x07 |
| 26 | #define SMSC_FDC37M81X_DID 0x20 |
| 27 | #define SMSC_FDC37M81X_DREV 0x21 |
| 28 | #define SMSC_FDC37M81X_PCNT 0x22 |
| 29 | #define SMSC_FDC37M81X_PMGT 0x23 |
| 30 | #define SMSC_FDC37M81X_OSC 0x24 |
| 31 | #define SMSC_FDC37M81X_CONFPA0 0x26 |
| 32 | #define SMSC_FDC37M81X_CONFPA1 0x27 |
| 33 | #define SMSC_FDC37M81X_TEST4 0x2B |
| 34 | #define SMSC_FDC37M81X_TEST5 0x2C |
| 35 | #define SMSC_FDC37M81X_TEST1 0x2D |
| 36 | #define SMSC_FDC37M81X_TEST2 0x2E |
| 37 | #define SMSC_FDC37M81X_TEST3 0x2F |
| 38 | |
| 39 | /* Logical device numbers */ |
| 40 | #define SMSC_FDC37M81X_FDD 0x00 |
| 41 | #define SMSC_FDC37M81X_PARALLEL 0x03 |
| 42 | #define SMSC_FDC37M81X_SERIAL1 0x04 |
| 43 | #define SMSC_FDC37M81X_SERIAL2 0x05 |
| 44 | #define SMSC_FDC37M81X_KBD 0x07 |
| 45 | #define SMSC_FDC37M81X_AUXIO 0x08 |
| 46 | #define SMSC_FDC37M81X_NONE 0xff |
| 47 | |
| 48 | /* Logical device Config Registers */ |
| 49 | #define SMSC_FDC37M81X_ACTIVE 0x30 |
| 50 | #define SMSC_FDC37M81X_BASEADDR0 0x60 |
| 51 | #define SMSC_FDC37M81X_BASEADDR1 0x61 |
| 52 | #define SMSC_FDC37M81X_INT 0x70 |
| 53 | #define SMSC_FDC37M81X_INT2 0x72 |
| 54 | #define SMSC_FDC37M81X_LDCR_F0 0xF0 |
| 55 | |
| 56 | /* Chip Config Values */ |
| 57 | #define SMSC_FDC37M81X_CONFIG_ENTER 0x55 |
| 58 | #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa |
| 59 | #define SMSC_FDC37M81X_CHIP_ID 0x4d |
| 60 | |
| 61 | unsigned long __init smsc_fdc37m81x_init(unsigned long port); |
| 62 | |
| 63 | void smsc_fdc37m81x_config_beg(void); |
| 64 | |
| 65 | void smsc_fdc37m81x_config_end(void); |
| 66 | |
| 67 | void smsc_fdc37m81x_config_set(u8 reg, u8 val); |
| 68 | |
| 69 | #endif |