Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*-*- linux-c -*- |
| 2 | * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device |
| 3 | * |
| 4 | * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> |
| 5 | * All Rights Reserved |
| 6 | * |
| 7 | * Contributors: |
| 8 | * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets |
| 9 | * and enabling the power-on state of |
| 10 | * external VGA connectors for |
| 11 | * secondary displays |
| 12 | * |
| 13 | * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of |
| 14 | * the VESA GTF |
| 15 | * |
| 16 | * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized |
| 17 | * timings support |
| 18 | * |
| 19 | * The code framework is a modification of vfb.c by Geert Uytterhoeven. |
| 20 | * DotClock and PLL calculations are partly based on i810_driver.c |
| 21 | * in xfree86 v4.0.3 by Precision Insight. |
| 22 | * Watermark calculation and tables are based on i810_wmark.c |
| 23 | * in xfre86 v4.0.3 by Precision Insight. Slight modifications |
| 24 | * only to allow for integer operations instead of floating point. |
| 25 | * |
| 26 | * This file is subject to the terms and conditions of the GNU General Public |
| 27 | * License. See the file COPYING in the main directory of this archive for |
| 28 | * more details. |
| 29 | */ |
| 30 | |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/config.h> |
| 33 | #include <linux/kernel.h> |
| 34 | #include <linux/errno.h> |
| 35 | #include <linux/string.h> |
| 36 | #include <linux/mm.h> |
| 37 | #include <linux/tty.h> |
| 38 | #include <linux/slab.h> |
| 39 | #include <linux/fb.h> |
| 40 | #include <linux/init.h> |
| 41 | #include <linux/pci.h> |
| 42 | #include <linux/pci_ids.h> |
| 43 | #include <linux/resource.h> |
| 44 | #include <linux/unistd.h> |
| 45 | |
| 46 | #include <asm/io.h> |
| 47 | #include <asm/div64.h> |
| 48 | |
| 49 | #ifdef CONFIG_MTRR |
| 50 | #include <asm/mtrr.h> |
| 51 | #endif |
| 52 | |
| 53 | #include <asm/page.h> |
| 54 | |
| 55 | #include "i810_regs.h" |
| 56 | #include "i810.h" |
| 57 | #include "i810_main.h" |
| 58 | |
| 59 | /* PCI */ |
| 60 | static const char *i810_pci_list[] __devinitdata = { |
| 61 | "Intel(R) 810 Framebuffer Device" , |
| 62 | "Intel(R) 810-DC100 Framebuffer Device" , |
| 63 | "Intel(R) 810E Framebuffer Device" , |
| 64 | "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" , |
| 65 | "Intel(R) 815 (Internal Graphics only) Framebuffer Device" , |
| 66 | "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device" |
| 67 | }; |
| 68 | |
| 69 | static struct pci_device_id i810fb_pci_tbl[] = { |
| 70 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1, |
| 71 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
| 72 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, |
| 73 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, |
| 74 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG, |
| 75 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, |
| 76 | /* mvo: added i815 PCI-ID */ |
| 77 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100, |
| 78 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, |
| 79 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP, |
| 80 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, |
| 81 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, |
| 82 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, |
| 83 | { 0 }, |
| 84 | }; |
| 85 | |
| 86 | static struct pci_driver i810fb_driver = { |
| 87 | .name = "i810fb", |
| 88 | .id_table = i810fb_pci_tbl, |
| 89 | .probe = i810fb_init_pci, |
| 90 | .remove = __exit_p(i810fb_remove_pci), |
| 91 | .suspend = i810fb_suspend, |
| 92 | .resume = i810fb_resume, |
| 93 | }; |
| 94 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 95 | static char *mode_option __devinitdata = NULL; |
| 96 | static int vram __devinitdata = 4; |
| 97 | static int bpp __devinitdata = 8; |
Antonino A. Daplas | 595e8a9 | 2005-09-12 09:15:16 +0800 | [diff] [blame] | 98 | static int mtrr __devinitdata; |
| 99 | static int accel __devinitdata; |
| 100 | static int hsync1 __devinitdata; |
| 101 | static int hsync2 __devinitdata; |
| 102 | static int vsync1 __devinitdata; |
| 103 | static int vsync2 __devinitdata; |
| 104 | static int xres __devinitdata; |
| 105 | static int yres __devinitdata; |
| 106 | static int vyres __devinitdata; |
| 107 | static int sync __devinitdata; |
Antonino A. Daplas | 747a505 | 2005-09-12 09:16:47 +0800 | [diff] [blame] | 108 | static int extvga __devinitdata; |
Antonino A. Daplas | 595e8a9 | 2005-09-12 09:15:16 +0800 | [diff] [blame] | 109 | static int dcolor __devinitdata; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
| 111 | /*------------------------------------------------------------*/ |
| 112 | |
| 113 | /************************************************************** |
| 114 | * Hardware Low Level Routines * |
| 115 | **************************************************************/ |
| 116 | |
| 117 | /** |
| 118 | * i810_screen_off - turns off/on display |
| 119 | * @mmio: address of register space |
| 120 | * @mode: on or off |
| 121 | * |
| 122 | * DESCRIPTION: |
| 123 | * Blanks/unblanks the display |
| 124 | */ |
| 125 | static void i810_screen_off(u8 __iomem *mmio, u8 mode) |
| 126 | { |
| 127 | u32 count = WAIT_COUNT; |
| 128 | u8 val; |
| 129 | |
| 130 | i810_writeb(SR_INDEX, mmio, SR01); |
| 131 | val = i810_readb(SR_DATA, mmio); |
| 132 | val = (mode == OFF) ? val | SCR_OFF : |
| 133 | val & ~SCR_OFF; |
| 134 | |
| 135 | while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); |
| 136 | i810_writeb(SR_INDEX, mmio, SR01); |
| 137 | i810_writeb(SR_DATA, mmio, val); |
| 138 | } |
| 139 | |
| 140 | /** |
| 141 | * i810_dram_off - turns off/on dram refresh |
| 142 | * @mmio: address of register space |
| 143 | * @mode: on or off |
| 144 | * |
| 145 | * DESCRIPTION: |
| 146 | * Turns off DRAM refresh. Must be off for only 2 vsyncs |
| 147 | * before data becomes corrupt |
| 148 | */ |
| 149 | static void i810_dram_off(u8 __iomem *mmio, u8 mode) |
| 150 | { |
| 151 | u8 val; |
| 152 | |
| 153 | val = i810_readb(DRAMCH, mmio); |
| 154 | val &= DRAM_OFF; |
| 155 | val = (mode == OFF) ? val : val | DRAM_ON; |
| 156 | i810_writeb(DRAMCH, mmio, val); |
| 157 | } |
| 158 | |
| 159 | /** |
| 160 | * i810_protect_regs - allows rw/ro mode of certain VGA registers |
| 161 | * @mmio: address of register space |
| 162 | * @mode: protect/unprotect |
| 163 | * |
| 164 | * DESCRIPTION: |
| 165 | * The IBM VGA standard allows protection of certain VGA registers. |
| 166 | * This will protect or unprotect them. |
| 167 | */ |
| 168 | static void i810_protect_regs(u8 __iomem *mmio, int mode) |
| 169 | { |
| 170 | u8 reg; |
| 171 | |
| 172 | i810_writeb(CR_INDEX_CGA, mmio, CR11); |
| 173 | reg = i810_readb(CR_DATA_CGA, mmio); |
| 174 | reg = (mode == OFF) ? reg & ~0x80 : |
| 175 | reg | 0x80; |
| 176 | |
| 177 | i810_writeb(CR_INDEX_CGA, mmio, CR11); |
| 178 | i810_writeb(CR_DATA_CGA, mmio, reg); |
| 179 | } |
| 180 | |
| 181 | /** |
| 182 | * i810_load_pll - loads values for the hardware PLL clock |
| 183 | * @par: pointer to i810fb_par structure |
| 184 | * |
| 185 | * DESCRIPTION: |
| 186 | * Loads the P, M, and N registers. |
| 187 | */ |
| 188 | static void i810_load_pll(struct i810fb_par *par) |
| 189 | { |
| 190 | u32 tmp1, tmp2; |
| 191 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 192 | |
| 193 | tmp1 = par->regs.M | par->regs.N << 16; |
| 194 | tmp2 = i810_readl(DCLK_2D, mmio); |
| 195 | tmp2 &= ~MN_MASK; |
| 196 | i810_writel(DCLK_2D, mmio, tmp1 | tmp2); |
| 197 | |
| 198 | tmp1 = par->regs.P; |
| 199 | tmp2 = i810_readl(DCLK_0DS, mmio); |
| 200 | tmp2 &= ~(P_OR << 16); |
| 201 | i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2); |
| 202 | |
| 203 | i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1); |
| 204 | |
| 205 | } |
| 206 | |
| 207 | /** |
| 208 | * i810_load_vga - load standard VGA registers |
| 209 | * @par: pointer to i810fb_par structure |
| 210 | * |
| 211 | * DESCRIPTION: |
| 212 | * Load values to VGA registers |
| 213 | */ |
| 214 | static void i810_load_vga(struct i810fb_par *par) |
| 215 | { |
| 216 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 217 | |
| 218 | /* interlace */ |
| 219 | i810_writeb(CR_INDEX_CGA, mmio, CR70); |
| 220 | i810_writeb(CR_DATA_CGA, mmio, par->interlace); |
| 221 | |
| 222 | i810_writeb(CR_INDEX_CGA, mmio, CR00); |
| 223 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00); |
| 224 | i810_writeb(CR_INDEX_CGA, mmio, CR01); |
| 225 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01); |
| 226 | i810_writeb(CR_INDEX_CGA, mmio, CR02); |
| 227 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02); |
| 228 | i810_writeb(CR_INDEX_CGA, mmio, CR03); |
| 229 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03); |
| 230 | i810_writeb(CR_INDEX_CGA, mmio, CR04); |
| 231 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04); |
| 232 | i810_writeb(CR_INDEX_CGA, mmio, CR05); |
| 233 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05); |
| 234 | i810_writeb(CR_INDEX_CGA, mmio, CR06); |
| 235 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06); |
| 236 | i810_writeb(CR_INDEX_CGA, mmio, CR09); |
| 237 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09); |
| 238 | i810_writeb(CR_INDEX_CGA, mmio, CR10); |
| 239 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10); |
| 240 | i810_writeb(CR_INDEX_CGA, mmio, CR11); |
| 241 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11); |
| 242 | i810_writeb(CR_INDEX_CGA, mmio, CR12); |
| 243 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12); |
| 244 | i810_writeb(CR_INDEX_CGA, mmio, CR15); |
| 245 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15); |
| 246 | i810_writeb(CR_INDEX_CGA, mmio, CR16); |
| 247 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16); |
| 248 | } |
| 249 | |
| 250 | /** |
| 251 | * i810_load_vgax - load extended VGA registers |
| 252 | * @par: pointer to i810fb_par structure |
| 253 | * |
| 254 | * DESCRIPTION: |
| 255 | * Load values to extended VGA registers |
| 256 | */ |
| 257 | static void i810_load_vgax(struct i810fb_par *par) |
| 258 | { |
| 259 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 260 | |
| 261 | i810_writeb(CR_INDEX_CGA, mmio, CR30); |
| 262 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30); |
| 263 | i810_writeb(CR_INDEX_CGA, mmio, CR31); |
| 264 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31); |
| 265 | i810_writeb(CR_INDEX_CGA, mmio, CR32); |
| 266 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32); |
| 267 | i810_writeb(CR_INDEX_CGA, mmio, CR33); |
| 268 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33); |
| 269 | i810_writeb(CR_INDEX_CGA, mmio, CR35); |
| 270 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35); |
| 271 | i810_writeb(CR_INDEX_CGA, mmio, CR39); |
| 272 | i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39); |
| 273 | } |
| 274 | |
| 275 | /** |
| 276 | * i810_load_2d - load grahics registers |
| 277 | * @par: pointer to i810fb_par structure |
| 278 | * |
| 279 | * DESCRIPTION: |
| 280 | * Load values to graphics registers |
| 281 | */ |
| 282 | static void i810_load_2d(struct i810fb_par *par) |
| 283 | { |
| 284 | u32 tmp; |
| 285 | u8 tmp8; |
| 286 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 287 | |
| 288 | i810_writel(FW_BLC, mmio, par->watermark); |
| 289 | tmp = i810_readl(PIXCONF, mmio); |
| 290 | tmp |= 1 | 1 << 20; |
| 291 | i810_writel(PIXCONF, mmio, tmp); |
| 292 | |
| 293 | i810_writel(OVRACT, mmio, par->ovract); |
| 294 | |
| 295 | i810_writeb(GR_INDEX, mmio, GR10); |
| 296 | tmp8 = i810_readb(GR_DATA, mmio); |
| 297 | tmp8 |= 2; |
| 298 | i810_writeb(GR_INDEX, mmio, GR10); |
| 299 | i810_writeb(GR_DATA, mmio, tmp8); |
| 300 | } |
| 301 | |
| 302 | /** |
| 303 | * i810_hires - enables high resolution mode |
| 304 | * @mmio: address of register space |
| 305 | */ |
| 306 | static void i810_hires(u8 __iomem *mmio) |
| 307 | { |
| 308 | u8 val; |
| 309 | |
| 310 | i810_writeb(CR_INDEX_CGA, mmio, CR80); |
| 311 | val = i810_readb(CR_DATA_CGA, mmio); |
| 312 | i810_writeb(CR_INDEX_CGA, mmio, CR80); |
| 313 | i810_writeb(CR_DATA_CGA, mmio, val | 1); |
Antonino A. Daplas | 63edcea | 2005-09-09 13:10:05 -0700 | [diff] [blame] | 314 | /* Stop LCD displays from flickering */ |
| 315 | i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | /** |
| 319 | * i810_load_pitch - loads the characters per line of the display |
| 320 | * @par: pointer to i810fb_par structure |
| 321 | * |
| 322 | * DESCRIPTION: |
| 323 | * Loads the characters per line |
| 324 | */ |
| 325 | static void i810_load_pitch(struct i810fb_par *par) |
| 326 | { |
| 327 | u32 tmp, pitch; |
| 328 | u8 val; |
| 329 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 330 | |
| 331 | pitch = par->pitch >> 3; |
| 332 | i810_writeb(SR_INDEX, mmio, SR01); |
| 333 | val = i810_readb(SR_DATA, mmio); |
| 334 | val &= 0xE0; |
| 335 | val |= 1 | 1 << 2; |
| 336 | i810_writeb(SR_INDEX, mmio, SR01); |
| 337 | i810_writeb(SR_DATA, mmio, val); |
| 338 | |
| 339 | tmp = pitch & 0xFF; |
| 340 | i810_writeb(CR_INDEX_CGA, mmio, CR13); |
| 341 | i810_writeb(CR_DATA_CGA, mmio, (u8) tmp); |
| 342 | |
| 343 | tmp = pitch >> 8; |
| 344 | i810_writeb(CR_INDEX_CGA, mmio, CR41); |
| 345 | val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F; |
| 346 | i810_writeb(CR_INDEX_CGA, mmio, CR41); |
| 347 | i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val); |
| 348 | } |
| 349 | |
| 350 | /** |
| 351 | * i810_load_color - loads the color depth of the display |
| 352 | * @par: pointer to i810fb_par structure |
| 353 | * |
| 354 | * DESCRIPTION: |
| 355 | * Loads the color depth of the display and the graphics engine |
| 356 | */ |
| 357 | static void i810_load_color(struct i810fb_par *par) |
| 358 | { |
| 359 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 360 | u32 reg1; |
| 361 | u16 reg2; |
| 362 | |
| 363 | reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27); |
| 364 | reg2 = i810_readw(BLTCNTL, mmio) & ~0x30; |
| 365 | |
| 366 | reg1 |= 0x8000 | par->pixconf; |
| 367 | reg2 |= par->bltcntl; |
| 368 | i810_writel(PIXCONF, mmio, reg1); |
| 369 | i810_writew(BLTCNTL, mmio, reg2); |
| 370 | } |
| 371 | |
| 372 | /** |
| 373 | * i810_load_regs - loads all registers for the mode |
| 374 | * @par: pointer to i810fb_par structure |
| 375 | * |
| 376 | * DESCRIPTION: |
| 377 | * Loads registers |
| 378 | */ |
| 379 | static void i810_load_regs(struct i810fb_par *par) |
| 380 | { |
| 381 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 382 | |
| 383 | i810_screen_off(mmio, OFF); |
| 384 | i810_protect_regs(mmio, OFF); |
| 385 | i810_dram_off(mmio, OFF); |
| 386 | i810_load_pll(par); |
| 387 | i810_load_vga(par); |
| 388 | i810_load_vgax(par); |
| 389 | i810_dram_off(mmio, ON); |
| 390 | i810_load_2d(par); |
| 391 | i810_hires(mmio); |
| 392 | i810_screen_off(mmio, ON); |
| 393 | i810_protect_regs(mmio, ON); |
| 394 | i810_load_color(par); |
| 395 | i810_load_pitch(par); |
| 396 | } |
| 397 | |
| 398 | static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue, |
| 399 | u8 __iomem *mmio) |
| 400 | { |
| 401 | i810_writeb(CLUT_INDEX_WRITE, mmio, regno); |
| 402 | i810_writeb(CLUT_DATA, mmio, red); |
| 403 | i810_writeb(CLUT_DATA, mmio, green); |
| 404 | i810_writeb(CLUT_DATA, mmio, blue); |
| 405 | } |
| 406 | |
| 407 | static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue, |
| 408 | u8 __iomem *mmio) |
| 409 | { |
| 410 | i810_writeb(CLUT_INDEX_READ, mmio, regno); |
| 411 | *red = i810_readb(CLUT_DATA, mmio); |
| 412 | *green = i810_readb(CLUT_DATA, mmio); |
| 413 | *blue = i810_readb(CLUT_DATA, mmio); |
| 414 | } |
| 415 | |
| 416 | /************************************************************ |
| 417 | * VGA State Restore * |
| 418 | ************************************************************/ |
| 419 | static void i810_restore_pll(struct i810fb_par *par) |
| 420 | { |
| 421 | u32 tmp1, tmp2; |
| 422 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 423 | |
| 424 | tmp1 = par->hw_state.dclk_2d; |
| 425 | tmp2 = i810_readl(DCLK_2D, mmio); |
| 426 | tmp1 &= ~MN_MASK; |
| 427 | tmp2 &= MN_MASK; |
| 428 | i810_writel(DCLK_2D, mmio, tmp1 | tmp2); |
| 429 | |
| 430 | tmp1 = par->hw_state.dclk_1d; |
| 431 | tmp2 = i810_readl(DCLK_1D, mmio); |
| 432 | tmp1 &= ~MN_MASK; |
| 433 | tmp2 &= MN_MASK; |
| 434 | i810_writel(DCLK_1D, mmio, tmp1 | tmp2); |
| 435 | |
| 436 | i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds); |
| 437 | } |
| 438 | |
| 439 | static void i810_restore_dac(struct i810fb_par *par) |
| 440 | { |
| 441 | u32 tmp1, tmp2; |
| 442 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 443 | |
| 444 | tmp1 = par->hw_state.pixconf; |
| 445 | tmp2 = i810_readl(PIXCONF, mmio); |
| 446 | tmp1 &= DAC_BIT; |
| 447 | tmp2 &= ~DAC_BIT; |
| 448 | i810_writel(PIXCONF, mmio, tmp1 | tmp2); |
| 449 | } |
| 450 | |
| 451 | static void i810_restore_vgax(struct i810fb_par *par) |
| 452 | { |
| 453 | u8 i, j; |
| 454 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 455 | |
| 456 | for (i = 0; i < 4; i++) { |
| 457 | i810_writeb(CR_INDEX_CGA, mmio, CR30+i); |
| 458 | i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i)); |
| 459 | } |
| 460 | i810_writeb(CR_INDEX_CGA, mmio, CR35); |
| 461 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35); |
| 462 | i810_writeb(CR_INDEX_CGA, mmio, CR39); |
| 463 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); |
| 464 | i810_writeb(CR_INDEX_CGA, mmio, CR41); |
| 465 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); |
| 466 | |
| 467 | /*restore interlace*/ |
| 468 | i810_writeb(CR_INDEX_CGA, mmio, CR70); |
| 469 | i = par->hw_state.cr70; |
| 470 | i &= INTERLACE_BIT; |
| 471 | j = i810_readb(CR_DATA_CGA, mmio); |
| 472 | i810_writeb(CR_INDEX_CGA, mmio, CR70); |
| 473 | i810_writeb(CR_DATA_CGA, mmio, j | i); |
| 474 | |
| 475 | i810_writeb(CR_INDEX_CGA, mmio, CR80); |
| 476 | i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80); |
| 477 | i810_writeb(MSR_WRITE, mmio, par->hw_state.msr); |
| 478 | i810_writeb(SR_INDEX, mmio, SR01); |
| 479 | i = (par->hw_state.sr01) & ~0xE0 ; |
| 480 | j = i810_readb(SR_DATA, mmio) & 0xE0; |
| 481 | i810_writeb(SR_INDEX, mmio, SR01); |
| 482 | i810_writeb(SR_DATA, mmio, i | j); |
| 483 | } |
| 484 | |
| 485 | static void i810_restore_vga(struct i810fb_par *par) |
| 486 | { |
| 487 | u8 i; |
| 488 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 489 | |
| 490 | for (i = 0; i < 10; i++) { |
| 491 | i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); |
| 492 | i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i)); |
| 493 | } |
| 494 | for (i = 0; i < 8; i++) { |
| 495 | i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); |
| 496 | i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i)); |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | static void i810_restore_addr_map(struct i810fb_par *par) |
| 501 | { |
| 502 | u8 tmp; |
| 503 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 504 | |
| 505 | i810_writeb(GR_INDEX, mmio, GR10); |
| 506 | tmp = i810_readb(GR_DATA, mmio); |
| 507 | tmp &= ADDR_MAP_MASK; |
| 508 | tmp |= par->hw_state.gr10; |
| 509 | i810_writeb(GR_INDEX, mmio, GR10); |
| 510 | i810_writeb(GR_DATA, mmio, tmp); |
| 511 | } |
| 512 | |
| 513 | static void i810_restore_2d(struct i810fb_par *par) |
| 514 | { |
| 515 | u32 tmp_long; |
| 516 | u16 tmp_word; |
| 517 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 518 | |
| 519 | tmp_word = i810_readw(BLTCNTL, mmio); |
| 520 | tmp_word &= ~(3 << 4); |
| 521 | tmp_word |= par->hw_state.bltcntl; |
| 522 | i810_writew(BLTCNTL, mmio, tmp_word); |
| 523 | |
| 524 | i810_dram_off(mmio, OFF); |
| 525 | i810_writel(PIXCONF, mmio, par->hw_state.pixconf); |
| 526 | i810_dram_off(mmio, ON); |
| 527 | |
| 528 | tmp_word = i810_readw(HWSTAM, mmio); |
| 529 | tmp_word &= 3 << 13; |
| 530 | tmp_word |= par->hw_state.hwstam; |
| 531 | i810_writew(HWSTAM, mmio, tmp_word); |
| 532 | |
| 533 | tmp_long = i810_readl(FW_BLC, mmio); |
| 534 | tmp_long &= FW_BLC_MASK; |
| 535 | tmp_long |= par->hw_state.fw_blc; |
| 536 | i810_writel(FW_BLC, mmio, tmp_long); |
| 537 | |
| 538 | i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga); |
| 539 | i810_writew(IER, mmio, par->hw_state.ier); |
| 540 | i810_writew(IMR, mmio, par->hw_state.imr); |
| 541 | i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas); |
| 542 | } |
| 543 | |
| 544 | static void i810_restore_vga_state(struct i810fb_par *par) |
| 545 | { |
| 546 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 547 | |
| 548 | i810_screen_off(mmio, OFF); |
| 549 | i810_protect_regs(mmio, OFF); |
| 550 | i810_dram_off(mmio, OFF); |
| 551 | i810_restore_pll(par); |
| 552 | i810_restore_dac(par); |
| 553 | i810_restore_vga(par); |
| 554 | i810_restore_vgax(par); |
| 555 | i810_restore_addr_map(par); |
| 556 | i810_dram_off(mmio, ON); |
| 557 | i810_restore_2d(par); |
| 558 | i810_screen_off(mmio, ON); |
| 559 | i810_protect_regs(mmio, ON); |
| 560 | } |
| 561 | |
| 562 | /*********************************************************************** |
| 563 | * VGA State Save * |
| 564 | ***********************************************************************/ |
| 565 | |
| 566 | static void i810_save_vgax(struct i810fb_par *par) |
| 567 | { |
| 568 | u8 i; |
| 569 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 570 | |
| 571 | for (i = 0; i < 4; i++) { |
| 572 | i810_writeb(CR_INDEX_CGA, mmio, CR30 + i); |
| 573 | *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio); |
| 574 | } |
| 575 | i810_writeb(CR_INDEX_CGA, mmio, CR35); |
| 576 | par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio); |
| 577 | i810_writeb(CR_INDEX_CGA, mmio, CR39); |
| 578 | par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio); |
| 579 | i810_writeb(CR_INDEX_CGA, mmio, CR41); |
| 580 | par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio); |
| 581 | i810_writeb(CR_INDEX_CGA, mmio, CR70); |
| 582 | par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio); |
| 583 | par->hw_state.msr = i810_readb(MSR_READ, mmio); |
| 584 | i810_writeb(CR_INDEX_CGA, mmio, CR80); |
| 585 | par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio); |
| 586 | i810_writeb(SR_INDEX, mmio, SR01); |
| 587 | par->hw_state.sr01 = i810_readb(SR_DATA, mmio); |
| 588 | } |
| 589 | |
| 590 | static void i810_save_vga(struct i810fb_par *par) |
| 591 | { |
| 592 | u8 i; |
| 593 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 594 | |
| 595 | for (i = 0; i < 10; i++) { |
| 596 | i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); |
| 597 | *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio); |
| 598 | } |
| 599 | for (i = 0; i < 8; i++) { |
| 600 | i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); |
| 601 | *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio); |
| 602 | } |
| 603 | } |
| 604 | |
| 605 | static void i810_save_2d(struct i810fb_par *par) |
| 606 | { |
| 607 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 608 | |
| 609 | par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio); |
| 610 | par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio); |
| 611 | par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio); |
| 612 | par->hw_state.pixconf = i810_readl(PIXCONF, mmio); |
| 613 | par->hw_state.fw_blc = i810_readl(FW_BLC, mmio); |
| 614 | par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio); |
| 615 | par->hw_state.hwstam = i810_readw(HWSTAM, mmio); |
| 616 | par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio); |
| 617 | par->hw_state.ier = i810_readw(IER, mmio); |
| 618 | par->hw_state.imr = i810_readw(IMR, mmio); |
| 619 | par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio); |
| 620 | } |
| 621 | |
| 622 | static void i810_save_vga_state(struct i810fb_par *par) |
| 623 | { |
| 624 | i810_save_vga(par); |
| 625 | i810_save_vgax(par); |
| 626 | i810_save_2d(par); |
| 627 | } |
| 628 | |
| 629 | /************************************************************ |
| 630 | * Helpers * |
| 631 | ************************************************************/ |
| 632 | /** |
| 633 | * get_line_length - calculates buffer pitch in bytes |
| 634 | * @par: pointer to i810fb_par structure |
| 635 | * @xres_virtual: virtual resolution of the frame |
| 636 | * @bpp: bits per pixel |
| 637 | * |
| 638 | * DESCRIPTION: |
| 639 | * Calculates buffer pitch in bytes. |
| 640 | */ |
| 641 | static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp) |
| 642 | { |
| 643 | u32 length; |
| 644 | |
| 645 | length = xres_virtual*bpp; |
| 646 | length = (length+31)&-32; |
| 647 | length >>= 3; |
| 648 | return length; |
| 649 | } |
| 650 | |
| 651 | /** |
| 652 | * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value |
| 653 | * @freq: target pixelclock in picoseconds |
| 654 | * @m: where to write M register |
| 655 | * @n: where to write N register |
| 656 | * @p: where to write P register |
| 657 | * |
| 658 | * DESCRIPTION: |
| 659 | * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P) |
| 660 | * Repeatedly computes the Freq until the actual Freq is equal to |
| 661 | * the target Freq or until the loop count is zero. In the latter |
| 662 | * case, the actual frequency nearest the target will be used. |
| 663 | */ |
| 664 | static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p) |
| 665 | { |
| 666 | u32 m_reg, n_reg, p_divisor, n_target_max; |
| 667 | u32 m_target, n_target, p_target, n_best, m_best, mod; |
| 668 | u32 f_out, target_freq, diff = 0, mod_min, diff_min; |
| 669 | |
| 670 | diff_min = mod_min = 0xFFFFFFFF; |
| 671 | n_best = m_best = m_target = f_out = 0; |
| 672 | |
| 673 | target_freq = freq; |
| 674 | n_target_max = 30; |
| 675 | |
| 676 | /* |
| 677 | * find P such that target freq is 16x reference freq (Hz). |
| 678 | */ |
| 679 | p_divisor = 1; |
| 680 | p_target = 0; |
| 681 | while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) && |
| 682 | p_divisor <= 32) { |
| 683 | p_divisor <<= 1; |
| 684 | p_target++; |
| 685 | } |
| 686 | |
| 687 | n_reg = m_reg = n_target = 3; |
| 688 | while (diff_min && mod_min && (n_target < n_target_max)) { |
| 689 | f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg); |
| 690 | mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg); |
| 691 | m_target = m_reg; |
| 692 | n_target = n_reg; |
| 693 | if (f_out <= target_freq) { |
| 694 | n_reg++; |
| 695 | diff = target_freq - f_out; |
| 696 | } else { |
| 697 | m_reg++; |
| 698 | diff = f_out - target_freq; |
| 699 | } |
| 700 | |
| 701 | if (diff_min > diff) { |
| 702 | diff_min = diff; |
| 703 | n_best = n_target; |
| 704 | m_best = m_target; |
| 705 | } |
| 706 | |
| 707 | if (!diff && mod_min > mod) { |
| 708 | mod_min = mod; |
| 709 | n_best = n_target; |
| 710 | m_best = m_target; |
| 711 | } |
| 712 | } |
| 713 | if (m) *m = (m_best - 2) & 0x3FF; |
| 714 | if (n) *n = (n_best - 2) & 0x3FF; |
| 715 | if (p) *p = (p_target << 4); |
| 716 | } |
| 717 | |
| 718 | /************************************************************* |
| 719 | * Hardware Cursor Routines * |
| 720 | *************************************************************/ |
| 721 | |
| 722 | /** |
| 723 | * i810_enable_cursor - show or hide the hardware cursor |
| 724 | * @mmio: address of register space |
| 725 | * @mode: show (1) or hide (0) |
| 726 | * |
| 727 | * Description: |
| 728 | * Shows or hides the hardware cursor |
| 729 | */ |
| 730 | static void i810_enable_cursor(u8 __iomem *mmio, int mode) |
| 731 | { |
| 732 | u32 temp; |
| 733 | |
| 734 | temp = i810_readl(PIXCONF, mmio); |
| 735 | temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK : |
| 736 | temp & ~CURSOR_ENABLE_MASK; |
| 737 | |
| 738 | i810_writel(PIXCONF, mmio, temp); |
| 739 | } |
| 740 | |
| 741 | static void i810_reset_cursor_image(struct i810fb_par *par) |
| 742 | { |
| 743 | u8 __iomem *addr = par->cursor_heap.virtual; |
| 744 | int i, j; |
| 745 | |
| 746 | for (i = 64; i--; ) { |
| 747 | for (j = 0; j < 8; j++) { |
| 748 | i810_writeb(j, addr, 0xff); |
| 749 | i810_writeb(j+8, addr, 0x00); |
| 750 | } |
| 751 | addr +=16; |
| 752 | } |
| 753 | } |
| 754 | |
| 755 | static void i810_load_cursor_image(int width, int height, u8 *data, |
| 756 | struct i810fb_par *par) |
| 757 | { |
| 758 | u8 __iomem *addr = par->cursor_heap.virtual; |
| 759 | int i, j, w = width/8; |
| 760 | int mod = width % 8, t_mask, d_mask; |
| 761 | |
| 762 | t_mask = 0xff >> mod; |
| 763 | d_mask = ~(0xff >> mod); |
| 764 | for (i = height; i--; ) { |
| 765 | for (j = 0; j < w; j++) { |
| 766 | i810_writeb(j+0, addr, 0x00); |
| 767 | i810_writeb(j+8, addr, *data++); |
| 768 | } |
| 769 | if (mod) { |
| 770 | i810_writeb(j+0, addr, t_mask); |
| 771 | i810_writeb(j+8, addr, *data++ & d_mask); |
| 772 | } |
| 773 | addr += 16; |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info) |
| 778 | { |
| 779 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 780 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 781 | u8 red, green, blue, trans, temp; |
| 782 | |
| 783 | i810fb_getcolreg(bg, &red, &green, &blue, &trans, info); |
| 784 | |
| 785 | temp = i810_readb(PIXCONF1, mmio); |
| 786 | i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); |
| 787 | |
| 788 | i810_write_dac(4, red, green, blue, mmio); |
| 789 | |
| 790 | i810_writeb(PIXCONF1, mmio, temp); |
| 791 | |
| 792 | i810fb_getcolreg(fg, &red, &green, &blue, &trans, info); |
| 793 | temp = i810_readb(PIXCONF1, mmio); |
| 794 | i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); |
| 795 | |
| 796 | i810_write_dac(5, red, green, blue, mmio); |
| 797 | |
| 798 | i810_writeb(PIXCONF1, mmio, temp); |
| 799 | } |
| 800 | |
| 801 | /** |
| 802 | * i810_init_cursor - initializes the cursor |
| 803 | * @par: pointer to i810fb_par structure |
| 804 | * |
| 805 | * DESCRIPTION: |
| 806 | * Initializes the cursor registers |
| 807 | */ |
| 808 | static void i810_init_cursor(struct i810fb_par *par) |
| 809 | { |
| 810 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 811 | |
| 812 | i810_enable_cursor(mmio, OFF); |
| 813 | i810_writel(CURBASE, mmio, par->cursor_heap.physical); |
| 814 | i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR); |
| 815 | } |
| 816 | |
| 817 | /********************************************************************* |
| 818 | * Framebuffer hook helpers * |
| 819 | *********************************************************************/ |
| 820 | /** |
| 821 | * i810_round_off - Round off values to capability of hardware |
| 822 | * @var: pointer to fb_var_screeninfo structure |
| 823 | * |
| 824 | * DESCRIPTION: |
| 825 | * @var contains user-defined information for the mode to be set. |
| 826 | * This will try modify those values to ones nearest the |
| 827 | * capability of the hardware |
| 828 | */ |
| 829 | static void i810_round_off(struct fb_var_screeninfo *var) |
| 830 | { |
| 831 | u32 xres, yres, vxres, vyres; |
| 832 | |
| 833 | /* |
| 834 | * Presently supports only these configurations |
| 835 | */ |
| 836 | |
| 837 | xres = var->xres; |
| 838 | yres = var->yres; |
| 839 | vxres = var->xres_virtual; |
| 840 | vyres = var->yres_virtual; |
| 841 | |
| 842 | var->bits_per_pixel += 7; |
| 843 | var->bits_per_pixel &= ~7; |
| 844 | |
| 845 | if (var->bits_per_pixel < 8) |
| 846 | var->bits_per_pixel = 8; |
| 847 | if (var->bits_per_pixel > 32) |
| 848 | var->bits_per_pixel = 32; |
| 849 | |
| 850 | round_off_xres(&xres); |
| 851 | if (xres < 40) |
| 852 | xres = 40; |
| 853 | if (xres > 2048) |
| 854 | xres = 2048; |
| 855 | xres = (xres + 7) & ~7; |
| 856 | |
| 857 | if (vxres < xres) |
| 858 | vxres = xres; |
| 859 | |
| 860 | round_off_yres(&xres, &yres); |
| 861 | if (yres < 1) |
| 862 | yres = 1; |
| 863 | if (yres >= 2048) |
| 864 | yres = 2048; |
| 865 | |
| 866 | if (vyres < yres) |
| 867 | vyres = yres; |
| 868 | |
| 869 | if (var->bits_per_pixel == 32) |
| 870 | var->accel_flags = 0; |
| 871 | |
| 872 | /* round of horizontal timings to nearest 8 pixels */ |
| 873 | var->left_margin = (var->left_margin + 4) & ~7; |
| 874 | var->right_margin = (var->right_margin + 4) & ~7; |
| 875 | var->hsync_len = (var->hsync_len + 4) & ~7; |
| 876 | |
| 877 | if (var->vmode & FB_VMODE_INTERLACED) { |
| 878 | if (!((yres + var->upper_margin + var->vsync_len + |
| 879 | var->lower_margin) & 1)) |
| 880 | var->upper_margin++; |
| 881 | } |
| 882 | |
| 883 | var->xres = xres; |
| 884 | var->yres = yres; |
| 885 | var->xres_virtual = vxres; |
| 886 | var->yres_virtual = vyres; |
| 887 | } |
| 888 | |
| 889 | /** |
| 890 | * set_color_bitfields - sets rgba fields |
| 891 | * @var: pointer to fb_var_screeninfo |
| 892 | * |
| 893 | * DESCRIPTION: |
| 894 | * The length, offset and ordering for each color field |
| 895 | * (red, green, blue) will be set as specified |
| 896 | * by the hardware |
| 897 | */ |
| 898 | static void set_color_bitfields(struct fb_var_screeninfo *var) |
| 899 | { |
| 900 | switch (var->bits_per_pixel) { |
| 901 | case 8: |
| 902 | var->red.offset = 0; |
| 903 | var->red.length = 8; |
| 904 | var->green.offset = 0; |
| 905 | var->green.length = 8; |
| 906 | var->blue.offset = 0; |
| 907 | var->blue.length = 8; |
| 908 | var->transp.offset = 0; |
| 909 | var->transp.length = 0; |
| 910 | break; |
| 911 | case 16: |
| 912 | var->green.length = (var->green.length == 5) ? 5 : 6; |
| 913 | var->red.length = 5; |
| 914 | var->blue.length = 5; |
| 915 | var->transp.length = 6 - var->green.length; |
| 916 | var->blue.offset = 0; |
| 917 | var->green.offset = 5; |
| 918 | var->red.offset = 5 + var->green.length; |
| 919 | var->transp.offset = (5 + var->red.offset) & 15; |
| 920 | break; |
| 921 | case 24: /* RGB 888 */ |
| 922 | case 32: /* RGBA 8888 */ |
| 923 | var->red.offset = 16; |
| 924 | var->red.length = 8; |
| 925 | var->green.offset = 8; |
| 926 | var->green.length = 8; |
| 927 | var->blue.offset = 0; |
| 928 | var->blue.length = 8; |
| 929 | var->transp.length = var->bits_per_pixel - 24; |
| 930 | var->transp.offset = (var->transp.length) ? 24 : 0; |
| 931 | break; |
| 932 | } |
| 933 | var->red.msb_right = 0; |
| 934 | var->green.msb_right = 0; |
| 935 | var->blue.msb_right = 0; |
| 936 | var->transp.msb_right = 0; |
| 937 | } |
| 938 | |
| 939 | /** |
| 940 | * i810_check_params - check if contents in var are valid |
| 941 | * @var: pointer to fb_var_screeninfo |
| 942 | * @info: pointer to fb_info |
| 943 | * |
| 944 | * DESCRIPTION: |
| 945 | * This will check if the framebuffer size is sufficient |
| 946 | * for the current mode and if the user's monitor has the |
| 947 | * required specifications to display the current mode. |
| 948 | */ |
| 949 | static int i810_check_params(struct fb_var_screeninfo *var, |
| 950 | struct fb_info *info) |
| 951 | { |
| 952 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 953 | int line_length, vidmem, mode_valid = 0, retval = 0; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 954 | u32 vyres = var->yres_virtual, vxres = var->xres_virtual; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | /* |
| 956 | * Memory limit |
| 957 | */ |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 958 | line_length = get_line_length(par, vxres, var->bits_per_pixel); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 959 | vidmem = line_length*vyres; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 960 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | if (vidmem > par->fb.size) { |
| 962 | vyres = par->fb.size/line_length; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 963 | if (vyres < var->yres) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | vyres = yres; |
| 965 | vxres = par->fb.size/vyres; |
| 966 | vxres /= var->bits_per_pixel >> 3; |
| 967 | line_length = get_line_length(par, vxres, |
| 968 | var->bits_per_pixel); |
| 969 | vidmem = line_length * yres; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 970 | if (vxres < var->xres) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | printk("i810fb: required video memory, " |
| 972 | "%d bytes, for %dx%d-%d (virtual) " |
| 973 | "is out of range\n", |
| 974 | vidmem, vxres, vyres, |
| 975 | var->bits_per_pixel); |
| 976 | return -ENOMEM; |
| 977 | } |
| 978 | } |
| 979 | } |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 980 | |
| 981 | var->xres_virtual = vxres; |
| 982 | var->yres_virtual = vyres; |
| 983 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | /* |
| 985 | * Monitor limit |
| 986 | */ |
| 987 | switch (var->bits_per_pixel) { |
| 988 | case 8: |
| 989 | info->monspecs.dclkmax = 234000000; |
| 990 | break; |
| 991 | case 16: |
| 992 | info->monspecs.dclkmax = 229000000; |
| 993 | break; |
| 994 | case 24: |
| 995 | case 32: |
| 996 | info->monspecs.dclkmax = 204000000; |
| 997 | break; |
| 998 | } |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 999 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1000 | info->monspecs.dclkmin = 15000000; |
| 1001 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1002 | if (!fb_validate_mode(var, info)) |
| 1003 | mode_valid = 1; |
| 1004 | |
| 1005 | #ifdef CONFIG_FB_I810_I2C |
| 1006 | if (!mode_valid && info->monspecs.gtf && |
| 1007 | !fb_get_mode(FB_MAXTIMINGS, 0, var, info)) |
| 1008 | mode_valid = 1; |
| 1009 | |
| 1010 | if (!mode_valid && info->monspecs.modedb_len) { |
| 1011 | struct fb_videomode *mode; |
| 1012 | |
| 1013 | mode = fb_find_best_mode(var, &info->modelist); |
| 1014 | if (mode) { |
| 1015 | fb_videomode_to_var(var, mode); |
| 1016 | mode_valid = 1; |
Denis Vlasenko | db9f1d9 | 2005-05-01 08:59:24 -0700 | [diff] [blame] | 1017 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | } |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1019 | #endif |
| 1020 | if (!mode_valid && info->monspecs.modedb_len == 0) { |
| 1021 | if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) { |
| 1022 | int default_sync = (info->monspecs.hfmin-HFMIN) |
| 1023 | |(info->monspecs.hfmax-HFMAX) |
| 1024 | |(info->monspecs.vfmin-VFMIN) |
| 1025 | |(info->monspecs.vfmax-VFMAX); |
| 1026 | printk("i810fb: invalid video mode%s\n", |
| 1027 | default_sync ? "" : ". Specifying " |
| 1028 | "vsyncN/hsyncN parameters may help"); |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 1029 | retval = -EINVAL; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1030 | } |
| 1031 | } |
| 1032 | |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 1033 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1034 | } |
| 1035 | |
| 1036 | /** |
| 1037 | * encode_fix - fill up fb_fix_screeninfo structure |
| 1038 | * @fix: pointer to fb_fix_screeninfo |
| 1039 | * @info: pointer to fb_info |
| 1040 | * |
| 1041 | * DESCRIPTION: |
| 1042 | * This will set up parameters that are unmodifiable by the user. |
| 1043 | */ |
| 1044 | static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info) |
| 1045 | { |
| 1046 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1047 | |
| 1048 | memset(fix, 0, sizeof(struct fb_fix_screeninfo)); |
| 1049 | |
| 1050 | strcpy(fix->id, "I810"); |
| 1051 | fix->smem_start = par->fb.physical; |
| 1052 | fix->smem_len = par->fb.size; |
| 1053 | fix->type = FB_TYPE_PACKED_PIXELS; |
| 1054 | fix->type_aux = 0; |
| 1055 | fix->xpanstep = 8; |
| 1056 | fix->ypanstep = 1; |
| 1057 | |
| 1058 | switch (info->var.bits_per_pixel) { |
| 1059 | case 8: |
| 1060 | fix->visual = FB_VISUAL_PSEUDOCOLOR; |
| 1061 | break; |
| 1062 | case 16: |
| 1063 | case 24: |
| 1064 | case 32: |
| 1065 | if (info->var.nonstd) |
| 1066 | fix->visual = FB_VISUAL_DIRECTCOLOR; |
| 1067 | else |
| 1068 | fix->visual = FB_VISUAL_TRUECOLOR; |
| 1069 | break; |
| 1070 | default: |
| 1071 | return -EINVAL; |
| 1072 | } |
| 1073 | fix->ywrapstep = 0; |
| 1074 | fix->line_length = par->pitch; |
| 1075 | fix->mmio_start = par->mmio_start_phys; |
| 1076 | fix->mmio_len = MMIO_SIZE; |
| 1077 | fix->accel = FB_ACCEL_I810; |
| 1078 | |
| 1079 | return 0; |
| 1080 | } |
| 1081 | |
| 1082 | /** |
| 1083 | * decode_var - modify par according to contents of var |
| 1084 | * @var: pointer to fb_var_screeninfo |
| 1085 | * @par: pointer to i810fb_par |
| 1086 | * |
| 1087 | * DESCRIPTION: |
| 1088 | * Based on the contents of @var, @par will be dynamically filled up. |
| 1089 | * @par contains all information necessary to modify the hardware. |
| 1090 | */ |
| 1091 | static void decode_var(const struct fb_var_screeninfo *var, |
| 1092 | struct i810fb_par *par) |
| 1093 | { |
| 1094 | u32 xres, yres, vxres, vyres; |
| 1095 | |
| 1096 | xres = var->xres; |
| 1097 | yres = var->yres; |
| 1098 | vxres = var->xres_virtual; |
| 1099 | vyres = var->yres_virtual; |
| 1100 | |
| 1101 | switch (var->bits_per_pixel) { |
| 1102 | case 8: |
| 1103 | par->pixconf = PIXCONF8; |
| 1104 | par->bltcntl = 0; |
| 1105 | par->depth = 1; |
| 1106 | par->blit_bpp = BPP8; |
| 1107 | break; |
| 1108 | case 16: |
| 1109 | if (var->green.length == 5) |
| 1110 | par->pixconf = PIXCONF15; |
| 1111 | else |
| 1112 | par->pixconf = PIXCONF16; |
| 1113 | par->bltcntl = 16; |
| 1114 | par->depth = 2; |
| 1115 | par->blit_bpp = BPP16; |
| 1116 | break; |
| 1117 | case 24: |
| 1118 | par->pixconf = PIXCONF24; |
| 1119 | par->bltcntl = 32; |
| 1120 | par->depth = 3; |
| 1121 | par->blit_bpp = BPP24; |
| 1122 | break; |
| 1123 | case 32: |
| 1124 | par->pixconf = PIXCONF32; |
| 1125 | par->bltcntl = 0; |
| 1126 | par->depth = 4; |
| 1127 | par->blit_bpp = 3 << 24; |
| 1128 | break; |
| 1129 | } |
| 1130 | if (var->nonstd && var->bits_per_pixel != 8) |
| 1131 | par->pixconf |= 1 << 27; |
| 1132 | |
| 1133 | i810_calc_dclk(var->pixclock, &par->regs.M, |
| 1134 | &par->regs.N, &par->regs.P); |
| 1135 | i810fb_encode_registers(var, par, xres, yres); |
| 1136 | |
| 1137 | par->watermark = i810_get_watermark(var, par); |
| 1138 | par->pitch = get_line_length(par, vxres, var->bits_per_pixel); |
| 1139 | } |
| 1140 | |
| 1141 | /** |
| 1142 | * i810fb_getcolreg - gets red, green and blue values of the hardware DAC |
| 1143 | * @regno: DAC index |
| 1144 | * @red: red |
| 1145 | * @green: green |
| 1146 | * @blue: blue |
| 1147 | * @transp: transparency (alpha) |
| 1148 | * @info: pointer to fb_info |
| 1149 | * |
| 1150 | * DESCRIPTION: |
| 1151 | * Gets the red, green and blue values of the hardware DAC as pointed by @regno |
| 1152 | * and writes them to @red, @green and @blue respectively |
| 1153 | */ |
| 1154 | static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue, |
| 1155 | u8 *transp, struct fb_info *info) |
| 1156 | { |
| 1157 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1158 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 1159 | u8 temp; |
| 1160 | |
| 1161 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
| 1162 | if ((info->var.green.length == 5 && regno > 31) || |
| 1163 | (info->var.green.length == 6 && regno > 63)) |
| 1164 | return 1; |
| 1165 | } |
| 1166 | |
| 1167 | temp = i810_readb(PIXCONF1, mmio); |
| 1168 | i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); |
| 1169 | |
| 1170 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && |
| 1171 | info->var.green.length == 5) |
| 1172 | i810_read_dac(regno * 8, red, green, blue, mmio); |
| 1173 | |
| 1174 | else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && |
| 1175 | info->var.green.length == 6) { |
| 1176 | u8 tmp; |
| 1177 | |
| 1178 | i810_read_dac(regno * 8, red, &tmp, blue, mmio); |
| 1179 | i810_read_dac(regno * 4, &tmp, green, &tmp, mmio); |
| 1180 | } |
| 1181 | else |
| 1182 | i810_read_dac(regno, red, green, blue, mmio); |
| 1183 | |
| 1184 | *transp = 0; |
| 1185 | i810_writeb(PIXCONF1, mmio, temp); |
| 1186 | |
| 1187 | return 0; |
| 1188 | } |
| 1189 | |
| 1190 | /****************************************************************** |
| 1191 | * Framebuffer device-specific hooks * |
| 1192 | ******************************************************************/ |
| 1193 | |
| 1194 | static int i810fb_open(struct fb_info *info, int user) |
| 1195 | { |
| 1196 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1197 | u32 count = atomic_read(&par->use_count); |
| 1198 | |
| 1199 | if (count == 0) { |
| 1200 | memset(&par->state, 0, sizeof(struct vgastate)); |
| 1201 | par->state.flags = VGA_SAVE_CMAP; |
| 1202 | par->state.vgabase = par->mmio_start_virtual; |
| 1203 | save_vga(&par->state); |
| 1204 | |
| 1205 | i810_save_vga_state(par); |
| 1206 | } |
| 1207 | |
| 1208 | atomic_inc(&par->use_count); |
| 1209 | |
| 1210 | return 0; |
| 1211 | } |
| 1212 | |
| 1213 | static int i810fb_release(struct fb_info *info, int user) |
| 1214 | { |
| 1215 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1216 | u32 count; |
| 1217 | |
| 1218 | count = atomic_read(&par->use_count); |
| 1219 | if (count == 0) |
| 1220 | return -EINVAL; |
| 1221 | |
| 1222 | if (count == 1) { |
| 1223 | i810_restore_vga_state(par); |
| 1224 | restore_vga(&par->state); |
| 1225 | } |
| 1226 | |
| 1227 | atomic_dec(&par->use_count); |
| 1228 | |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | |
| 1233 | static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 1234 | unsigned blue, unsigned transp, |
| 1235 | struct fb_info *info) |
| 1236 | { |
| 1237 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1238 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 1239 | u8 temp; |
| 1240 | int i; |
| 1241 | |
| 1242 | if (regno > 255) return 1; |
| 1243 | |
| 1244 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
| 1245 | if ((info->var.green.length == 5 && regno > 31) || |
| 1246 | (info->var.green.length == 6 && regno > 63)) |
| 1247 | return 1; |
| 1248 | } |
| 1249 | |
| 1250 | if (info->var.grayscale) |
| 1251 | red = green = blue = (19595 * red + 38470 * green + |
| 1252 | 7471 * blue) >> 16; |
| 1253 | |
| 1254 | temp = i810_readb(PIXCONF1, mmio); |
| 1255 | i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); |
| 1256 | |
| 1257 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && |
| 1258 | info->var.green.length == 5) { |
| 1259 | for (i = 0; i < 8; i++) |
| 1260 | i810_write_dac((u8) (regno * 8) + i, (u8) red, |
| 1261 | (u8) green, (u8) blue, mmio); |
| 1262 | } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && |
| 1263 | info->var.green.length == 6) { |
| 1264 | u8 r, g, b; |
| 1265 | |
| 1266 | if (regno < 32) { |
| 1267 | for (i = 0; i < 8; i++) |
| 1268 | i810_write_dac((u8) (regno * 8) + i, |
| 1269 | (u8) red, (u8) green, |
| 1270 | (u8) blue, mmio); |
| 1271 | } |
| 1272 | i810_read_dac((u8) (regno*4), &r, &g, &b, mmio); |
| 1273 | for (i = 0; i < 4; i++) |
| 1274 | i810_write_dac((u8) (regno*4) + i, r, (u8) green, |
| 1275 | b, mmio); |
| 1276 | } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { |
| 1277 | i810_write_dac((u8) regno, (u8) red, (u8) green, |
| 1278 | (u8) blue, mmio); |
| 1279 | } |
| 1280 | |
| 1281 | i810_writeb(PIXCONF1, mmio, temp); |
| 1282 | |
| 1283 | if (regno < 16) { |
| 1284 | switch (info->var.bits_per_pixel) { |
| 1285 | case 16: |
| 1286 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
| 1287 | if (info->var.green.length == 5) |
| 1288 | ((u32 *)info->pseudo_palette)[regno] = |
| 1289 | (regno << 10) | (regno << 5) | |
| 1290 | regno; |
| 1291 | else |
| 1292 | ((u32 *)info->pseudo_palette)[regno] = |
| 1293 | (regno << 11) | (regno << 5) | |
| 1294 | regno; |
| 1295 | } else { |
| 1296 | if (info->var.green.length == 5) { |
| 1297 | /* RGB 555 */ |
| 1298 | ((u32 *)info->pseudo_palette)[regno] = |
| 1299 | ((red & 0xf800) >> 1) | |
| 1300 | ((green & 0xf800) >> 6) | |
| 1301 | ((blue & 0xf800) >> 11); |
| 1302 | } else { |
| 1303 | /* RGB 565 */ |
| 1304 | ((u32 *)info->pseudo_palette)[regno] = |
| 1305 | (red & 0xf800) | |
| 1306 | ((green & 0xf800) >> 5) | |
| 1307 | ((blue & 0xf800) >> 11); |
| 1308 | } |
| 1309 | } |
| 1310 | break; |
| 1311 | case 24: /* RGB 888 */ |
| 1312 | case 32: /* RGBA 8888 */ |
| 1313 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) |
| 1314 | ((u32 *)info->pseudo_palette)[regno] = |
| 1315 | (regno << 16) | (regno << 8) | |
| 1316 | regno; |
| 1317 | else |
| 1318 | ((u32 *)info->pseudo_palette)[regno] = |
| 1319 | ((red & 0xff00) << 8) | |
| 1320 | (green & 0xff00) | |
| 1321 | ((blue & 0xff00) >> 8); |
| 1322 | break; |
| 1323 | } |
| 1324 | } |
| 1325 | return 0; |
| 1326 | } |
| 1327 | |
| 1328 | static int i810fb_pan_display(struct fb_var_screeninfo *var, |
| 1329 | struct fb_info *info) |
| 1330 | { |
| 1331 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1332 | u32 total; |
| 1333 | |
| 1334 | total = var->xoffset * par->depth + |
| 1335 | var->yoffset * info->fix.line_length; |
| 1336 | i810fb_load_front(total, info); |
| 1337 | |
| 1338 | return 0; |
| 1339 | } |
| 1340 | |
| 1341 | static int i810fb_blank (int blank_mode, struct fb_info *info) |
| 1342 | { |
| 1343 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1344 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 1345 | int mode = 0, pwr, scr_off = 0; |
| 1346 | |
| 1347 | pwr = i810_readl(PWR_CLKC, mmio); |
| 1348 | |
| 1349 | switch (blank_mode) { |
| 1350 | case FB_BLANK_UNBLANK: |
| 1351 | mode = POWERON; |
| 1352 | pwr |= 1; |
| 1353 | scr_off = ON; |
| 1354 | break; |
| 1355 | case FB_BLANK_NORMAL: |
| 1356 | mode = POWERON; |
| 1357 | pwr |= 1; |
| 1358 | scr_off = OFF; |
| 1359 | break; |
| 1360 | case FB_BLANK_VSYNC_SUSPEND: |
| 1361 | mode = STANDBY; |
| 1362 | pwr |= 1; |
| 1363 | scr_off = OFF; |
| 1364 | break; |
| 1365 | case FB_BLANK_HSYNC_SUSPEND: |
| 1366 | mode = SUSPEND; |
| 1367 | pwr |= 1; |
| 1368 | scr_off = OFF; |
| 1369 | break; |
| 1370 | case FB_BLANK_POWERDOWN: |
| 1371 | mode = POWERDOWN; |
| 1372 | pwr &= ~1; |
| 1373 | scr_off = OFF; |
| 1374 | break; |
| 1375 | default: |
| 1376 | return -EINVAL; |
| 1377 | } |
| 1378 | |
| 1379 | i810_screen_off(mmio, scr_off); |
| 1380 | i810_writel(HVSYNC, mmio, mode); |
| 1381 | i810_writel(PWR_CLKC, mmio, pwr); |
| 1382 | |
| 1383 | return 0; |
| 1384 | } |
| 1385 | |
| 1386 | static int i810fb_set_par(struct fb_info *info) |
| 1387 | { |
| 1388 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1389 | |
| 1390 | decode_var(&info->var, par); |
| 1391 | i810_load_regs(par); |
| 1392 | i810_init_cursor(par); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1393 | encode_fix(&info->fix, info); |
| 1394 | |
| 1395 | if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) { |
| 1396 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN | |
| 1397 | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | |
| 1398 | FBINFO_HWACCEL_IMAGEBLIT; |
| 1399 | info->pixmap.scan_align = 2; |
| 1400 | } else { |
| 1401 | info->pixmap.scan_align = 1; |
| 1402 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
| 1403 | } |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
| 1407 | static int i810fb_check_var(struct fb_var_screeninfo *var, |
| 1408 | struct fb_info *info) |
| 1409 | { |
| 1410 | int err; |
| 1411 | |
| 1412 | if (IS_DVT) { |
| 1413 | var->vmode &= ~FB_VMODE_MASK; |
| 1414 | var->vmode |= FB_VMODE_NONINTERLACED; |
| 1415 | } |
| 1416 | if (var->vmode & FB_VMODE_DOUBLE) { |
| 1417 | var->vmode &= ~FB_VMODE_MASK; |
| 1418 | var->vmode |= FB_VMODE_NONINTERLACED; |
| 1419 | } |
| 1420 | |
| 1421 | i810_round_off(var); |
| 1422 | if ((err = i810_check_params(var, info))) |
| 1423 | return err; |
| 1424 | |
| 1425 | i810fb_fill_var_timings(var); |
| 1426 | set_color_bitfields(var); |
| 1427 | return 0; |
| 1428 | } |
| 1429 | |
| 1430 | static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor) |
| 1431 | { |
| 1432 | struct i810fb_par *par = (struct i810fb_par *)info->par; |
| 1433 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 1434 | |
James Simmons | 4c7ffe0 | 2005-09-09 13:04:31 -0700 | [diff] [blame] | 1435 | if (!par->dev_flags & LOCKUP) |
| 1436 | return -ENXIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1437 | |
| 1438 | if (cursor->image.width > 64 || cursor->image.height > 64) |
| 1439 | return -ENXIO; |
| 1440 | |
| 1441 | if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) { |
| 1442 | i810_init_cursor(par); |
| 1443 | cursor->set |= FB_CUR_SETALL; |
| 1444 | } |
| 1445 | |
| 1446 | i810_enable_cursor(mmio, OFF); |
| 1447 | |
| 1448 | if (cursor->set & FB_CUR_SETPOS) { |
| 1449 | u32 tmp; |
| 1450 | |
| 1451 | tmp = (cursor->image.dx - info->var.xoffset) & 0xffff; |
| 1452 | tmp |= (cursor->image.dy - info->var.yoffset) << 16; |
| 1453 | i810_writel(CURPOS, mmio, tmp); |
| 1454 | } |
| 1455 | |
| 1456 | if (cursor->set & FB_CUR_SETSIZE) |
| 1457 | i810_reset_cursor_image(par); |
| 1458 | |
| 1459 | if (cursor->set & FB_CUR_SETCMAP) |
| 1460 | i810_load_cursor_colors(cursor->image.fg_color, |
| 1461 | cursor->image.bg_color, |
| 1462 | info); |
| 1463 | |
| 1464 | if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { |
| 1465 | int size = ((cursor->image.width + 7) >> 3) * |
| 1466 | cursor->image.height; |
| 1467 | int i; |
| 1468 | u8 *data = kmalloc(64 * 8, GFP_KERNEL); |
| 1469 | |
| 1470 | if (data == NULL) |
| 1471 | return -ENOMEM; |
| 1472 | |
| 1473 | switch (cursor->rop) { |
| 1474 | case ROP_XOR: |
| 1475 | for (i = 0; i < size; i++) |
| 1476 | data[i] = cursor->image.data[i] ^ cursor->mask[i]; |
| 1477 | break; |
| 1478 | case ROP_COPY: |
| 1479 | default: |
| 1480 | for (i = 0; i < size; i++) |
| 1481 | data[i] = cursor->image.data[i] & cursor->mask[i]; |
| 1482 | break; |
| 1483 | } |
| 1484 | |
| 1485 | i810_load_cursor_image(cursor->image.width, |
| 1486 | cursor->image.height, data, |
| 1487 | par); |
| 1488 | kfree(data); |
| 1489 | } |
| 1490 | |
| 1491 | if (cursor->enable) |
| 1492 | i810_enable_cursor(mmio, ON); |
| 1493 | |
| 1494 | return 0; |
| 1495 | } |
| 1496 | |
| 1497 | static struct fb_ops i810fb_ops __devinitdata = { |
| 1498 | .owner = THIS_MODULE, |
| 1499 | .fb_open = i810fb_open, |
| 1500 | .fb_release = i810fb_release, |
| 1501 | .fb_check_var = i810fb_check_var, |
| 1502 | .fb_set_par = i810fb_set_par, |
| 1503 | .fb_setcolreg = i810fb_setcolreg, |
| 1504 | .fb_blank = i810fb_blank, |
| 1505 | .fb_pan_display = i810fb_pan_display, |
| 1506 | .fb_fillrect = i810fb_fillrect, |
| 1507 | .fb_copyarea = i810fb_copyarea, |
| 1508 | .fb_imageblit = i810fb_imageblit, |
| 1509 | .fb_cursor = i810fb_cursor, |
| 1510 | .fb_sync = i810fb_sync, |
| 1511 | }; |
| 1512 | |
| 1513 | /*********************************************************************** |
| 1514 | * Power Management * |
| 1515 | ***********************************************************************/ |
| 1516 | static int i810fb_suspend(struct pci_dev *dev, pm_message_t state) |
| 1517 | { |
| 1518 | struct fb_info *info = pci_get_drvdata(dev); |
| 1519 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1520 | int blank = 0, prev_state = par->cur_state; |
| 1521 | |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 1522 | if (state.event == prev_state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1523 | return 0; |
| 1524 | |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 1525 | par->cur_state = state.event; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 1527 | switch (state.event) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1528 | case 1: |
| 1529 | blank = VESA_VSYNC_SUSPEND; |
| 1530 | break; |
| 1531 | case 2: |
| 1532 | blank = VESA_HSYNC_SUSPEND; |
| 1533 | break; |
| 1534 | case 3: |
| 1535 | blank = VESA_POWERDOWN; |
| 1536 | break; |
| 1537 | default: |
| 1538 | return -EINVAL; |
| 1539 | } |
| 1540 | info->fbops->fb_blank(blank, info); |
| 1541 | |
| 1542 | if (!prev_state) { |
| 1543 | agp_unbind_memory(par->i810_gtt.i810_fb_memory); |
| 1544 | agp_unbind_memory(par->i810_gtt.i810_cursor_memory); |
| 1545 | pci_disable_device(dev); |
| 1546 | } |
| 1547 | pci_save_state(dev); |
| 1548 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
| 1549 | |
| 1550 | return 0; |
| 1551 | } |
| 1552 | |
| 1553 | static int i810fb_resume(struct pci_dev *dev) |
| 1554 | { |
| 1555 | struct fb_info *info = pci_get_drvdata(dev); |
| 1556 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1557 | |
| 1558 | if (par->cur_state == 0) |
| 1559 | return 0; |
| 1560 | |
| 1561 | pci_restore_state(dev); |
| 1562 | pci_set_power_state(dev, PCI_D0); |
| 1563 | pci_enable_device(dev); |
| 1564 | agp_bind_memory(par->i810_gtt.i810_fb_memory, |
| 1565 | par->fb.offset); |
| 1566 | agp_bind_memory(par->i810_gtt.i810_cursor_memory, |
| 1567 | par->cursor_heap.offset); |
| 1568 | |
| 1569 | info->fbops->fb_blank(VESA_NO_BLANKING, info); |
| 1570 | |
| 1571 | par->cur_state = 0; |
| 1572 | |
| 1573 | return 0; |
| 1574 | } |
| 1575 | /*********************************************************************** |
| 1576 | * AGP resource allocation * |
| 1577 | ***********************************************************************/ |
| 1578 | |
| 1579 | static void __devinit i810_fix_pointers(struct i810fb_par *par) |
| 1580 | { |
| 1581 | par->fb.physical = par->aperture.physical+(par->fb.offset << 12); |
| 1582 | par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12); |
| 1583 | par->iring.physical = par->aperture.physical + |
| 1584 | (par->iring.offset << 12); |
| 1585 | par->iring.virtual = par->aperture.virtual + |
| 1586 | (par->iring.offset << 12); |
| 1587 | par->cursor_heap.virtual = par->aperture.virtual+ |
| 1588 | (par->cursor_heap.offset << 12); |
| 1589 | } |
| 1590 | |
| 1591 | static void __devinit i810_fix_offsets(struct i810fb_par *par) |
| 1592 | { |
| 1593 | if (vram + 1 > par->aperture.size >> 20) |
| 1594 | vram = (par->aperture.size >> 20) - 1; |
| 1595 | if (v_offset_default > (par->aperture.size >> 20)) |
| 1596 | v_offset_default = (par->aperture.size >> 20); |
| 1597 | if (vram + v_offset_default + 1 > par->aperture.size >> 20) |
| 1598 | v_offset_default = (par->aperture.size >> 20) - (vram + 1); |
| 1599 | |
| 1600 | par->fb.size = vram << 20; |
| 1601 | par->fb.offset = v_offset_default << 20; |
| 1602 | par->fb.offset >>= 12; |
| 1603 | |
| 1604 | par->iring.offset = par->fb.offset + (par->fb.size >> 12); |
| 1605 | par->iring.size = RINGBUFFER_SIZE; |
| 1606 | |
| 1607 | par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12); |
| 1608 | par->cursor_heap.size = 4096; |
| 1609 | } |
| 1610 | |
| 1611 | static int __devinit i810_alloc_agp_mem(struct fb_info *info) |
| 1612 | { |
| 1613 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 1614 | int size; |
| 1615 | struct agp_bridge_data *bridge; |
| 1616 | |
| 1617 | i810_fix_offsets(par); |
| 1618 | size = par->fb.size + par->iring.size; |
| 1619 | |
| 1620 | if (!(bridge = agp_backend_acquire(par->dev))) { |
| 1621 | printk("i810fb_alloc_fbmem: cannot acquire agpgart\n"); |
| 1622 | return -ENODEV; |
| 1623 | } |
| 1624 | if (!(par->i810_gtt.i810_fb_memory = |
| 1625 | agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) { |
| 1626 | printk("i810fb_alloc_fbmem: can't allocate framebuffer " |
| 1627 | "memory\n"); |
| 1628 | agp_backend_release(bridge); |
| 1629 | return -ENOMEM; |
| 1630 | } |
| 1631 | if (agp_bind_memory(par->i810_gtt.i810_fb_memory, |
| 1632 | par->fb.offset)) { |
| 1633 | printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n"); |
| 1634 | agp_backend_release(bridge); |
| 1635 | return -EBUSY; |
| 1636 | } |
| 1637 | |
| 1638 | if (!(par->i810_gtt.i810_cursor_memory = |
| 1639 | agp_allocate_memory(bridge, par->cursor_heap.size >> 12, |
| 1640 | AGP_PHYSICAL_MEMORY))) { |
| 1641 | printk("i810fb_alloc_cursormem: can't allocate" |
| 1642 | "cursor memory\n"); |
| 1643 | agp_backend_release(bridge); |
| 1644 | return -ENOMEM; |
| 1645 | } |
| 1646 | if (agp_bind_memory(par->i810_gtt.i810_cursor_memory, |
| 1647 | par->cursor_heap.offset)) { |
| 1648 | printk("i810fb_alloc_cursormem: cannot bind cursor memory\n"); |
| 1649 | agp_backend_release(bridge); |
| 1650 | return -EBUSY; |
| 1651 | } |
| 1652 | |
| 1653 | par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical; |
| 1654 | |
| 1655 | i810_fix_pointers(par); |
| 1656 | |
| 1657 | agp_backend_release(bridge); |
| 1658 | |
| 1659 | return 0; |
| 1660 | } |
| 1661 | |
| 1662 | /*************************************************************** |
| 1663 | * Initialization * |
| 1664 | ***************************************************************/ |
| 1665 | |
| 1666 | /** |
| 1667 | * i810_init_monspecs |
| 1668 | * @info: pointer to device specific info structure |
| 1669 | * |
| 1670 | * DESCRIPTION: |
| 1671 | * Sets the the user monitor's horizontal and vertical |
| 1672 | * frequency limits |
| 1673 | */ |
| 1674 | static void __devinit i810_init_monspecs(struct fb_info *info) |
| 1675 | { |
| 1676 | if (!hsync1) |
| 1677 | hsync1 = HFMIN; |
| 1678 | if (!hsync2) |
| 1679 | hsync2 = HFMAX; |
| 1680 | if (!info->monspecs.hfmax) |
| 1681 | info->monspecs.hfmax = hsync2; |
| 1682 | if (!info->monspecs.hfmin) |
| 1683 | info->monspecs.hfmin = hsync1; |
| 1684 | if (hsync2 < hsync1) |
| 1685 | info->monspecs.hfmin = hsync2; |
| 1686 | |
| 1687 | if (!vsync1) |
| 1688 | vsync1 = VFMIN; |
| 1689 | if (!vsync2) |
| 1690 | vsync2 = VFMAX; |
| 1691 | if (IS_DVT && vsync1 < 60) |
| 1692 | vsync1 = 60; |
| 1693 | if (!info->monspecs.vfmax) |
| 1694 | info->monspecs.vfmax = vsync2; |
| 1695 | if (!info->monspecs.vfmin) |
| 1696 | info->monspecs.vfmin = vsync1; |
| 1697 | if (vsync2 < vsync1) |
| 1698 | info->monspecs.vfmin = vsync2; |
| 1699 | } |
| 1700 | |
| 1701 | /** |
| 1702 | * i810_init_defaults - initializes default values to use |
| 1703 | * @par: pointer to i810fb_par structure |
| 1704 | * @info: pointer to current fb_info structure |
| 1705 | */ |
| 1706 | static void __devinit i810_init_defaults(struct i810fb_par *par, |
| 1707 | struct fb_info *info) |
| 1708 | { |
| 1709 | if (voffset) |
| 1710 | v_offset_default = voffset; |
| 1711 | else if (par->aperture.size > 32 * 1024 * 1024) |
| 1712 | v_offset_default = 16; |
| 1713 | else |
| 1714 | v_offset_default = 8; |
| 1715 | |
| 1716 | if (!vram) |
| 1717 | vram = 1; |
| 1718 | |
| 1719 | if (accel) |
| 1720 | par->dev_flags |= HAS_ACCELERATION; |
| 1721 | |
| 1722 | if (sync) |
| 1723 | par->dev_flags |= ALWAYS_SYNC; |
| 1724 | |
| 1725 | if (bpp < 8) |
| 1726 | bpp = 8; |
| 1727 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | par->i810fb_ops = i810fb_ops; |
Antonino A. Daplas | 595e8a9 | 2005-09-12 09:15:16 +0800 | [diff] [blame] | 1729 | |
| 1730 | if (xres) |
| 1731 | info->var.xres = xres; |
| 1732 | else |
| 1733 | info->var.xres = 640; |
| 1734 | |
| 1735 | if (yres) |
| 1736 | info->var.yres = yres; |
| 1737 | else |
| 1738 | info->var.yres = 480; |
| 1739 | |
| 1740 | if (!vyres) |
| 1741 | vyres = (vram << 20)/(info->var.xres*bpp >> 3); |
| 1742 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1743 | info->var.yres_virtual = vyres; |
| 1744 | info->var.bits_per_pixel = bpp; |
| 1745 | |
| 1746 | if (dcolor) |
| 1747 | info->var.nonstd = 1; |
| 1748 | |
| 1749 | if (par->dev_flags & HAS_ACCELERATION) |
| 1750 | info->var.accel_flags = 1; |
| 1751 | |
| 1752 | i810_init_monspecs(info); |
| 1753 | } |
| 1754 | |
| 1755 | /** |
| 1756 | * i810_init_device - initialize device |
| 1757 | * @par: pointer to i810fb_par structure |
| 1758 | */ |
| 1759 | static void __devinit i810_init_device(struct i810fb_par *par) |
| 1760 | { |
| 1761 | u8 reg; |
| 1762 | u8 __iomem *mmio = par->mmio_start_virtual; |
| 1763 | |
| 1764 | if (mtrr) set_mtrr(par); |
| 1765 | |
| 1766 | i810_init_cursor(par); |
| 1767 | |
| 1768 | /* mvo: enable external vga-connector (for laptops) */ |
Antonino A. Daplas | 747a505 | 2005-09-12 09:16:47 +0800 | [diff] [blame] | 1769 | if (extvga) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1770 | i810_writel(HVSYNC, mmio, 0); |
| 1771 | i810_writel(PWR_CLKC, mmio, 3); |
| 1772 | } |
| 1773 | |
| 1774 | pci_read_config_byte(par->dev, 0x50, ®); |
| 1775 | reg &= FREQ_MASK; |
| 1776 | par->mem_freq = (reg) ? 133 : 100; |
| 1777 | |
| 1778 | } |
| 1779 | |
| 1780 | static int __devinit |
| 1781 | i810_allocate_pci_resource(struct i810fb_par *par, |
| 1782 | const struct pci_device_id *entry) |
| 1783 | { |
| 1784 | int err; |
| 1785 | |
| 1786 | if ((err = pci_enable_device(par->dev))) { |
| 1787 | printk("i810fb_init: cannot enable device\n"); |
| 1788 | return err; |
| 1789 | } |
| 1790 | par->res_flags |= PCI_DEVICE_ENABLED; |
| 1791 | |
| 1792 | if (pci_resource_len(par->dev, 0) > 512 * 1024) { |
| 1793 | par->aperture.physical = pci_resource_start(par->dev, 0); |
| 1794 | par->aperture.size = pci_resource_len(par->dev, 0); |
| 1795 | par->mmio_start_phys = pci_resource_start(par->dev, 1); |
| 1796 | } else { |
| 1797 | par->aperture.physical = pci_resource_start(par->dev, 1); |
| 1798 | par->aperture.size = pci_resource_len(par->dev, 1); |
| 1799 | par->mmio_start_phys = pci_resource_start(par->dev, 0); |
| 1800 | } |
| 1801 | if (!par->aperture.size) { |
| 1802 | printk("i810fb_init: device is disabled\n"); |
| 1803 | return -ENOMEM; |
| 1804 | } |
| 1805 | |
| 1806 | if (!request_mem_region(par->aperture.physical, |
| 1807 | par->aperture.size, |
| 1808 | i810_pci_list[entry->driver_data])) { |
| 1809 | printk("i810fb_init: cannot request framebuffer region\n"); |
| 1810 | return -ENODEV; |
| 1811 | } |
| 1812 | par->res_flags |= FRAMEBUFFER_REQ; |
| 1813 | |
| 1814 | par->aperture.virtual = ioremap_nocache(par->aperture.physical, |
| 1815 | par->aperture.size); |
| 1816 | if (!par->aperture.virtual) { |
| 1817 | printk("i810fb_init: cannot remap framebuffer region\n"); |
| 1818 | return -ENODEV; |
| 1819 | } |
| 1820 | |
| 1821 | if (!request_mem_region(par->mmio_start_phys, |
| 1822 | MMIO_SIZE, |
| 1823 | i810_pci_list[entry->driver_data])) { |
| 1824 | printk("i810fb_init: cannot request mmio region\n"); |
| 1825 | return -ENODEV; |
| 1826 | } |
| 1827 | par->res_flags |= MMIO_REQ; |
| 1828 | |
| 1829 | par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys, |
| 1830 | MMIO_SIZE); |
| 1831 | if (!par->mmio_start_virtual) { |
| 1832 | printk("i810fb_init: cannot remap mmio region\n"); |
| 1833 | return -ENODEV; |
| 1834 | } |
| 1835 | |
| 1836 | return 0; |
| 1837 | } |
| 1838 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1839 | static void __devinit i810fb_find_init_mode(struct fb_info *info) |
| 1840 | { |
| 1841 | struct fb_videomode mode; |
| 1842 | struct fb_var_screeninfo var; |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 1843 | struct fb_monspecs *specs = &info->monspecs; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1844 | int found = 0; |
| 1845 | #ifdef CONFIG_FB_I810_I2C |
| 1846 | int i; |
| 1847 | int err; |
| 1848 | struct i810fb_par *par = info->par; |
| 1849 | #endif |
| 1850 | |
| 1851 | INIT_LIST_HEAD(&info->modelist); |
| 1852 | memset(&mode, 0, sizeof(struct fb_videomode)); |
| 1853 | var = info->var; |
| 1854 | #ifdef CONFIG_FB_I810_I2C |
| 1855 | i810_create_i2c_busses(par); |
| 1856 | |
Antonino A. Daplas | 5fab851 | 2005-11-07 01:00:50 -0800 | [diff] [blame] | 1857 | for (i = 0; i < 4; i++) { |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1858 | err = i810_probe_i2c_connector(info, &par->edid, i+1); |
| 1859 | if (!err) |
| 1860 | break; |
| 1861 | } |
| 1862 | |
| 1863 | if (!err) |
| 1864 | printk("i810fb_init_pci: DDC probe successful\n"); |
| 1865 | |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 1866 | fb_edid_to_monspecs(par->edid, specs); |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1867 | |
Antonino A. Daplas | 883f645 | 2005-09-12 09:13:32 +0800 | [diff] [blame] | 1868 | if (specs->modedb == NULL) |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1869 | printk("i810fb_init_pci: Unable to get Mode Database\n"); |
| 1870 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1871 | fb_videomode_to_modelist(specs->modedb, specs->modedb_len, |
| 1872 | &info->modelist); |
| 1873 | if (specs->modedb != NULL) { |
Antonino A. Daplas | 5ee1ef9 | 2005-11-07 01:00:55 -0800 | [diff] [blame] | 1874 | struct fb_videomode *m; |
Antonino A. Daplas | 595e8a9 | 2005-09-12 09:15:16 +0800 | [diff] [blame] | 1875 | |
Antonino A. Daplas | 5ee1ef9 | 2005-11-07 01:00:55 -0800 | [diff] [blame] | 1876 | if (xres && yres) { |
Antonino A. Daplas | 595e8a9 | 2005-09-12 09:15:16 +0800 | [diff] [blame] | 1877 | if ((m = fb_find_best_mode(&var, &info->modelist))) { |
| 1878 | mode = *m; |
| 1879 | found = 1; |
| 1880 | } |
| 1881 | } |
| 1882 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1883 | if (!found) { |
Antonino A. Daplas | 5ee1ef9 | 2005-11-07 01:00:55 -0800 | [diff] [blame] | 1884 | m = fb_find_best_display(&info->monspecs, &info->modelist); |
| 1885 | mode = *m; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1886 | found = 1; |
| 1887 | } |
| 1888 | |
| 1889 | fb_videomode_to_var(&var, &mode); |
| 1890 | } |
| 1891 | #endif |
| 1892 | if (mode_option) |
| 1893 | fb_find_mode(&var, info, mode_option, specs->modedb, |
| 1894 | specs->modedb_len, (found) ? &mode : NULL, |
| 1895 | info->var.bits_per_pixel); |
| 1896 | |
| 1897 | info->var = var; |
| 1898 | fb_destroy_modedb(specs->modedb); |
| 1899 | specs->modedb = NULL; |
| 1900 | } |
| 1901 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | #ifndef MODULE |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1903 | static int __devinit i810fb_setup(char *options) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | { |
| 1905 | char *this_opt, *suffix = NULL; |
| 1906 | |
| 1907 | if (!options || !*options) |
| 1908 | return 0; |
| 1909 | |
| 1910 | while ((this_opt = strsep(&options, ",")) != NULL) { |
| 1911 | if (!strncmp(this_opt, "mtrr", 4)) |
| 1912 | mtrr = 1; |
| 1913 | else if (!strncmp(this_opt, "accel", 5)) |
| 1914 | accel = 1; |
Antonino A. Daplas | 747a505 | 2005-09-12 09:16:47 +0800 | [diff] [blame] | 1915 | else if (!strncmp(this_opt, "extvga", 6)) |
| 1916 | extvga = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1917 | else if (!strncmp(this_opt, "sync", 4)) |
| 1918 | sync = 1; |
| 1919 | else if (!strncmp(this_opt, "vram:", 5)) |
| 1920 | vram = (simple_strtoul(this_opt+5, NULL, 0)); |
| 1921 | else if (!strncmp(this_opt, "voffset:", 8)) |
| 1922 | voffset = (simple_strtoul(this_opt+8, NULL, 0)); |
| 1923 | else if (!strncmp(this_opt, "xres:", 5)) |
| 1924 | xres = simple_strtoul(this_opt+5, NULL, 0); |
| 1925 | else if (!strncmp(this_opt, "yres:", 5)) |
| 1926 | yres = simple_strtoul(this_opt+5, NULL, 0); |
| 1927 | else if (!strncmp(this_opt, "vyres:", 6)) |
| 1928 | vyres = simple_strtoul(this_opt+6, NULL, 0); |
| 1929 | else if (!strncmp(this_opt, "bpp:", 4)) |
| 1930 | bpp = simple_strtoul(this_opt+4, NULL, 0); |
| 1931 | else if (!strncmp(this_opt, "hsync1:", 7)) { |
| 1932 | hsync1 = simple_strtoul(this_opt+7, &suffix, 0); |
| 1933 | if (strncmp(suffix, "H", 1)) |
| 1934 | hsync1 *= 1000; |
| 1935 | } else if (!strncmp(this_opt, "hsync2:", 7)) { |
| 1936 | hsync2 = simple_strtoul(this_opt+7, &suffix, 0); |
| 1937 | if (strncmp(suffix, "H", 1)) |
| 1938 | hsync2 *= 1000; |
| 1939 | } else if (!strncmp(this_opt, "vsync1:", 7)) |
| 1940 | vsync1 = simple_strtoul(this_opt+7, NULL, 0); |
| 1941 | else if (!strncmp(this_opt, "vsync2:", 7)) |
| 1942 | vsync2 = simple_strtoul(this_opt+7, NULL, 0); |
| 1943 | else if (!strncmp(this_opt, "dcolor", 6)) |
| 1944 | dcolor = 1; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1945 | else |
| 1946 | mode_option = this_opt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1947 | } |
| 1948 | return 0; |
| 1949 | } |
| 1950 | #endif |
| 1951 | |
| 1952 | static int __devinit i810fb_init_pci (struct pci_dev *dev, |
| 1953 | const struct pci_device_id *entry) |
| 1954 | { |
| 1955 | struct fb_info *info; |
| 1956 | struct i810fb_par *par = NULL; |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1957 | struct fb_videomode mode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1958 | int i, err = -1, vfreq, hfreq, pixclock; |
| 1959 | |
| 1960 | i = 0; |
| 1961 | |
| 1962 | info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev); |
| 1963 | if (!info) |
| 1964 | return -ENOMEM; |
| 1965 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1966 | par = info->par; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1967 | par->dev = dev; |
| 1968 | |
| 1969 | if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) { |
| 1970 | i810fb_release_resource(info, par); |
| 1971 | return -ENOMEM; |
| 1972 | } |
| 1973 | memset(info->pixmap.addr, 0, 8*1024); |
| 1974 | info->pixmap.size = 8*1024; |
| 1975 | info->pixmap.buf_align = 8; |
James Simmons | 58a6064 | 2005-06-21 17:17:08 -0700 | [diff] [blame] | 1976 | info->pixmap.access_align = 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1977 | info->pixmap.flags = FB_PIXMAP_SYSTEM; |
| 1978 | |
| 1979 | if ((err = i810_allocate_pci_resource(par, entry))) { |
| 1980 | i810fb_release_resource(info, par); |
| 1981 | return err; |
| 1982 | } |
| 1983 | |
| 1984 | i810_init_defaults(par, info); |
| 1985 | |
| 1986 | if ((err = i810_alloc_agp_mem(info))) { |
| 1987 | i810fb_release_resource(info, par); |
| 1988 | return err; |
| 1989 | } |
| 1990 | |
| 1991 | i810_init_device(par); |
| 1992 | |
| 1993 | info->screen_base = par->fb.virtual; |
| 1994 | info->fbops = &par->i810fb_ops; |
| 1995 | info->pseudo_palette = par->pseudo_palette; |
| 1996 | fb_alloc_cmap(&info->cmap, 256, 0); |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 1997 | i810fb_find_init_mode(info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1998 | |
| 1999 | if ((err = info->fbops->fb_check_var(&info->var, info))) { |
| 2000 | i810fb_release_resource(info, par); |
| 2001 | return err; |
| 2002 | } |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2003 | |
| 2004 | fb_var_to_videomode(&mode, &info->var); |
| 2005 | fb_add_videomode(&mode, &info->modelist); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | encode_fix(&info->fix, info); |
| 2007 | |
| 2008 | i810fb_init_ringbuffer(info); |
| 2009 | err = register_framebuffer(info); |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2010 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | if (err < 0) { |
| 2012 | i810fb_release_resource(info, par); |
| 2013 | printk("i810fb_init: cannot register framebuffer device\n"); |
| 2014 | return err; |
| 2015 | } |
| 2016 | |
| 2017 | pci_set_drvdata(dev, info); |
| 2018 | pixclock = 1000000000/(info->var.pixclock); |
| 2019 | pixclock *= 1000; |
| 2020 | hfreq = pixclock/(info->var.xres + info->var.left_margin + |
| 2021 | info->var.hsync_len + info->var.right_margin); |
| 2022 | vfreq = hfreq/(info->var.yres + info->var.upper_margin + |
| 2023 | info->var.vsync_len + info->var.lower_margin); |
| 2024 | |
| 2025 | printk("I810FB: fb%d : %s v%d.%d.%d%s\n" |
| 2026 | "I810FB: Video RAM : %dK\n" |
| 2027 | "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n" |
| 2028 | "I810FB: Mode : %dx%d-%dbpp@%dHz\n", |
| 2029 | info->node, |
| 2030 | i810_pci_list[entry->driver_data], |
| 2031 | VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION, |
| 2032 | (int) par->fb.size>>10, info->monspecs.hfmin/1000, |
| 2033 | info->monspecs.hfmax/1000, info->monspecs.vfmin, |
| 2034 | info->monspecs.vfmax, info->var.xres, |
| 2035 | info->var.yres, info->var.bits_per_pixel, vfreq); |
| 2036 | return 0; |
| 2037 | } |
| 2038 | |
| 2039 | /*************************************************************** |
| 2040 | * De-initialization * |
| 2041 | ***************************************************************/ |
| 2042 | |
| 2043 | static void i810fb_release_resource(struct fb_info *info, |
| 2044 | struct i810fb_par *par) |
| 2045 | { |
| 2046 | struct gtt_data *gtt = &par->i810_gtt; |
| 2047 | unset_mtrr(par); |
| 2048 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2049 | i810_delete_i2c_busses(par); |
| 2050 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2051 | if (par->i810_gtt.i810_cursor_memory) |
| 2052 | agp_free_memory(gtt->i810_cursor_memory); |
| 2053 | if (par->i810_gtt.i810_fb_memory) |
| 2054 | agp_free_memory(gtt->i810_fb_memory); |
| 2055 | |
| 2056 | if (par->mmio_start_virtual) |
| 2057 | iounmap(par->mmio_start_virtual); |
| 2058 | if (par->aperture.virtual) |
| 2059 | iounmap(par->aperture.virtual); |
Jesper Juhl | 6044ec8 | 2005-11-07 01:01:32 -0800 | [diff] [blame^] | 2060 | kfree(par->edid); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2061 | if (par->res_flags & FRAMEBUFFER_REQ) |
| 2062 | release_mem_region(par->aperture.physical, |
| 2063 | par->aperture.size); |
| 2064 | if (par->res_flags & MMIO_REQ) |
| 2065 | release_mem_region(par->mmio_start_phys, MMIO_SIZE); |
| 2066 | |
| 2067 | if (par->res_flags & PCI_DEVICE_ENABLED) |
| 2068 | pci_disable_device(par->dev); |
| 2069 | |
| 2070 | framebuffer_release(info); |
| 2071 | |
| 2072 | } |
| 2073 | |
| 2074 | static void __exit i810fb_remove_pci(struct pci_dev *dev) |
| 2075 | { |
| 2076 | struct fb_info *info = pci_get_drvdata(dev); |
| 2077 | struct i810fb_par *par = (struct i810fb_par *) info->par; |
| 2078 | |
| 2079 | unregister_framebuffer(info); |
| 2080 | i810fb_release_resource(info, par); |
| 2081 | pci_set_drvdata(dev, NULL); |
| 2082 | printk("cleanup_module: unloaded i810 framebuffer device\n"); |
| 2083 | } |
| 2084 | |
| 2085 | #ifndef MODULE |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2086 | static int __devinit i810fb_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2087 | { |
| 2088 | char *option = NULL; |
| 2089 | |
| 2090 | if (fb_get_options("i810fb", &option)) |
| 2091 | return -ENODEV; |
| 2092 | i810fb_setup(option); |
| 2093 | |
| 2094 | return pci_register_driver(&i810fb_driver); |
| 2095 | } |
| 2096 | #endif |
| 2097 | |
| 2098 | /********************************************************************* |
| 2099 | * Modularization * |
| 2100 | *********************************************************************/ |
| 2101 | |
| 2102 | #ifdef MODULE |
| 2103 | |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2104 | static int __devinit i810fb_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2105 | { |
| 2106 | hsync1 *= 1000; |
| 2107 | hsync2 *= 1000; |
| 2108 | |
| 2109 | return pci_register_driver(&i810fb_driver); |
| 2110 | } |
| 2111 | |
| 2112 | module_param(vram, int, 0); |
| 2113 | MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB" |
| 2114 | " (default=4)"); |
| 2115 | module_param(voffset, int, 0); |
| 2116 | MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer " |
| 2117 | "memory (0 to maximum aperture size), in MiB (default = 48)"); |
| 2118 | module_param(bpp, int, 0); |
| 2119 | MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel" |
| 2120 | " (default = 8)"); |
| 2121 | module_param(xres, int, 0); |
| 2122 | MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)"); |
| 2123 | module_param(yres, int, 0); |
| 2124 | MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)"); |
| 2125 | module_param(vyres,int, 0); |
| 2126 | MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines" |
| 2127 | " (default = 480)"); |
| 2128 | module_param(hsync1, int, 0); |
| 2129 | MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz" |
Denis Vlasenko | db9f1d9 | 2005-05-01 08:59:24 -0700 | [diff] [blame] | 2130 | " (default = 29)"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2131 | module_param(hsync2, int, 0); |
| 2132 | MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz" |
Denis Vlasenko | db9f1d9 | 2005-05-01 08:59:24 -0700 | [diff] [blame] | 2133 | " (default = 30)"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2134 | module_param(vsync1, int, 0); |
| 2135 | MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz" |
| 2136 | " (default = 50)"); |
| 2137 | module_param(vsync2, int, 0); |
| 2138 | MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz" |
| 2139 | " (default = 60)"); |
| 2140 | module_param(accel, bool, 0); |
| 2141 | MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)"); |
| 2142 | module_param(mtrr, bool, 0); |
| 2143 | MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)"); |
Antonino A. Daplas | 747a505 | 2005-09-12 09:16:47 +0800 | [diff] [blame] | 2144 | module_param(extvga, bool, 0); |
| 2145 | MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2146 | module_param(sync, bool, 0); |
| 2147 | MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing" |
| 2148 | " (default = 0)"); |
| 2149 | module_param(dcolor, bool, 0); |
| 2150 | MODULE_PARM_DESC(dcolor, "use DirectColor visuals" |
| 2151 | " (default = 0 = TrueColor)"); |
Antonino A. Daplas | 74f6ae8 | 2005-09-09 13:10:04 -0700 | [diff] [blame] | 2152 | module_param(mode_option, charp, 0); |
| 2153 | MODULE_PARM_DESC(mode_option, "Specify initial video mode"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2154 | |
| 2155 | MODULE_AUTHOR("Tony A. Daplas"); |
| 2156 | MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and" |
| 2157 | " compatible cards"); |
| 2158 | MODULE_LICENSE("GPL"); |
| 2159 | |
| 2160 | static void __exit i810fb_exit(void) |
| 2161 | { |
| 2162 | pci_unregister_driver(&i810fb_driver); |
| 2163 | } |
| 2164 | module_exit(i810fb_exit); |
| 2165 | |
| 2166 | #endif /* MODULE */ |
| 2167 | |
| 2168 | module_init(i810fb_init); |