Netanel Belgazal | 1738cd3 | 2016-08-10 14:03:22 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Amazon.com, Inc. or its affiliates. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef ENA_COM |
| 34 | #define ENA_COM |
| 35 | |
| 36 | #include <linux/delay.h> |
| 37 | #include <linux/dma-mapping.h> |
| 38 | #include <linux/gfp.h> |
| 39 | #include <linux/sched.h> |
| 40 | #include <linux/sizes.h> |
| 41 | #include <linux/spinlock.h> |
| 42 | #include <linux/types.h> |
| 43 | #include <linux/wait.h> |
| 44 | |
| 45 | #include "ena_common_defs.h" |
| 46 | #include "ena_admin_defs.h" |
| 47 | #include "ena_eth_io_defs.h" |
| 48 | #include "ena_regs_defs.h" |
| 49 | |
| 50 | #undef pr_fmt |
| 51 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 52 | |
| 53 | #define ENA_MAX_NUM_IO_QUEUES 128U |
| 54 | /* We need to queues for each IO (on for Tx and one for Rx) */ |
| 55 | #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) |
| 56 | |
| 57 | #define ENA_MAX_HANDLERS 256 |
| 58 | |
| 59 | #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 |
| 60 | |
| 61 | /* Unit in usec */ |
| 62 | #define ENA_REG_READ_TIMEOUT 200000 |
| 63 | |
| 64 | #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) |
| 65 | #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) |
| 66 | #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) |
| 67 | |
| 68 | /*****************************************************************************/ |
| 69 | /*****************************************************************************/ |
| 70 | /* ENA adaptive interrupt moderation settings */ |
| 71 | |
| 72 | #define ENA_INTR_LOWEST_USECS (0) |
| 73 | #define ENA_INTR_LOWEST_PKTS (3) |
| 74 | #define ENA_INTR_LOWEST_BYTES (2 * 1524) |
| 75 | |
| 76 | #define ENA_INTR_LOW_USECS (32) |
| 77 | #define ENA_INTR_LOW_PKTS (12) |
| 78 | #define ENA_INTR_LOW_BYTES (16 * 1024) |
| 79 | |
| 80 | #define ENA_INTR_MID_USECS (80) |
| 81 | #define ENA_INTR_MID_PKTS (48) |
| 82 | #define ENA_INTR_MID_BYTES (64 * 1024) |
| 83 | |
| 84 | #define ENA_INTR_HIGH_USECS (128) |
| 85 | #define ENA_INTR_HIGH_PKTS (96) |
| 86 | #define ENA_INTR_HIGH_BYTES (128 * 1024) |
| 87 | |
| 88 | #define ENA_INTR_HIGHEST_USECS (192) |
| 89 | #define ENA_INTR_HIGHEST_PKTS (128) |
| 90 | #define ENA_INTR_HIGHEST_BYTES (192 * 1024) |
| 91 | |
| 92 | #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196 |
| 93 | #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4 |
| 94 | #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6 |
| 95 | #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 |
| 96 | #define ENA_INTR_MODER_LEVEL_STRIDE 2 |
| 97 | #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF |
| 98 | |
| 99 | enum ena_intr_moder_level { |
| 100 | ENA_INTR_MODER_LOWEST = 0, |
| 101 | ENA_INTR_MODER_LOW, |
| 102 | ENA_INTR_MODER_MID, |
| 103 | ENA_INTR_MODER_HIGH, |
| 104 | ENA_INTR_MODER_HIGHEST, |
| 105 | ENA_INTR_MAX_NUM_OF_LEVELS, |
| 106 | }; |
| 107 | |
| 108 | struct ena_intr_moder_entry { |
| 109 | unsigned int intr_moder_interval; |
| 110 | unsigned int pkts_per_interval; |
| 111 | unsigned int bytes_per_interval; |
| 112 | }; |
| 113 | |
| 114 | enum queue_direction { |
| 115 | ENA_COM_IO_QUEUE_DIRECTION_TX, |
| 116 | ENA_COM_IO_QUEUE_DIRECTION_RX |
| 117 | }; |
| 118 | |
| 119 | struct ena_com_buf { |
| 120 | dma_addr_t paddr; /**< Buffer physical address */ |
| 121 | u16 len; /**< Buffer length in bytes */ |
| 122 | }; |
| 123 | |
| 124 | struct ena_com_rx_buf_info { |
| 125 | u16 len; |
| 126 | u16 req_id; |
| 127 | }; |
| 128 | |
| 129 | struct ena_com_io_desc_addr { |
| 130 | u8 __iomem *pbuf_dev_addr; /* LLQ address */ |
| 131 | u8 *virt_addr; |
| 132 | dma_addr_t phys_addr; |
| 133 | }; |
| 134 | |
| 135 | struct ena_com_tx_meta { |
| 136 | u16 mss; |
| 137 | u16 l3_hdr_len; |
| 138 | u16 l3_hdr_offset; |
| 139 | u16 l4_hdr_len; /* In words */ |
| 140 | }; |
| 141 | |
| 142 | struct ena_com_io_cq { |
| 143 | struct ena_com_io_desc_addr cdesc_addr; |
| 144 | |
| 145 | /* Interrupt unmask register */ |
| 146 | u32 __iomem *unmask_reg; |
| 147 | |
| 148 | /* The completion queue head doorbell register */ |
| 149 | u32 __iomem *cq_head_db_reg; |
| 150 | |
| 151 | /* numa configuration register (for TPH) */ |
| 152 | u32 __iomem *numa_node_cfg_reg; |
| 153 | |
| 154 | /* The value to write to the above register to unmask |
| 155 | * the interrupt of this queue |
| 156 | */ |
| 157 | u32 msix_vector; |
| 158 | |
| 159 | enum queue_direction direction; |
| 160 | |
| 161 | /* holds the number of cdesc of the current packet */ |
| 162 | u16 cur_rx_pkt_cdesc_count; |
| 163 | /* save the firt cdesc idx of the current packet */ |
| 164 | u16 cur_rx_pkt_cdesc_start_idx; |
| 165 | |
| 166 | u16 q_depth; |
| 167 | /* Caller qid */ |
| 168 | u16 qid; |
| 169 | |
| 170 | /* Device queue index */ |
| 171 | u16 idx; |
| 172 | u16 head; |
| 173 | u16 last_head_update; |
| 174 | u8 phase; |
| 175 | u8 cdesc_entry_size_in_bytes; |
| 176 | |
| 177 | } ____cacheline_aligned; |
| 178 | |
| 179 | struct ena_com_io_sq { |
| 180 | struct ena_com_io_desc_addr desc_addr; |
| 181 | |
| 182 | u32 __iomem *db_addr; |
| 183 | u8 __iomem *header_addr; |
| 184 | |
| 185 | enum queue_direction direction; |
| 186 | enum ena_admin_placement_policy_type mem_queue_type; |
| 187 | |
| 188 | u32 msix_vector; |
| 189 | struct ena_com_tx_meta cached_tx_meta; |
| 190 | |
| 191 | u16 q_depth; |
| 192 | u16 qid; |
| 193 | |
| 194 | u16 idx; |
| 195 | u16 tail; |
| 196 | u16 next_to_comp; |
| 197 | u32 tx_max_header_size; |
| 198 | u8 phase; |
| 199 | u8 desc_entry_size; |
| 200 | u8 dma_addr_bits; |
| 201 | } ____cacheline_aligned; |
| 202 | |
| 203 | struct ena_com_admin_cq { |
| 204 | struct ena_admin_acq_entry *entries; |
| 205 | dma_addr_t dma_addr; |
| 206 | |
| 207 | u16 head; |
| 208 | u8 phase; |
| 209 | }; |
| 210 | |
| 211 | struct ena_com_admin_sq { |
| 212 | struct ena_admin_aq_entry *entries; |
| 213 | dma_addr_t dma_addr; |
| 214 | |
| 215 | u32 __iomem *db_addr; |
| 216 | |
| 217 | u16 head; |
| 218 | u16 tail; |
| 219 | u8 phase; |
| 220 | |
| 221 | }; |
| 222 | |
| 223 | struct ena_com_stats_admin { |
| 224 | u32 aborted_cmd; |
| 225 | u32 submitted_cmd; |
| 226 | u32 completed_cmd; |
| 227 | u32 out_of_space; |
| 228 | u32 no_completion; |
| 229 | }; |
| 230 | |
| 231 | struct ena_com_admin_queue { |
| 232 | void *q_dmadev; |
| 233 | spinlock_t q_lock; /* spinlock for the admin queue */ |
| 234 | struct ena_comp_ctx *comp_ctx; |
| 235 | u16 q_depth; |
| 236 | struct ena_com_admin_cq cq; |
| 237 | struct ena_com_admin_sq sq; |
| 238 | |
| 239 | /* Indicate if the admin queue should poll for completion */ |
| 240 | bool polling; |
| 241 | |
| 242 | u16 curr_cmd_id; |
| 243 | |
| 244 | /* Indicate that the ena was initialized and can |
| 245 | * process new admin commands |
| 246 | */ |
| 247 | bool running_state; |
| 248 | |
| 249 | /* Count the number of outstanding admin commands */ |
| 250 | atomic_t outstanding_cmds; |
| 251 | |
| 252 | struct ena_com_stats_admin stats; |
| 253 | }; |
| 254 | |
| 255 | struct ena_aenq_handlers; |
| 256 | |
| 257 | struct ena_com_aenq { |
| 258 | u16 head; |
| 259 | u8 phase; |
| 260 | struct ena_admin_aenq_entry *entries; |
| 261 | dma_addr_t dma_addr; |
| 262 | u16 q_depth; |
| 263 | struct ena_aenq_handlers *aenq_handlers; |
| 264 | }; |
| 265 | |
| 266 | struct ena_com_mmio_read { |
| 267 | struct ena_admin_ena_mmio_req_read_less_resp *read_resp; |
| 268 | dma_addr_t read_resp_dma_addr; |
| 269 | u16 seq_num; |
| 270 | bool readless_supported; |
| 271 | /* spin lock to ensure a single outstanding read */ |
| 272 | spinlock_t lock; |
| 273 | }; |
| 274 | |
| 275 | struct ena_rss { |
| 276 | /* Indirect table */ |
| 277 | u16 *host_rss_ind_tbl; |
| 278 | struct ena_admin_rss_ind_table_entry *rss_ind_tbl; |
| 279 | dma_addr_t rss_ind_tbl_dma_addr; |
| 280 | u16 tbl_log_size; |
| 281 | |
| 282 | /* Hash key */ |
| 283 | enum ena_admin_hash_functions hash_func; |
| 284 | struct ena_admin_feature_rss_flow_hash_control *hash_key; |
| 285 | dma_addr_t hash_key_dma_addr; |
| 286 | u32 hash_init_val; |
| 287 | |
| 288 | /* Flow Control */ |
| 289 | struct ena_admin_feature_rss_hash_control *hash_ctrl; |
| 290 | dma_addr_t hash_ctrl_dma_addr; |
| 291 | |
| 292 | }; |
| 293 | |
| 294 | struct ena_host_attribute { |
| 295 | /* Debug area */ |
| 296 | u8 *debug_area_virt_addr; |
| 297 | dma_addr_t debug_area_dma_addr; |
| 298 | u32 debug_area_size; |
| 299 | |
| 300 | /* Host information */ |
| 301 | struct ena_admin_host_info *host_info; |
| 302 | dma_addr_t host_info_dma_addr; |
| 303 | }; |
| 304 | |
| 305 | /* Each ena_dev is a PCI function. */ |
| 306 | struct ena_com_dev { |
| 307 | struct ena_com_admin_queue admin_queue; |
| 308 | struct ena_com_aenq aenq; |
| 309 | struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; |
| 310 | struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; |
| 311 | u8 __iomem *reg_bar; |
| 312 | void __iomem *mem_bar; |
| 313 | void *dmadev; |
| 314 | |
| 315 | enum ena_admin_placement_policy_type tx_mem_queue_type; |
| 316 | u32 tx_max_header_size; |
| 317 | u16 stats_func; /* Selected function for extended statistic dump */ |
| 318 | u16 stats_queue; /* Selected queue for extended statistic dump */ |
| 319 | |
| 320 | struct ena_com_mmio_read mmio_read; |
| 321 | |
| 322 | struct ena_rss rss; |
| 323 | u32 supported_features; |
| 324 | u32 dma_addr_bits; |
| 325 | |
| 326 | struct ena_host_attribute host_attr; |
| 327 | bool adaptive_coalescing; |
| 328 | u16 intr_delay_resolution; |
| 329 | u32 intr_moder_tx_interval; |
| 330 | struct ena_intr_moder_entry *intr_moder_tbl; |
| 331 | }; |
| 332 | |
| 333 | struct ena_com_dev_get_features_ctx { |
| 334 | struct ena_admin_queue_feature_desc max_queues; |
| 335 | struct ena_admin_device_attr_feature_desc dev_attr; |
| 336 | struct ena_admin_feature_aenq_desc aenq; |
| 337 | struct ena_admin_feature_offload_desc offload; |
| 338 | }; |
| 339 | |
| 340 | struct ena_com_create_io_ctx { |
| 341 | enum ena_admin_placement_policy_type mem_queue_type; |
| 342 | enum queue_direction direction; |
| 343 | int numa_node; |
| 344 | u32 msix_vector; |
| 345 | u16 queue_size; |
| 346 | u16 qid; |
| 347 | }; |
| 348 | |
| 349 | typedef void (*ena_aenq_handler)(void *data, |
| 350 | struct ena_admin_aenq_entry *aenq_e); |
| 351 | |
| 352 | /* Holds aenq handlers. Indexed by AENQ event group */ |
| 353 | struct ena_aenq_handlers { |
| 354 | ena_aenq_handler handlers[ENA_MAX_HANDLERS]; |
| 355 | ena_aenq_handler unimplemented_handler; |
| 356 | }; |
| 357 | |
| 358 | /*****************************************************************************/ |
| 359 | /*****************************************************************************/ |
| 360 | |
| 361 | /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism |
| 362 | * @ena_dev: ENA communication layer struct |
| 363 | * |
| 364 | * Initialize the register read mechanism. |
| 365 | * |
| 366 | * @note: This method must be the first stage in the initialization sequence. |
| 367 | * |
| 368 | * @return - 0 on success, negative value on failure. |
| 369 | */ |
| 370 | int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); |
| 371 | |
| 372 | /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism |
| 373 | * @ena_dev: ENA communication layer struct |
| 374 | * @readless_supported: readless mode (enable/disable) |
| 375 | */ |
| 376 | void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, |
| 377 | bool readless_supported); |
| 378 | |
| 379 | /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return |
| 380 | * value physical address. |
| 381 | * @ena_dev: ENA communication layer struct |
| 382 | */ |
| 383 | void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); |
| 384 | |
| 385 | /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism |
| 386 | * @ena_dev: ENA communication layer struct |
| 387 | */ |
| 388 | void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); |
| 389 | |
| 390 | /* ena_com_admin_init - Init the admin and the async queues |
| 391 | * @ena_dev: ENA communication layer struct |
| 392 | * @aenq_handlers: Those handlers to be called upon event. |
| 393 | * @init_spinlock: Indicate if this method should init the admin spinlock or |
| 394 | * the spinlock was init before (for example, in a case of FLR). |
| 395 | * |
| 396 | * Initialize the admin submission and completion queues. |
| 397 | * Initialize the asynchronous events notification queues. |
| 398 | * |
| 399 | * @return - 0 on success, negative value on failure. |
| 400 | */ |
| 401 | int ena_com_admin_init(struct ena_com_dev *ena_dev, |
| 402 | struct ena_aenq_handlers *aenq_handlers, |
| 403 | bool init_spinlock); |
| 404 | |
| 405 | /* ena_com_admin_destroy - Destroy the admin and the async events queues. |
| 406 | * @ena_dev: ENA communication layer struct |
| 407 | * |
| 408 | * @note: Before calling this method, the caller must validate that the device |
| 409 | * won't send any additional admin completions/aenq. |
| 410 | * To achieve that, a FLR is recommended. |
| 411 | */ |
| 412 | void ena_com_admin_destroy(struct ena_com_dev *ena_dev); |
| 413 | |
| 414 | /* ena_com_dev_reset - Perform device FLR to the device. |
| 415 | * @ena_dev: ENA communication layer struct |
| 416 | * |
| 417 | * @return - 0 on success, negative value on failure. |
| 418 | */ |
| 419 | int ena_com_dev_reset(struct ena_com_dev *ena_dev); |
| 420 | |
| 421 | /* ena_com_create_io_queue - Create io queue. |
| 422 | * @ena_dev: ENA communication layer struct |
| 423 | * @ctx - create context structure |
| 424 | * |
| 425 | * Create the submission and the completion queues. |
| 426 | * |
| 427 | * @return - 0 on success, negative value on failure. |
| 428 | */ |
| 429 | int ena_com_create_io_queue(struct ena_com_dev *ena_dev, |
| 430 | struct ena_com_create_io_ctx *ctx); |
| 431 | |
| 432 | /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. |
| 433 | * @ena_dev: ENA communication layer struct |
| 434 | * @qid - the caller virtual queue id. |
| 435 | */ |
| 436 | void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); |
| 437 | |
| 438 | /* ena_com_get_io_handlers - Return the io queue handlers |
| 439 | * @ena_dev: ENA communication layer struct |
| 440 | * @qid - the caller virtual queue id. |
| 441 | * @io_sq - IO submission queue handler |
| 442 | * @io_cq - IO completion queue handler. |
| 443 | * |
| 444 | * @return - 0 on success, negative value on failure. |
| 445 | */ |
| 446 | int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, |
| 447 | struct ena_com_io_sq **io_sq, |
| 448 | struct ena_com_io_cq **io_cq); |
| 449 | |
| 450 | /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications |
| 451 | * @ena_dev: ENA communication layer struct |
| 452 | * |
| 453 | * After this method, aenq event can be received via AENQ. |
| 454 | */ |
| 455 | void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); |
| 456 | |
| 457 | /* ena_com_set_admin_running_state - Set the state of the admin queue |
| 458 | * @ena_dev: ENA communication layer struct |
| 459 | * |
| 460 | * Change the state of the admin queue (enable/disable) |
| 461 | */ |
| 462 | void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); |
| 463 | |
| 464 | /* ena_com_get_admin_running_state - Get the admin queue state |
| 465 | * @ena_dev: ENA communication layer struct |
| 466 | * |
| 467 | * Retrieve the state of the admin queue (enable/disable) |
| 468 | * |
| 469 | * @return - current polling mode (enable/disable) |
| 470 | */ |
| 471 | bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); |
| 472 | |
| 473 | /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode |
| 474 | * @ena_dev: ENA communication layer struct |
| 475 | * @polling: ENAble/Disable polling mode |
| 476 | * |
| 477 | * Set the admin completion mode. |
| 478 | */ |
| 479 | void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); |
| 480 | |
| 481 | /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode |
| 482 | * @ena_dev: ENA communication layer struct |
| 483 | * |
| 484 | * Get the admin completion mode. |
| 485 | * If polling mode is on, ena_com_execute_admin_command will perform a |
| 486 | * polling on the admin completion queue for the commands completion, |
| 487 | * otherwise it will wait on wait event. |
| 488 | * |
| 489 | * @return state |
| 490 | */ |
| 491 | bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev); |
| 492 | |
| 493 | /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler |
| 494 | * @ena_dev: ENA communication layer struct |
| 495 | * |
| 496 | * This method go over the admin completion queue and wake up all the pending |
| 497 | * threads that wait on the commands wait event. |
| 498 | * |
| 499 | * @note: Should be called after MSI-X interrupt. |
| 500 | */ |
| 501 | void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); |
| 502 | |
| 503 | /* ena_com_aenq_intr_handler - AENQ interrupt handler |
| 504 | * @ena_dev: ENA communication layer struct |
| 505 | * |
| 506 | * This method go over the async event notification queue and call the proper |
| 507 | * aenq handler. |
| 508 | */ |
| 509 | void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); |
| 510 | |
| 511 | /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. |
| 512 | * @ena_dev: ENA communication layer struct |
| 513 | * |
| 514 | * This method aborts all the outstanding admin commands. |
| 515 | * The caller should then call ena_com_wait_for_abort_completion to make sure |
| 516 | * all the commands were completed. |
| 517 | */ |
| 518 | void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); |
| 519 | |
| 520 | /* ena_com_wait_for_abort_completion - Wait for admin commands abort. |
| 521 | * @ena_dev: ENA communication layer struct |
| 522 | * |
| 523 | * This method wait until all the outstanding admin commands will be completed. |
| 524 | */ |
| 525 | void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); |
| 526 | |
| 527 | /* ena_com_validate_version - Validate the device parameters |
| 528 | * @ena_dev: ENA communication layer struct |
| 529 | * |
| 530 | * This method validate the device parameters are the same as the saved |
| 531 | * parameters in ena_dev. |
| 532 | * This method is useful after device reset, to validate the device mac address |
| 533 | * and the device offloads are the same as before the reset. |
| 534 | * |
| 535 | * @return - 0 on success negative value otherwise. |
| 536 | */ |
| 537 | int ena_com_validate_version(struct ena_com_dev *ena_dev); |
| 538 | |
| 539 | /* ena_com_get_link_params - Retrieve physical link parameters. |
| 540 | * @ena_dev: ENA communication layer struct |
| 541 | * @resp: Link parameters |
| 542 | * |
| 543 | * Retrieve the physical link parameters, |
| 544 | * like speed, auto-negotiation and full duplex support. |
| 545 | * |
| 546 | * @return - 0 on Success negative value otherwise. |
| 547 | */ |
| 548 | int ena_com_get_link_params(struct ena_com_dev *ena_dev, |
| 549 | struct ena_admin_get_feat_resp *resp); |
| 550 | |
| 551 | /* ena_com_get_dma_width - Retrieve physical dma address width the device |
| 552 | * supports. |
| 553 | * @ena_dev: ENA communication layer struct |
| 554 | * |
| 555 | * Retrieve the maximum physical address bits the device can handle. |
| 556 | * |
| 557 | * @return: > 0 on Success and negative value otherwise. |
| 558 | */ |
| 559 | int ena_com_get_dma_width(struct ena_com_dev *ena_dev); |
| 560 | |
| 561 | /* ena_com_set_aenq_config - Set aenq groups configurations |
| 562 | * @ena_dev: ENA communication layer struct |
| 563 | * @groups flag: bit fields flags of enum ena_admin_aenq_group. |
| 564 | * |
| 565 | * Configure which aenq event group the driver would like to receive. |
| 566 | * |
| 567 | * @return: 0 on Success and negative value otherwise. |
| 568 | */ |
| 569 | int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); |
| 570 | |
| 571 | /* ena_com_get_dev_attr_feat - Get device features |
| 572 | * @ena_dev: ENA communication layer struct |
| 573 | * @get_feat_ctx: returned context that contain the get features. |
| 574 | * |
| 575 | * @return: 0 on Success and negative value otherwise. |
| 576 | */ |
| 577 | int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, |
| 578 | struct ena_com_dev_get_features_ctx *get_feat_ctx); |
| 579 | |
| 580 | /* ena_com_get_dev_basic_stats - Get device basic statistics |
| 581 | * @ena_dev: ENA communication layer struct |
| 582 | * @stats: stats return value |
| 583 | * |
| 584 | * @return: 0 on Success and negative value otherwise. |
| 585 | */ |
| 586 | int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, |
| 587 | struct ena_admin_basic_stats *stats); |
| 588 | |
| 589 | /* ena_com_set_dev_mtu - Configure the device mtu. |
| 590 | * @ena_dev: ENA communication layer struct |
| 591 | * @mtu: mtu value |
| 592 | * |
| 593 | * @return: 0 on Success and negative value otherwise. |
| 594 | */ |
| 595 | int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); |
| 596 | |
| 597 | /* ena_com_get_offload_settings - Retrieve the device offloads capabilities |
| 598 | * @ena_dev: ENA communication layer struct |
| 599 | * @offlad: offload return value |
| 600 | * |
| 601 | * @return: 0 on Success and negative value otherwise. |
| 602 | */ |
| 603 | int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, |
| 604 | struct ena_admin_feature_offload_desc *offload); |
| 605 | |
| 606 | /* ena_com_rss_init - Init RSS |
| 607 | * @ena_dev: ENA communication layer struct |
| 608 | * @log_size: indirection log size |
| 609 | * |
| 610 | * Allocate RSS/RFS resources. |
| 611 | * The caller then can configure rss using ena_com_set_hash_function, |
| 612 | * ena_com_set_hash_ctrl and ena_com_indirect_table_set. |
| 613 | * |
| 614 | * @return: 0 on Success and negative value otherwise. |
| 615 | */ |
| 616 | int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); |
| 617 | |
| 618 | /* ena_com_rss_destroy - Destroy rss |
| 619 | * @ena_dev: ENA communication layer struct |
| 620 | * |
| 621 | * Free all the RSS/RFS resources. |
| 622 | */ |
| 623 | void ena_com_rss_destroy(struct ena_com_dev *ena_dev); |
| 624 | |
| 625 | /* ena_com_fill_hash_function - Fill RSS hash function |
| 626 | * @ena_dev: ENA communication layer struct |
| 627 | * @func: The hash function (Toeplitz or crc) |
| 628 | * @key: Hash key (for toeplitz hash) |
| 629 | * @key_len: key length (max length 10 DW) |
| 630 | * @init_val: initial value for the hash function |
| 631 | * |
| 632 | * Fill the ena_dev resources with the desire hash function, hash key, key_len |
| 633 | * and key initial value (if needed by the hash function). |
| 634 | * To flush the key into the device the caller should call |
| 635 | * ena_com_set_hash_function. |
| 636 | * |
| 637 | * @return: 0 on Success and negative value otherwise. |
| 638 | */ |
| 639 | int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, |
| 640 | enum ena_admin_hash_functions func, |
| 641 | const u8 *key, u16 key_len, u32 init_val); |
| 642 | |
| 643 | /* ena_com_set_hash_function - Flush the hash function and it dependencies to |
| 644 | * the device. |
| 645 | * @ena_dev: ENA communication layer struct |
| 646 | * |
| 647 | * Flush the hash function and it dependencies (key, key length and |
| 648 | * initial value) if needed. |
| 649 | * |
| 650 | * @note: Prior to this method the caller should call ena_com_fill_hash_function |
| 651 | * |
| 652 | * @return: 0 on Success and negative value otherwise. |
| 653 | */ |
| 654 | int ena_com_set_hash_function(struct ena_com_dev *ena_dev); |
| 655 | |
| 656 | /* ena_com_get_hash_function - Retrieve the hash function and the hash key |
| 657 | * from the device. |
| 658 | * @ena_dev: ENA communication layer struct |
| 659 | * @func: hash function |
| 660 | * @key: hash key |
| 661 | * |
| 662 | * Retrieve the hash function and the hash key from the device. |
| 663 | * |
| 664 | * @note: If the caller called ena_com_fill_hash_function but didn't flash |
| 665 | * it to the device, the new configuration will be lost. |
| 666 | * |
| 667 | * @return: 0 on Success and negative value otherwise. |
| 668 | */ |
| 669 | int ena_com_get_hash_function(struct ena_com_dev *ena_dev, |
| 670 | enum ena_admin_hash_functions *func, |
| 671 | u8 *key); |
| 672 | |
| 673 | /* ena_com_fill_hash_ctrl - Fill RSS hash control |
| 674 | * @ena_dev: ENA communication layer struct. |
| 675 | * @proto: The protocol to configure. |
| 676 | * @hash_fields: bit mask of ena_admin_flow_hash_fields |
| 677 | * |
| 678 | * Fill the ena_dev resources with the desire hash control (the ethernet |
| 679 | * fields that take part of the hash) for a specific protocol. |
| 680 | * To flush the hash control to the device, the caller should call |
| 681 | * ena_com_set_hash_ctrl. |
| 682 | * |
| 683 | * @return: 0 on Success and negative value otherwise. |
| 684 | */ |
| 685 | int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, |
| 686 | enum ena_admin_flow_hash_proto proto, |
| 687 | u16 hash_fields); |
| 688 | |
| 689 | /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. |
| 690 | * @ena_dev: ENA communication layer struct |
| 691 | * |
| 692 | * Flush the hash control (the ethernet fields that take part of the hash) |
| 693 | * |
| 694 | * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. |
| 695 | * |
| 696 | * @return: 0 on Success and negative value otherwise. |
| 697 | */ |
| 698 | int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); |
| 699 | |
| 700 | /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. |
| 701 | * @ena_dev: ENA communication layer struct |
| 702 | * @proto: The protocol to retrieve. |
| 703 | * @fields: bit mask of ena_admin_flow_hash_fields. |
| 704 | * |
| 705 | * Retrieve the hash control from the device. |
| 706 | * |
| 707 | * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash |
| 708 | * it to the device, the new configuration will be lost. |
| 709 | * |
| 710 | * @return: 0 on Success and negative value otherwise. |
| 711 | */ |
| 712 | int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, |
| 713 | enum ena_admin_flow_hash_proto proto, |
| 714 | u16 *fields); |
| 715 | |
| 716 | /* ena_com_set_default_hash_ctrl - Set the hash control to a default |
| 717 | * configuration. |
| 718 | * @ena_dev: ENA communication layer struct |
| 719 | * |
| 720 | * Fill the ena_dev resources with the default hash control configuration. |
| 721 | * To flush the hash control to the device, the caller should call |
| 722 | * ena_com_set_hash_ctrl. |
| 723 | * |
| 724 | * @return: 0 on Success and negative value otherwise. |
| 725 | */ |
| 726 | int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); |
| 727 | |
| 728 | /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS |
| 729 | * indirection table |
| 730 | * @ena_dev: ENA communication layer struct. |
| 731 | * @entry_idx - indirection table entry. |
| 732 | * @entry_value - redirection value |
| 733 | * |
| 734 | * Fill a single entry of the RSS indirection table in the ena_dev resources. |
| 735 | * To flush the indirection table to the device, the called should call |
| 736 | * ena_com_indirect_table_set. |
| 737 | * |
| 738 | * @return: 0 on Success and negative value otherwise. |
| 739 | */ |
| 740 | int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, |
| 741 | u16 entry_idx, u16 entry_value); |
| 742 | |
| 743 | /* ena_com_indirect_table_set - Flush the indirection table to the device. |
| 744 | * @ena_dev: ENA communication layer struct |
| 745 | * |
| 746 | * Flush the indirection hash control to the device. |
| 747 | * Prior to this method the caller should call ena_com_indirect_table_fill_entry |
| 748 | * |
| 749 | * @return: 0 on Success and negative value otherwise. |
| 750 | */ |
| 751 | int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); |
| 752 | |
| 753 | /* ena_com_indirect_table_get - Retrieve the indirection table from the device. |
| 754 | * @ena_dev: ENA communication layer struct |
| 755 | * @ind_tbl: indirection table |
| 756 | * |
| 757 | * Retrieve the RSS indirection table from the device. |
| 758 | * |
| 759 | * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash |
| 760 | * it to the device, the new configuration will be lost. |
| 761 | * |
| 762 | * @return: 0 on Success and negative value otherwise. |
| 763 | */ |
| 764 | int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); |
| 765 | |
| 766 | /* ena_com_allocate_host_info - Allocate host info resources. |
| 767 | * @ena_dev: ENA communication layer struct |
| 768 | * |
| 769 | * @return: 0 on Success and negative value otherwise. |
| 770 | */ |
| 771 | int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); |
| 772 | |
| 773 | /* ena_com_allocate_debug_area - Allocate debug area. |
| 774 | * @ena_dev: ENA communication layer struct |
| 775 | * @debug_area_size - debug area size. |
| 776 | * |
| 777 | * @return: 0 on Success and negative value otherwise. |
| 778 | */ |
| 779 | int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, |
| 780 | u32 debug_area_size); |
| 781 | |
| 782 | /* ena_com_delete_debug_area - Free the debug area resources. |
| 783 | * @ena_dev: ENA communication layer struct |
| 784 | * |
| 785 | * Free the allocate debug area. |
| 786 | */ |
| 787 | void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); |
| 788 | |
| 789 | /* ena_com_delete_host_info - Free the host info resources. |
| 790 | * @ena_dev: ENA communication layer struct |
| 791 | * |
| 792 | * Free the allocate host info. |
| 793 | */ |
| 794 | void ena_com_delete_host_info(struct ena_com_dev *ena_dev); |
| 795 | |
| 796 | /* ena_com_set_host_attributes - Update the device with the host |
| 797 | * attributes (debug area and host info) base address. |
| 798 | * @ena_dev: ENA communication layer struct |
| 799 | * |
| 800 | * @return: 0 on Success and negative value otherwise. |
| 801 | */ |
| 802 | int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); |
| 803 | |
| 804 | /* ena_com_create_io_cq - Create io completion queue. |
| 805 | * @ena_dev: ENA communication layer struct |
| 806 | * @io_cq - io completion queue handler |
| 807 | |
| 808 | * Create IO completion queue. |
| 809 | * |
| 810 | * @return - 0 on success, negative value on failure. |
| 811 | */ |
| 812 | int ena_com_create_io_cq(struct ena_com_dev *ena_dev, |
| 813 | struct ena_com_io_cq *io_cq); |
| 814 | |
| 815 | /* ena_com_destroy_io_cq - Destroy io completion queue. |
| 816 | * @ena_dev: ENA communication layer struct |
| 817 | * @io_cq - io completion queue handler |
| 818 | |
| 819 | * Destroy IO completion queue. |
| 820 | * |
| 821 | * @return - 0 on success, negative value on failure. |
| 822 | */ |
| 823 | int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, |
| 824 | struct ena_com_io_cq *io_cq); |
| 825 | |
| 826 | /* ena_com_execute_admin_command - Execute admin command |
| 827 | * @admin_queue: admin queue. |
| 828 | * @cmd: the admin command to execute. |
| 829 | * @cmd_size: the command size. |
| 830 | * @cmd_completion: command completion return value. |
| 831 | * @cmd_comp_size: command completion size. |
| 832 | |
| 833 | * Submit an admin command and then wait until the device will return a |
| 834 | * completion. |
| 835 | * The completion will be copyed into cmd_comp. |
| 836 | * |
| 837 | * @return - 0 on success, negative value on failure. |
| 838 | */ |
| 839 | int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, |
| 840 | struct ena_admin_aq_entry *cmd, |
| 841 | size_t cmd_size, |
| 842 | struct ena_admin_acq_entry *cmd_comp, |
| 843 | size_t cmd_comp_size); |
| 844 | |
| 845 | /* ena_com_init_interrupt_moderation - Init interrupt moderation |
| 846 | * @ena_dev: ENA communication layer struct |
| 847 | * |
| 848 | * @return - 0 on success, negative value on failure. |
| 849 | */ |
| 850 | int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); |
| 851 | |
| 852 | /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources |
| 853 | * @ena_dev: ENA communication layer struct |
| 854 | */ |
| 855 | void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); |
| 856 | |
| 857 | /* ena_com_interrupt_moderation_supported - Return if interrupt moderation |
| 858 | * capability is supported by the device. |
| 859 | * |
| 860 | * @return - supported or not. |
| 861 | */ |
| 862 | bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); |
| 863 | |
| 864 | /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt |
| 865 | * moderation table back to the default parameters. |
| 866 | * @ena_dev: ENA communication layer struct |
| 867 | */ |
| 868 | void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev); |
| 869 | |
| 870 | /* ena_com_update_nonadaptive_moderation_interval_tx - Update the |
| 871 | * non-adaptive interval in Tx direction. |
| 872 | * @ena_dev: ENA communication layer struct |
| 873 | * @tx_coalesce_usecs: Interval in usec. |
| 874 | * |
| 875 | * @return - 0 on success, negative value on failure. |
| 876 | */ |
| 877 | int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, |
| 878 | u32 tx_coalesce_usecs); |
| 879 | |
| 880 | /* ena_com_update_nonadaptive_moderation_interval_rx - Update the |
| 881 | * non-adaptive interval in Rx direction. |
| 882 | * @ena_dev: ENA communication layer struct |
| 883 | * @rx_coalesce_usecs: Interval in usec. |
| 884 | * |
| 885 | * @return - 0 on success, negative value on failure. |
| 886 | */ |
| 887 | int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, |
| 888 | u32 rx_coalesce_usecs); |
| 889 | |
| 890 | /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the |
| 891 | * non-adaptive interval in Tx direction. |
| 892 | * @ena_dev: ENA communication layer struct |
| 893 | * |
| 894 | * @return - interval in usec |
| 895 | */ |
| 896 | unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); |
| 897 | |
| 898 | /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the |
| 899 | * non-adaptive interval in Rx direction. |
| 900 | * @ena_dev: ENA communication layer struct |
| 901 | * |
| 902 | * @return - interval in usec |
| 903 | */ |
| 904 | unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); |
| 905 | |
| 906 | /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt |
| 907 | * moderation table. |
| 908 | * @ena_dev: ENA communication layer struct |
| 909 | * @level: Interrupt moderation table level |
| 910 | * @entry: Entry value |
| 911 | * |
| 912 | * Update a single entry in the interrupt moderation table. |
| 913 | */ |
| 914 | void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, |
| 915 | enum ena_intr_moder_level level, |
| 916 | struct ena_intr_moder_entry *entry); |
| 917 | |
| 918 | /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry. |
| 919 | * @ena_dev: ENA communication layer struct |
| 920 | * @level: Interrupt moderation table level |
| 921 | * @entry: Entry to fill. |
| 922 | * |
| 923 | * Initialize the entry according to the adaptive interrupt moderation table. |
| 924 | */ |
| 925 | void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, |
| 926 | enum ena_intr_moder_level level, |
| 927 | struct ena_intr_moder_entry *entry); |
| 928 | |
| 929 | static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) |
| 930 | { |
| 931 | return ena_dev->adaptive_coalescing; |
| 932 | } |
| 933 | |
| 934 | static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) |
| 935 | { |
| 936 | ena_dev->adaptive_coalescing = true; |
| 937 | } |
| 938 | |
| 939 | static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) |
| 940 | { |
| 941 | ena_dev->adaptive_coalescing = false; |
| 942 | } |
| 943 | |
| 944 | /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay |
| 945 | * @ena_dev: ENA communication layer struct |
| 946 | * @pkts: Number of packets since the last update |
| 947 | * @bytes: Number of bytes received since the last update. |
| 948 | * @smoothed_interval: Returned interval |
| 949 | * @moder_tbl_idx: Current table level as input update new level as return |
| 950 | * value. |
| 951 | */ |
| 952 | static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev, |
| 953 | unsigned int pkts, |
| 954 | unsigned int bytes, |
| 955 | unsigned int *smoothed_interval, |
| 956 | unsigned int *moder_tbl_idx) |
| 957 | { |
| 958 | enum ena_intr_moder_level curr_moder_idx, new_moder_idx; |
| 959 | struct ena_intr_moder_entry *curr_moder_entry; |
| 960 | struct ena_intr_moder_entry *pred_moder_entry; |
| 961 | struct ena_intr_moder_entry *new_moder_entry; |
| 962 | struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; |
| 963 | unsigned int interval; |
| 964 | |
| 965 | /* We apply adaptive moderation on Rx path only. |
| 966 | * Tx uses static interrupt moderation. |
| 967 | */ |
| 968 | if (!pkts || !bytes) |
| 969 | /* Tx interrupt, or spurious interrupt, |
| 970 | * in both cases we just use same delay values |
| 971 | */ |
| 972 | return; |
| 973 | |
| 974 | curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx); |
| 975 | if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) { |
| 976 | pr_err("Wrong moderation index %u\n", curr_moder_idx); |
| 977 | return; |
| 978 | } |
| 979 | |
| 980 | curr_moder_entry = &intr_moder_tbl[curr_moder_idx]; |
| 981 | new_moder_idx = curr_moder_idx; |
| 982 | |
| 983 | if (curr_moder_idx == ENA_INTR_MODER_LOWEST) { |
| 984 | if ((pkts > curr_moder_entry->pkts_per_interval) || |
| 985 | (bytes > curr_moder_entry->bytes_per_interval)) |
| 986 | new_moder_idx = |
| 987 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); |
| 988 | } else { |
| 989 | pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE]; |
| 990 | |
| 991 | if ((pkts <= pred_moder_entry->pkts_per_interval) || |
| 992 | (bytes <= pred_moder_entry->bytes_per_interval)) |
| 993 | new_moder_idx = |
| 994 | (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE); |
| 995 | else if ((pkts > curr_moder_entry->pkts_per_interval) || |
| 996 | (bytes > curr_moder_entry->bytes_per_interval)) { |
| 997 | if (curr_moder_idx != ENA_INTR_MODER_HIGHEST) |
| 998 | new_moder_idx = |
| 999 | (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); |
| 1000 | } |
| 1001 | } |
| 1002 | new_moder_entry = &intr_moder_tbl[new_moder_idx]; |
| 1003 | |
| 1004 | interval = new_moder_entry->intr_moder_interval; |
| 1005 | *smoothed_interval = ( |
| 1006 | (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT + |
| 1007 | ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) / |
| 1008 | 10; |
| 1009 | |
| 1010 | *moder_tbl_idx = new_moder_idx; |
| 1011 | } |
| 1012 | |
| 1013 | /* ena_com_update_intr_reg - Prepare interrupt register |
| 1014 | * @intr_reg: interrupt register to update. |
| 1015 | * @rx_delay_interval: Rx interval in usecs |
| 1016 | * @tx_delay_interval: Tx interval in usecs |
| 1017 | * @unmask: unask enable/disable |
| 1018 | * |
| 1019 | * Prepare interrupt update register with the supplied parameters. |
| 1020 | */ |
| 1021 | static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, |
| 1022 | u32 rx_delay_interval, |
| 1023 | u32 tx_delay_interval, |
| 1024 | bool unmask) |
| 1025 | { |
| 1026 | intr_reg->intr_control = 0; |
| 1027 | intr_reg->intr_control |= rx_delay_interval & |
| 1028 | ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; |
| 1029 | |
| 1030 | intr_reg->intr_control |= |
| 1031 | (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) |
| 1032 | & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; |
| 1033 | |
| 1034 | if (unmask) |
| 1035 | intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; |
| 1036 | } |
| 1037 | |
| 1038 | #endif /* !(ENA_COM) */ |