| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 1 | #ifndef _MACH_PORTMUX_H_ |
| 2 | #define _MACH_PORTMUX_H_ |
| 3 | |
| Michael Hennerich | fac3cf4 | 2007-12-24 20:07:03 +0800 | [diff] [blame] | 4 | #define MAX_RESOURCES MAX_BLACKFIN_GPIOS |
| 5 | |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 6 | #define P_PPI0_CLK (P_DONTCARE) |
| 7 | #define P_PPI0_FS1 (P_DONTCARE) |
| 8 | #define P_PPI0_FS2 (P_DONTCARE) |
| 9 | #define P_PPI0_FS3 (P_DONTCARE) |
| 10 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) |
| 11 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) |
| 12 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) |
| 13 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) |
| 14 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) |
| 15 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) |
| 16 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) |
| 17 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) |
| 18 | #define P_PPI0_D0 (P_DONTCARE) |
| 19 | #define P_PPI0_D1 (P_DONTCARE) |
| 20 | #define P_PPI0_D2 (P_DONTCARE) |
| 21 | #define P_PPI0_D3 (P_DONTCARE) |
| 22 | #define P_PPI0_D4 (P_DONTCARE) |
| 23 | #define P_PPI0_D5 (P_DONTCARE) |
| 24 | #define P_PPI0_D6 (P_DONTCARE) |
| 25 | #define P_PPI0_D7 (P_DONTCARE) |
| 26 | #define P_PPI1_CLK (P_DONTCARE) |
| 27 | #define P_PPI1_FS1 (P_DONTCARE) |
| 28 | #define P_PPI1_FS2 (P_DONTCARE) |
| 29 | #define P_PPI1_FS3 (P_DONTCARE) |
| 30 | #define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) |
| 31 | #define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) |
| 32 | #define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) |
| 33 | #define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) |
| 34 | #define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) |
| 35 | #define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) |
| 36 | #define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) |
| 37 | #define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) |
| 38 | #define P_PPI1_D0 (P_DONTCARE) |
| 39 | #define P_PPI1_D1 (P_DONTCARE) |
| 40 | #define P_PPI1_D2 (P_DONTCARE) |
| 41 | #define P_PPI1_D3 (P_DONTCARE) |
| 42 | #define P_PPI1_D4 (P_DONTCARE) |
| 43 | #define P_PPI1_D5 (P_DONTCARE) |
| 44 | #define P_PPI1_D6 (P_DONTCARE) |
| 45 | #define P_PPI1_D7 (P_DONTCARE) |
| 46 | #define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) |
| 47 | #define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) |
| 48 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) |
| 49 | #define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) |
| 50 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) |
| 51 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) |
| 52 | #define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) |
| 53 | #define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) |
| 54 | #define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) |
| 55 | #define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) |
| 56 | #define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) |
| 57 | #define P_SPORT1_DRPRI (P_DONTCARE) |
| 58 | #define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) |
| 59 | #define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) |
| 60 | #define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) |
| 61 | #define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) |
| 62 | #define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) |
| 63 | #define P_SPORT0_DRPRI (P_DONTCARE) |
| 64 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) |
| 65 | #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) |
| 66 | #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) |
| 67 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) |
| 68 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) |
| 69 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) |
| 70 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) |
| 71 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) |
| 72 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) |
| 73 | #define P_TMR11 (P_DONTCARE) |
| 74 | #define P_TMR10 (P_DONTCARE) |
| 75 | #define P_TMR9 (P_DONTCARE) |
| 76 | #define P_TMR8 (P_DONTCARE) |
| 77 | #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) |
| 78 | #define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) |
| 79 | #define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) |
| 80 | #define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) |
| 81 | #define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) |
| 82 | #define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) |
| 83 | #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) |
| 84 | #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) |
| 85 | #define P_SPI0_MOSI (P_DONTCARE) |
| Bryan Wu | 7c100f3 | 2007-08-05 15:43:03 +0800 | [diff] [blame] | 86 | #define P_SPI0_MISO (P_DONTCARE) |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 87 | #define P_SPI0_SCK (P_DONTCARE) |
| 88 | |
| 89 | #endif /* _MACH_PORTMUX_H_ */ |