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Catalin Marinas8ad68bb2005-10-31 14:25:02 +00001/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000021#include <linux/init.h>
Russell King1be72282005-10-31 16:57:06 +000022#include <linux/platform_device.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000023#include <linux/dma-mapping.h>
24#include <linux/sysdev.h>
25#include <linux/interrupt.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
Catalin Marinas85802af2008-02-04 17:24:54 +010028#include <linux/clocksource.h>
Catalin Marinasae30cea2008-02-04 17:26:55 +010029#include <linux/clockchips.h>
Russell Kingfced80c2008-09-06 12:10:45 +010030#include <linux/io.h>
Steve Glendinningc5142e82009-01-20 13:23:30 +000031#include <linux/smsc911x.h>
Catalin Marinas6be62ba2009-02-12 15:59:21 +010032#include <linux/ata_platform.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000033
Russell Kingcf30fb42008-11-08 20:05:55 +000034#include <asm/clkdev.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000035#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010036#include <mach/hardware.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000037#include <asm/irq.h>
38#include <asm/leds.h>
Colin Tuckley68c3d932008-11-10 14:10:11 +000039#include <asm/mach-types.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000040#include <asm/hardware/arm_timer.h>
41#include <asm/hardware/icst307.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/flash.h>
45#include <asm/mach/irq.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000046#include <asm/mach/map.h>
47#include <asm/mach/mmc.h>
48
49#include <asm/hardware/gic.h>
50
51#include "core.h"
52#include "clock.h"
53
54#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
55
Catalin Marinas1bbdf632008-12-01 14:54:58 +000056/* used by entry-macro.S and platsmp.c */
Catalin Marinasc4057f52008-02-04 17:41:01 +010057void __iomem *gic_cpu_base_addr;
58
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000059/*
60 * This is the RealView sched_clock implementation. This has
61 * a resolution of 41.7ns, and a maximum value of about 179s.
62 */
63unsigned long long sched_clock(void)
64{
65 unsigned long long v;
66
67 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
68 do_div(v, 3);
69
70 return v;
71}
72
73
74#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
75
76static int realview_flash_init(void)
77{
78 u32 val;
79
80 val = __raw_readl(REALVIEW_FLASHCTRL);
81 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
82 __raw_writel(val, REALVIEW_FLASHCTRL);
83
84 return 0;
85}
86
87static void realview_flash_exit(void)
88{
89 u32 val;
90
91 val = __raw_readl(REALVIEW_FLASHCTRL);
92 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
93 __raw_writel(val, REALVIEW_FLASHCTRL);
94}
95
96static void realview_flash_set_vpp(int on)
97{
98 u32 val;
99
100 val = __raw_readl(REALVIEW_FLASHCTRL);
101 if (on)
102 val |= REALVIEW_FLASHPROG_FLVPPEN;
103 else
104 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
105 __raw_writel(val, REALVIEW_FLASHCTRL);
106}
107
108static struct flash_platform_data realview_flash_data = {
109 .map_name = "cfi_probe",
110 .width = 4,
111 .init = realview_flash_init,
112 .exit = realview_flash_exit,
113 .set_vpp = realview_flash_set_vpp,
114};
115
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000116struct platform_device realview_flash_device = {
117 .name = "armflash",
118 .id = 0,
119 .dev = {
120 .platform_data = &realview_flash_data,
121 },
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000122};
123
Catalin Marinasa44ddfd2008-04-18 22:43:10 +0100124int realview_flash_register(struct resource *res, u32 num)
125{
126 realview_flash_device.resource = res;
127 realview_flash_device.num_resources = num;
128 return platform_device_register(&realview_flash_device);
129}
130
Steve Glendinningc5142e82009-01-20 13:23:30 +0000131static struct smsc911x_platform_config smsc911x_config = {
132 .flags = SMSC911X_USE_32BIT,
133 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
134 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
135 .phy_interface = PHY_INTERFACE_MODE_MII,
Catalin Marinas0a5b2f62008-12-01 14:54:59 +0000136};
137
Catalin Marinas0a381332008-12-01 14:54:58 +0000138static struct platform_device realview_eth_device = {
Steve Glendinningc5142e82009-01-20 13:23:30 +0000139 .name = "smsc911x",
Catalin Marinas0a381332008-12-01 14:54:58 +0000140 .id = 0,
141 .num_resources = 2,
142};
143
144int realview_eth_register(const char *name, struct resource *res)
145{
146 if (name)
147 realview_eth_device.name = name;
148 realview_eth_device.resource = res;
Steve Glendinningc5142e82009-01-20 13:23:30 +0000149 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
150 realview_eth_device.dev.platform_data = &smsc911x_config;
Catalin Marinas0a381332008-12-01 14:54:58 +0000151
152 return platform_device_register(&realview_eth_device);
153}
154
Catalin Marinas7db21712009-02-12 16:00:21 +0100155struct platform_device realview_usb_device = {
156 .name = "isp1760",
157 .num_resources = 2,
158};
159
160int realview_usb_register(struct resource *res)
161{
162 realview_usb_device.resource = res;
163 return platform_device_register(&realview_usb_device);
164}
165
Catalin Marinas6be62ba2009-02-12 15:59:21 +0100166static struct pata_platform_info pata_platform_data = {
167 .ioport_shift = 1,
168};
169
170static struct resource pata_resources[] = {
171 [0] = {
172 .start = REALVIEW_CF_BASE,
173 .end = REALVIEW_CF_BASE + 0xff,
174 .flags = IORESOURCE_MEM,
175 },
176 [1] = {
177 .start = REALVIEW_CF_BASE + 0x100,
178 .end = REALVIEW_CF_BASE + SZ_4K - 1,
179 .flags = IORESOURCE_MEM,
180 },
181};
182
183struct platform_device realview_cf_device = {
184 .name = "pata_platform",
185 .id = -1,
186 .num_resources = ARRAY_SIZE(pata_resources),
187 .resource = pata_resources,
188 .dev = {
189 .platform_data = &pata_platform_data,
190 },
191};
192
Russell King6b65cd72006-12-10 21:21:32 +0100193static struct resource realview_i2c_resource = {
194 .start = REALVIEW_I2C_BASE,
195 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
196 .flags = IORESOURCE_MEM,
197};
198
199struct platform_device realview_i2c_device = {
200 .name = "versatile-i2c",
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100201 .id = 0,
Russell King6b65cd72006-12-10 21:21:32 +0100202 .num_resources = 1,
203 .resource = &realview_i2c_resource,
204};
205
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100206static struct i2c_board_info realview_i2c_board_info[] = {
207 {
208 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
209 .type = "ds1338",
210 },
211};
212
213static int __init realview_i2c_init(void)
214{
215 return i2c_register_board_info(0, realview_i2c_board_info,
216 ARRAY_SIZE(realview_i2c_board_info));
217}
218arch_initcall(realview_i2c_init);
219
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000220#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
221
222static unsigned int realview_mmc_status(struct device *dev)
223{
224 struct amba_device *adev = container_of(dev, struct amba_device, dev);
225 u32 mask;
226
227 if (adev->res.start == REALVIEW_MMCI0_BASE)
228 mask = 1;
229 else
230 mask = 2;
231
232 return readl(REALVIEW_SYSMCI) & mask;
233}
234
235struct mmc_platform_data realview_mmc0_plat_data = {
236 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
237 .status = realview_mmc_status,
238};
239
240struct mmc_platform_data realview_mmc1_plat_data = {
241 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
242 .status = realview_mmc_status,
243};
244
245/*
246 * Clock handling
247 */
248static const struct icst307_params realview_oscvco_params = {
249 .ref = 24000,
250 .vco_max = 200000,
251 .vd_min = 4 + 8,
252 .vd_max = 511 + 8,
253 .rd_min = 1 + 2,
254 .rd_max = 127 + 2,
255};
256
257static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
258{
259 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
Colin Tuckley68c3d932008-11-10 14:10:11 +0000260 void __iomem *sys_osc;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000261 u32 val;
262
Colin Tuckley68c3d932008-11-10 14:10:11 +0000263 if (machine_is_realview_pb1176())
264 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
265 else
266 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
267
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000268 val = readl(sys_osc) & ~0x7ffff;
269 val |= vco.v | (vco.r << 9) | (vco.s << 16);
270
271 writel(0xa05f, sys_lock);
272 writel(val, sys_osc);
273 writel(0, sys_lock);
274}
275
Russell Kingcf30fb42008-11-08 20:05:55 +0000276static struct clk oscvco_clk = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000277 .params = &realview_oscvco_params,
278 .setvco = realview_oscvco_set,
279};
280
281/*
Russell Kingcf30fb42008-11-08 20:05:55 +0000282 * These are fixed clocks.
283 */
284static struct clk ref24_clk = {
285 .rate = 24000000,
286};
287
288static struct clk_lookup lookups[] = {
289 { /* UART0 */
290 .dev_id = "dev:f1",
291 .clk = &ref24_clk,
292 }, { /* UART1 */
293 .dev_id = "dev:f2",
294 .clk = &ref24_clk,
295 }, { /* UART2 */
296 .dev_id = "dev:f3",
297 .clk = &ref24_clk,
298 }, { /* UART3 */
299 .dev_id = "fpga:09",
300 .clk = &ref24_clk,
301 }, { /* KMI0 */
302 .dev_id = "fpga:06",
303 .clk = &ref24_clk,
304 }, { /* KMI1 */
305 .dev_id = "fpga:07",
306 .clk = &ref24_clk,
307 }, { /* MMC0 */
308 .dev_id = "fpga:05",
309 .clk = &ref24_clk,
310 }, { /* EB:CLCD */
311 .dev_id = "dev:20",
312 .clk = &oscvco_clk,
313 }, { /* PB:CLCD */
314 .dev_id = "issp:20",
315 .clk = &oscvco_clk,
316 }
317};
318
319static int __init clk_init(void)
320{
321 int i;
322
323 for (i = 0; i < ARRAY_SIZE(lookups); i++)
324 clkdev_add(&lookups[i]);
325 return 0;
326}
327arch_initcall(clk_init);
328
329/*
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000330 * CLCD support.
331 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000332#define SYS_CLCD_NLCDIOON (1 << 2)
333#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
334#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
335#define SYS_CLCD_ID_MASK (0x1f << 8)
336#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
337#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
338#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
339#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
340#define SYS_CLCD_ID_VGA (0x1f << 8)
341
342static struct clcd_panel vga = {
343 .mode = {
344 .name = "VGA",
345 .refresh = 60,
346 .xres = 640,
347 .yres = 480,
348 .pixclock = 39721,
349 .left_margin = 40,
350 .right_margin = 24,
351 .upper_margin = 32,
352 .lower_margin = 11,
353 .hsync_len = 96,
354 .vsync_len = 2,
355 .sync = 0,
356 .vmode = FB_VMODE_NONINTERLACED,
357 },
358 .width = -1,
359 .height = -1,
360 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000361 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000362 .bpp = 16,
363};
364
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000365static struct clcd_panel xvga = {
366 .mode = {
367 .name = "XVGA",
368 .refresh = 60,
369 .xres = 1024,
370 .yres = 768,
371 .pixclock = 15748,
372 .left_margin = 152,
373 .right_margin = 48,
374 .upper_margin = 23,
375 .lower_margin = 3,
376 .hsync_len = 104,
377 .vsync_len = 4,
378 .sync = 0,
379 .vmode = FB_VMODE_NONINTERLACED,
380 },
381 .width = -1,
382 .height = -1,
383 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000384 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000385 .bpp = 16,
386};
387
388static struct clcd_panel sanyo_3_8_in = {
389 .mode = {
390 .name = "Sanyo QVGA",
391 .refresh = 116,
392 .xres = 320,
393 .yres = 240,
394 .pixclock = 100000,
395 .left_margin = 6,
396 .right_margin = 6,
397 .upper_margin = 5,
398 .lower_margin = 5,
399 .hsync_len = 6,
400 .vsync_len = 6,
401 .sync = 0,
402 .vmode = FB_VMODE_NONINTERLACED,
403 },
404 .width = -1,
405 .height = -1,
406 .tim2 = TIM2_BCD,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000407 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000408 .bpp = 16,
409};
410
411static struct clcd_panel sanyo_2_5_in = {
412 .mode = {
413 .name = "Sanyo QVGA Portrait",
414 .refresh = 116,
415 .xres = 240,
416 .yres = 320,
417 .pixclock = 100000,
418 .left_margin = 20,
419 .right_margin = 10,
420 .upper_margin = 2,
421 .lower_margin = 2,
422 .hsync_len = 10,
423 .vsync_len = 2,
424 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
425 .vmode = FB_VMODE_NONINTERLACED,
426 },
427 .width = -1,
428 .height = -1,
429 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000430 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000431 .bpp = 16,
432};
433
434static struct clcd_panel epson_2_2_in = {
435 .mode = {
436 .name = "Epson QCIF",
437 .refresh = 390,
438 .xres = 176,
439 .yres = 220,
440 .pixclock = 62500,
441 .left_margin = 3,
442 .right_margin = 2,
443 .upper_margin = 1,
444 .lower_margin = 0,
445 .hsync_len = 3,
446 .vsync_len = 2,
447 .sync = 0,
448 .vmode = FB_VMODE_NONINTERLACED,
449 },
450 .width = -1,
451 .height = -1,
452 .tim2 = TIM2_BCD | TIM2_IPC,
Catalin Marinas4eccca22008-11-10 14:10:13 +0000453 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000454 .bpp = 16,
455};
456
457/*
458 * Detect which LCD panel is connected, and return the appropriate
459 * clcd_panel structure. Note: we do not have any information on
460 * the required timings for the 8.4in panel, so we presently assume
461 * VGA timings.
462 */
463static struct clcd_panel *realview_clcd_panel(void)
464{
465 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000466 struct clcd_panel *vga_panel;
467 struct clcd_panel *panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000468 u32 val;
469
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000470 if (machine_is_realview_eb())
471 vga_panel = &vga;
472 else
473 vga_panel = &xvga;
474
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000475 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
476 if (val == SYS_CLCD_ID_SANYO_3_8)
477 panel = &sanyo_3_8_in;
478 else if (val == SYS_CLCD_ID_SANYO_2_5)
479 panel = &sanyo_2_5_in;
480 else if (val == SYS_CLCD_ID_EPSON_2_2)
481 panel = &epson_2_2_in;
482 else if (val == SYS_CLCD_ID_VGA)
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000483 panel = vga_panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000484 else {
485 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
486 val);
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000487 panel = vga_panel;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000488 }
489
490 return panel;
491}
492
493/*
494 * Disable all display connectors on the interface module.
495 */
496static void realview_clcd_disable(struct clcd_fb *fb)
497{
498 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
499 u32 val;
500
501 val = readl(sys_clcd);
502 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
503 writel(val, sys_clcd);
504}
505
506/*
507 * Enable the relevant connector on the interface module.
508 */
509static void realview_clcd_enable(struct clcd_fb *fb)
510{
511 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
512 u32 val;
513
Catalin Marinas9e7714d2006-03-16 14:10:20 +0000514 /*
515 * Enable the PSUs
516 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000517 val = readl(sys_clcd);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000518 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
519 writel(val, sys_clcd);
520}
521
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000522static int realview_clcd_setup(struct clcd_fb *fb)
523{
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000524 unsigned long framesize;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000525 dma_addr_t dma;
526
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000527 if (machine_is_realview_eb())
528 /* VGA, 16bpp */
529 framesize = 640 * 480 * 2;
530 else
531 /* XVGA, 16bpp */
532 framesize = 1024 * 768 * 2;
533
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000534 fb->panel = realview_clcd_panel();
535
536 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
537 &dma, GFP_KERNEL);
538 if (!fb->fb.screen_base) {
539 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
540 return -ENOMEM;
541 }
542
543 fb->fb.fix.smem_start = dma;
544 fb->fb.fix.smem_len = framesize;
545
546 return 0;
547}
548
549static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
550{
551 return dma_mmap_writecombine(&fb->dev->dev, vma,
552 fb->fb.screen_base,
553 fb->fb.fix.smem_start,
554 fb->fb.fix.smem_len);
555}
556
557static void realview_clcd_remove(struct clcd_fb *fb)
558{
559 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
560 fb->fb.screen_base, fb->fb.fix.smem_start);
561}
562
563struct clcd_board clcd_plat_data = {
564 .name = "RealView",
565 .check = clcdfb_check,
566 .decode = clcdfb_decode,
567 .disable = realview_clcd_disable,
568 .enable = realview_clcd_enable,
569 .setup = realview_clcd_setup,
570 .mmap = realview_clcd_mmap,
571 .remove = realview_clcd_remove,
572};
573
574#ifdef CONFIG_LEDS
575#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
576
577void realview_leds_event(led_event_t ledevt)
578{
579 unsigned long flags;
580 u32 val;
581
582 local_irq_save(flags);
583 val = readl(VA_LEDS_BASE);
584
585 switch (ledevt) {
586 case led_idle_start:
587 val = val & ~REALVIEW_SYS_LED0;
588 break;
589
590 case led_idle_end:
591 val = val | REALVIEW_SYS_LED0;
592 break;
593
594 case led_timer:
595 val = val ^ REALVIEW_SYS_LED1;
596 break;
597
598 case led_halted:
599 val = 0;
600 break;
601
602 default:
603 break;
604 }
605
606 writel(val, VA_LEDS_BASE);
607 local_irq_restore(flags);
608}
609#endif /* CONFIG_LEDS */
610
611/*
612 * Where is the timer (VA)?
613 */
Catalin Marinas80192732008-04-18 22:43:11 +0100614void __iomem *timer0_va_base;
615void __iomem *timer1_va_base;
616void __iomem *timer2_va_base;
617void __iomem *timer3_va_base;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000618
619/*
620 * How long is the timer interval?
621 */
622#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
623#if TIMER_INTERVAL >= 0x100000
624#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
625#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
626#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
627#elif TIMER_INTERVAL >= 0x10000
628#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
629#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
630#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
631#else
632#define TIMER_RELOAD (TIMER_INTERVAL)
633#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
634#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
635#endif
636
Catalin Marinasae30cea2008-02-04 17:26:55 +0100637static void timer_set_mode(enum clock_event_mode mode,
638 struct clock_event_device *clk)
639{
640 unsigned long ctrl;
641
642 switch(mode) {
643 case CLOCK_EVT_MODE_PERIODIC:
Catalin Marinas80192732008-04-18 22:43:11 +0100644 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
Catalin Marinasae30cea2008-02-04 17:26:55 +0100645
646 ctrl = TIMER_CTRL_PERIODIC;
647 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
648 break;
649 case CLOCK_EVT_MODE_ONESHOT:
650 /* period set, and timer enabled in 'next_event' hook */
651 ctrl = TIMER_CTRL_ONESHOT;
652 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
653 break;
654 case CLOCK_EVT_MODE_UNUSED:
655 case CLOCK_EVT_MODE_SHUTDOWN:
656 default:
657 ctrl = 0;
658 }
659
Catalin Marinas80192732008-04-18 22:43:11 +0100660 writel(ctrl, timer0_va_base + TIMER_CTRL);
Catalin Marinasae30cea2008-02-04 17:26:55 +0100661}
662
663static int timer_set_next_event(unsigned long evt,
664 struct clock_event_device *unused)
665{
Catalin Marinas80192732008-04-18 22:43:11 +0100666 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
Catalin Marinasae30cea2008-02-04 17:26:55 +0100667
Catalin Marinas80192732008-04-18 22:43:11 +0100668 writel(evt, timer0_va_base + TIMER_LOAD);
669 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
Catalin Marinasae30cea2008-02-04 17:26:55 +0100670
671 return 0;
672}
673
674static struct clock_event_device timer0_clockevent = {
675 .name = "timer0",
676 .shift = 32,
677 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
678 .set_mode = timer_set_mode,
679 .set_next_event = timer_set_next_event,
680 .rating = 300,
Rusty Russell320ab2b2008-12-13 21:20:26 +1030681 .cpumask = cpu_all_mask,
Catalin Marinasae30cea2008-02-04 17:26:55 +0100682};
683
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100684static void __init realview_clockevents_init(unsigned int timer_irq)
Catalin Marinasae30cea2008-02-04 17:26:55 +0100685{
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100686 timer0_clockevent.irq = timer_irq;
Catalin Marinasae30cea2008-02-04 17:26:55 +0100687 timer0_clockevent.mult =
688 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
689 timer0_clockevent.max_delta_ns =
690 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
691 timer0_clockevent.min_delta_ns =
692 clockevent_delta2ns(0xf, &timer0_clockevent);
693
694 clockevents_register_device(&timer0_clockevent);
695}
696
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000697/*
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000698 * IRQ handler for the timer
699 */
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700700static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000701{
Catalin Marinasae30cea2008-02-04 17:26:55 +0100702 struct clock_event_device *evt = &timer0_clockevent;
703
704 /* clear the interrupt */
Catalin Marinas80192732008-04-18 22:43:11 +0100705 writel(1, timer0_va_base + TIMER_INTCLR);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000706
Catalin Marinasae30cea2008-02-04 17:26:55 +0100707 evt->event_handler(evt);
Russell Kingdbebb4c2005-11-08 10:40:10 +0000708
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000709 return IRQ_HANDLED;
710}
711
712static struct irqaction realview_timer_irq = {
713 .name = "RealView Timer Tick",
Bernhard Walleb30faba2007-05-08 00:35:39 -0700714 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000715 .handler = realview_timer_interrupt,
716};
717
Magnus Damm8e196082009-04-21 12:24:00 -0700718static cycle_t realview_get_cycles(struct clocksource *cs)
Catalin Marinas85802af2008-02-04 17:24:54 +0100719{
Catalin Marinas80192732008-04-18 22:43:11 +0100720 return ~readl(timer3_va_base + TIMER_VALUE);
Catalin Marinas85802af2008-02-04 17:24:54 +0100721}
722
723static struct clocksource clocksource_realview = {
724 .name = "timer3",
725 .rating = 200,
726 .read = realview_get_cycles,
727 .mask = CLOCKSOURCE_MASK(32),
728 .shift = 20,
729 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
730};
731
732static void __init realview_clocksource_init(void)
733{
734 /* setup timer 0 as free-running clocksource */
Catalin Marinas80192732008-04-18 22:43:11 +0100735 writel(0, timer3_va_base + TIMER_CTRL);
736 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
737 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
Catalin Marinas85802af2008-02-04 17:24:54 +0100738 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
Catalin Marinas80192732008-04-18 22:43:11 +0100739 timer3_va_base + TIMER_CTRL);
Catalin Marinas85802af2008-02-04 17:24:54 +0100740
741 clocksource_realview.mult =
742 clocksource_khz2mult(1000, clocksource_realview.shift);
743 clocksource_register(&clocksource_realview);
744}
745
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000746/*
Catalin Marinasa8655e82008-02-04 17:30:57 +0100747 * Set up the clock source and clock events devices
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000748 */
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100749void __init realview_timer_init(unsigned int timer_irq)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000750{
751 u32 val;
752
Catalin Marinasa8655e82008-02-04 17:30:57 +0100753#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
754 /*
755 * The dummy clock device has to be registered before the main device
756 * so that the latter will broadcast the clock events
757 */
Catalin Marinasebac6542008-12-01 14:54:57 +0000758 local_timer_setup();
Catalin Marinasa8655e82008-02-04 17:30:57 +0100759#endif
760
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000761 /*
762 * set clock frequency:
763 * REALVIEW_REFCLK is 32KHz
764 * REALVIEW_TIMCLK is 1MHz
765 */
766 val = readl(__io_address(REALVIEW_SCTL_BASE));
767 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
768 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
769 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
770 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
771 __io_address(REALVIEW_SCTL_BASE));
772
773 /*
774 * Initialise to a known state (all timers off)
775 */
Catalin Marinas80192732008-04-18 22:43:11 +0100776 writel(0, timer0_va_base + TIMER_CTRL);
777 writel(0, timer1_va_base + TIMER_CTRL);
778 writel(0, timer2_va_base + TIMER_CTRL);
779 writel(0, timer3_va_base + TIMER_CTRL);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000780
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000781 /*
782 * Make irqs happen for the system timer
783 */
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100784 setup_irq(timer_irq, &realview_timer_irq);
Catalin Marinas85802af2008-02-04 17:24:54 +0100785
786 realview_clocksource_init();
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100787 realview_clockevents_init(timer_irq);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000788}