Ben Skeggs | 573a2a3 | 2010-08-25 15:26:04 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | #include "nouveau_drv.h" |
| 27 | #include "nouveau_mm.h" |
| 28 | |
| 29 | static int types[0x80] = { |
| 30 | 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 31 | 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0, |
| 32 | 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0, |
| 33 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 34 | 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0, |
| 35 | 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 36 | 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2, |
| 37 | 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0 |
| 38 | }; |
| 39 | |
| 40 | void |
| 41 | nv50_vram_del(struct drm_device *dev, struct nouveau_vram **pvram) |
| 42 | { |
| 43 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 44 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; |
| 45 | struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM]; |
| 46 | struct nouveau_mm *mm = man->priv; |
| 47 | struct nouveau_mm_node *this; |
| 48 | struct nouveau_vram *vram; |
| 49 | |
| 50 | vram = *pvram; |
| 51 | *pvram = NULL; |
| 52 | if (unlikely(vram == NULL)) |
| 53 | return; |
| 54 | |
| 55 | mutex_lock(&mm->mutex); |
| 56 | while (!list_empty(&vram->regions)) { |
| 57 | this = list_first_entry(&vram->regions, struct nouveau_mm_node, rl_entry); |
| 58 | |
| 59 | list_del(&this->rl_entry); |
| 60 | nouveau_mm_put(mm, this); |
| 61 | } |
| 62 | mutex_unlock(&mm->mutex); |
| 63 | |
| 64 | kfree(vram); |
| 65 | } |
| 66 | |
| 67 | int |
| 68 | nv50_vram_new(struct drm_device *dev, u64 size, u32 align, u32 size_nc, |
| 69 | u32 type, struct nouveau_vram **pvram) |
| 70 | { |
| 71 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 72 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; |
| 73 | struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM]; |
| 74 | struct nouveau_mm *mm = man->priv; |
| 75 | struct nouveau_mm_node *r; |
| 76 | struct nouveau_vram *vram; |
| 77 | int ret; |
| 78 | |
| 79 | if (!types[type]) |
| 80 | return -EINVAL; |
| 81 | size >>= 12; |
| 82 | align >>= 12; |
| 83 | size_nc >>= 12; |
| 84 | |
| 85 | vram = kzalloc(sizeof(*vram), GFP_KERNEL); |
| 86 | if (!vram) |
| 87 | return -ENOMEM; |
| 88 | |
| 89 | INIT_LIST_HEAD(&vram->regions); |
| 90 | vram->dev = dev_priv->dev; |
| 91 | vram->memtype = type; |
| 92 | vram->size = size; |
| 93 | |
| 94 | mutex_lock(&mm->mutex); |
| 95 | do { |
| 96 | ret = nouveau_mm_get(mm, types[type], size, size_nc, align, &r); |
| 97 | if (ret) { |
| 98 | mutex_unlock(&mm->mutex); |
| 99 | nv50_vram_del(dev, &vram); |
| 100 | return ret; |
| 101 | } |
| 102 | |
| 103 | list_add_tail(&r->rl_entry, &vram->regions); |
| 104 | size -= r->length; |
| 105 | } while (size); |
| 106 | mutex_unlock(&mm->mutex); |
| 107 | |
| 108 | r = list_first_entry(&vram->regions, struct nouveau_mm_node, rl_entry); |
| 109 | vram->offset = (u64)r->offset << 12; |
| 110 | *pvram = vram; |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static u32 |
| 115 | nv50_vram_rblock(struct drm_device *dev) |
| 116 | { |
| 117 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 118 | int i, parts, colbits, rowbitsa, rowbitsb, banks; |
| 119 | u64 rowsize, predicted; |
| 120 | u32 r0, r4, rt, ru, rblock_size; |
| 121 | |
| 122 | r0 = nv_rd32(dev, 0x100200); |
| 123 | r4 = nv_rd32(dev, 0x100204); |
| 124 | rt = nv_rd32(dev, 0x100250); |
| 125 | ru = nv_rd32(dev, 0x001540); |
| 126 | NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru); |
| 127 | |
| 128 | for (i = 0, parts = 0; i < 8; i++) { |
| 129 | if (ru & (0x00010000 << i)) |
| 130 | parts++; |
| 131 | } |
| 132 | |
| 133 | colbits = (r4 & 0x0000f000) >> 12; |
| 134 | rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; |
| 135 | rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; |
| 136 | banks = ((r4 & 0x01000000) ? 8 : 4); |
| 137 | |
| 138 | rowsize = parts * banks * (1 << colbits) * 8; |
| 139 | predicted = rowsize << rowbitsa; |
| 140 | if (r0 & 0x00000004) |
| 141 | predicted += rowsize << rowbitsb; |
| 142 | |
| 143 | if (predicted != dev_priv->vram_size) { |
| 144 | NV_WARN(dev, "memory controller reports %dMiB VRAM\n", |
| 145 | (u32)(dev_priv->vram_size >> 20)); |
| 146 | NV_WARN(dev, "we calculated %dMiB VRAM\n", |
| 147 | (u32)(predicted >> 20)); |
| 148 | } |
| 149 | |
| 150 | rblock_size = rowsize; |
| 151 | if (rt & 1) |
| 152 | rblock_size *= 3; |
| 153 | |
| 154 | NV_DEBUG(dev, "rblock %d bytes\n", rblock_size); |
| 155 | return rblock_size; |
| 156 | } |
| 157 | |
| 158 | int |
| 159 | nv50_vram_init(struct drm_device *dev) |
| 160 | { |
| 161 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 162 | |
| 163 | dev_priv->vram_size = nv_rd32(dev, 0x10020c); |
| 164 | dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; |
| 165 | dev_priv->vram_size &= 0xffffffff00ULL; |
| 166 | |
| 167 | switch (dev_priv->chipset) { |
| 168 | case 0xaa: |
| 169 | case 0xac: |
| 170 | case 0xaf: |
| 171 | dev_priv->vram_sys_base = (u64)nv_rd32(dev, 0x100e10) << 12; |
| 172 | dev_priv->vram_rblock_size = 4096; |
| 173 | break; |
| 174 | default: |
| 175 | dev_priv->vram_rblock_size = nv50_vram_rblock(dev); |
| 176 | break; |
| 177 | } |
| 178 | |
| 179 | return 0; |
| 180 | } |