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gerrit-public.fairphone.software / kernel / msm-4.9 / 6110fc36d55f082309a04b31fa7a0eea43e31b57 / . / drivers / clk / msm / clock-gcc-8952.c
blob: 71f0ea6fb746a2c25ddf4c57319221ae26d8079d [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]205 F_APCS_PLL(1171200000, 61, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]206 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]207 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
208 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]209};
210
211static struct pll_clk a53ss_c0_pll = {
212 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
213 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
214 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
215 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
216 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
217 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
218 .freq_tbl = apcs_c0_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]219 .config_ctl_reg = (void __iomem *)APCS_C0_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]220 .masks = {
221 .vco_mask = BM(29, 28),
222 .pre_div_mask = BIT(12),
223 .post_div_mask = BM(9, 8),
224 .mn_en_mask = BIT(24),
225 .main_output_mask = BIT(0),
226 },
227 .base = &virt_bases[APCS_C0_PLL_BASE],
228 .spm_ctrl = {
229 .offset = 0x50,
230 .event_bit = 0x4,
231 },
232 .c = {
233 .parent = &xo_a_clk_src.c,
234 .dbg_name = "a53ss_c0_pll",
235 .ops = &clk_ops_sr2_pll,
236 .vdd_class = &vdd_sr2_pll,
237 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
238 [VDD_SR2_PLL_SVS] = 1000000000,
239 [VDD_SR2_PLL_NOM] = 1900000000,
240 },
241 .num_fmax = VDD_SR2_PLL_NUM,
242 CLK_INIT(a53ss_c0_pll.c),
243 },
244};
245
246static struct pll_freq_tbl apcs_c1_pll_freq[] = {
247 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
263 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]264 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]265 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
269 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
270 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
271 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
272 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
273 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]274 F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
275 F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),
276 F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatladb8f4672018-11-02 10:48:42 +0530[diff] [blame]277 F_APCS_PLL(2016000000, 105, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]278};
279
280static struct pll_clk a53ss_c1_pll = {
281 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
282 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
283 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
284 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
285 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
286 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
287 .freq_tbl = apcs_c1_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]288 .config_ctl_reg = (void __iomem *)APCS_C1_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]289 .masks = {
290 .vco_mask = BM(29, 28),
291 .pre_div_mask = BIT(12),
292 .post_div_mask = BM(9, 8),
293 .mn_en_mask = BIT(24),
294 .main_output_mask = BIT(0),
295 },
296 .base = &virt_bases[APCS_C1_PLL_BASE],
297 .spm_ctrl = {
298 .offset = 0x50,
299 .event_bit = 0x4,
300 },
301 .c = {
302 .parent = &xo_a_clk_src.c,
303 .dbg_name = "a53ss_c1_pll",
304 .ops = &clk_ops_sr2_pll,
305 .vdd_class = &vdd_hf_pll,
306 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
307 [VDD_HF_PLL_SVS] = 1000000000,
Odelu Kukatladb8f4672018-11-02 10:48:42 +0530[diff] [blame]308 [VDD_HF_PLL_NOM] = 2020000000,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]309 },
310 .num_fmax = VDD_HF_PLL_NUM,
311 CLK_INIT(a53ss_c1_pll.c),
312 },
313};
314
315static struct pll_vote_clk gpll0_sleep_clk_src = {
316 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
317 .en_mask = BIT(23),
318 .status_reg = (void __iomem *)GPLL0_MODE,
319 .status_mask = BIT(30),
320 .base = &virt_bases[GCC_BASE],
321 .c = {
322 .parent = &xo_clk_src.c,
323 .rate = 800000000,
324 .dbg_name = "gpll0_sleep_clk_src",
325 .ops = &clk_ops_pll_sleep_vote,
326 CLK_INIT(gpll0_sleep_clk_src.c),
327 },
328};
329
330static unsigned int soft_vote_gpll0;
331
332/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
333 * gets set from PLL voting FSM.It indicates when
334 * FSM has enabled the PLL and PLL should be locked.
335 */
336static struct pll_vote_clk gpll0_clk_src_8952 = {
337 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
338 .en_mask = BIT(0),
339 .status_reg = (void __iomem *)GPLL0_STATUS,
340 .status_mask = BIT(17),
341 .soft_vote = &soft_vote_gpll0,
342 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
343 .base = &virt_bases[GCC_BASE],
344 .c = {
345 .parent = &xo_clk_src.c,
346 .rate = 800000000,
347 .dbg_name = "gpll0_clk_src_8952",
348 .ops = &clk_ops_pll_acpu_vote,
349 CLK_INIT(gpll0_clk_src_8952.c),
350 },
351};
352
353static struct pll_vote_clk gpll0_clk_src_8937 = {
354 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
355 .en_mask = BIT(0),
356 .status_reg = (void __iomem *)GPLL0_MODE,
357 .status_mask = BIT(30),
358 .soft_vote = &soft_vote_gpll0,
359 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
360 .base = &virt_bases[GCC_BASE],
361 .c = {
362 .parent = &gpll0_sleep_clk_src.c,
363 .rate = 800000000,
364 .dbg_name = "gpll0_clk_src_8937",
365 .ops = &clk_ops_pll_acpu_vote,
366 CLK_INIT(gpll0_clk_src_8937.c),
367 },
368};
369
370DEFINE_EXT_CLK(gpll0_clk_src, NULL);
371DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
372DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
373DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
374DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
375DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
376DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
377DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
378
379/* Don't vote for xo if using this clock to allow xo shutdown */
380static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
381 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
382 .en_mask = BIT(0),
383 .status_reg = (void __iomem *)GPLL0_STATUS,
384 .status_mask = BIT(17),
385 .soft_vote = &soft_vote_gpll0,
386 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
387 .base = &virt_bases[GCC_BASE],
388 .c = {
389 .parent = &xo_a_clk_src.c,
390 .rate = 800000000,
391 .dbg_name = "gpll0_ao_clk_src_8952",
392 .ops = &clk_ops_pll_acpu_vote,
393 CLK_INIT(gpll0_ao_clk_src_8952.c),
394 },
395};
396
397static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
398 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
399 .en_mask = BIT(0),
400 .status_reg = (void __iomem *)GPLL0_MODE,
401 .status_mask = BIT(30),
402 .soft_vote = &soft_vote_gpll0,
403 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
404 .base = &virt_bases[GCC_BASE],
405 .c = {
406 .parent = &xo_a_clk_src.c,
407 .rate = 800000000,
408 .dbg_name = "gpll0_ao_clk_src_8937",
409 .ops = &clk_ops_pll_acpu_vote,
410 CLK_INIT(gpll0_ao_clk_src_8937.c),
411 },
412};
413
414static struct pll_vote_clk gpll6_clk_src = {
415 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
416 .en_mask = BIT(7),
417 .status_reg = (void __iomem *)GPLL6_STATUS,
418 .status_mask = BIT(17),
419 .base = &virt_bases[GCC_BASE],
420 .c = {
421 .parent = &xo_clk_src.c,
422 .rate = 1080000000,
423 .dbg_name = "gpll6_clk_src",
424 .ops = &clk_ops_pll_vote,
425 CLK_INIT(gpll6_clk_src.c),
426 },
427};
428
429DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
430DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
431
432static struct alpha_pll_masks pll_masks_p = {
433 .lock_mask = BIT(31),
434 .active_mask = BIT(30),
435 .vco_mask = BM(21, 20) >> 20,
436 .vco_shift = 20,
437 .alpha_en_mask = BIT(24),
438 .output_mask = 0xf,
439 .update_mask = BIT(22),
440 .post_div_mask = BM(11, 8),
441 .test_ctl_lo_mask = BM(31, 0),
442 .test_ctl_hi_mask = BM(31, 0),
443};
444
445/* Slewing plls won't allow to change vco_sel.
446 * Hence will have only one vco table entry
447 */
448static struct alpha_pll_vco_tbl p_vco[] = {
449 VCO(0, 700000000, 1400000000),
450};
451
452/* Slewing plls won't allow to change vco_sel.
453 * Hence will have only one vco table entry
454 */
455static struct alpha_pll_vco_tbl p_vco_8937[] = {
456 VCO(1, 525000000, 1066000000),
457};
458
459static struct alpha_pll_clk gpll3_clk_src = {
460 .masks = &pll_masks_p,
461 .base = &virt_bases[GCC_BASE],
462 .offset = GPLL3_MODE,
463 .vco_tbl = p_vco,
464 .num_vco = ARRAY_SIZE(p_vco),
465 .enable_config = 1,
466 /*
467 * gpll3 is dedicated to oxili and has a fuse implementation for
468 * post divider to limit frequency. HW with fuse blown has a divider
469 * value set to 2. So lets stick to divide by 2 in software to avoid
470 * conflicts.
471 */
472 .post_div_config = 1 << 8,
473 .slew = true,
474 .config_ctl_val = 0x4001055b,
475 .test_ctl_hi_val = 0x40000600,
476 .c = {
477 .rate = 1050000000,
478 .parent = &xo_clk_src.c,
479 .dbg_name = "gpll3_clk_src",
480 .ops = &clk_ops_dyna_alpha_pll,
481 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
482 CLK_INIT(gpll3_clk_src.c),
483 },
484};
485
486static struct pll_vote_clk gpll4_clk_src = {
487 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
488 .en_mask = BIT(5),
489 .status_reg = (void __iomem *)GPLL4_MODE,
490 .status_mask = BIT(30),
491 .base = &virt_bases[GCC_BASE],
492 .c = {
493 .rate = 1152000000,
494 .parent = &xo_clk_src.c,
495 .dbg_name = "gpll4_clk_src",
496 .ops = &clk_ops_pll_vote,
497 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
498 CLK_INIT(gpll4_clk_src.c),
499 },
500};
501DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
502
503static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
504 F( 40000000, gpll0, 10, 1, 2),
505 F( 61540000, gpll0, 13, 0, 0),
506 F( 80000000, gpll0, 10, 0, 0),
507 F_END
508};
509
510static struct rcg_clk camss_top_ahb_clk_src = {
511 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
512 .set_rate = set_rate_mnd,
513 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
514 .current_freq = &rcg_dummy_freq,
515 .base = &virt_bases[GCC_BASE],
516 .c = {
517 .dbg_name = "camss_top_ahb_clk_src",
518 .ops = &clk_ops_rcg_mnd,
519 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
520 NOMINAL, 80000000),
521 CLK_INIT(camss_top_ahb_clk_src.c),
522 },
523};
524
525static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
526 F( 19200000, xo_a, 1, 0, 0),
527 F( 50000000, gpll0, 16, 0, 0),
528 F( 100000000, gpll0, 8, 0, 0),
529 F( 133330000, gpll0, 6, 0, 0),
530 F_END
531};
532
533static struct rcg_clk apss_ahb_clk_src = {
534 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
535 .set_rate = set_rate_hid,
536 .freq_tbl = ftbl_gcc_apss_ahb_clk,
537 .current_freq = &rcg_dummy_freq,
538 .base = &virt_bases[GCC_BASE],
539 .c = {
540 .dbg_name = "apss_ahb_clk_src",
541 .ops = &clk_ops_rcg,
542 CLK_INIT(apss_ahb_clk_src.c),
543 },
544};
545
546static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
547 F( 100000000, gpll0, 8, 0, 0),
548 F( 160000000, gpll0, 5, 0, 0),
549 F( 200000000, gpll0, 4, 0, 0),
550 F_END
551};
552
553static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
554 F( 100000000, gpll0, 8, 0, 0),
555 F( 160000000, gpll0, 5, 0, 0),
556 F( 200000000, gpll0, 4, 0, 0),
557 F( 266670000, gpll0, 3, 0, 0),
558 F_END
559};
560
561
562static struct rcg_clk csi0_clk_src = {
563 .cmd_rcgr_reg = CSI0_CMD_RCGR,
564 .set_rate = set_rate_hid,
565 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
566 .current_freq = &rcg_dummy_freq,
567 .base = &virt_bases[GCC_BASE],
568 .c = {
569 .dbg_name = "csi0_clk_src",
570 .ops = &clk_ops_rcg,
571 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
572 NOMINAL, 200000000),
573 CLK_INIT(csi0_clk_src.c),
574 },
575};
576
577static struct rcg_clk csi1_clk_src = {
578 .cmd_rcgr_reg = CSI1_CMD_RCGR,
579 .set_rate = set_rate_hid,
580 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
581 .current_freq = &rcg_dummy_freq,
582 .base = &virt_bases[GCC_BASE],
583 .c = {
584 .dbg_name = "csi1_clk_src",
585 .ops = &clk_ops_rcg,
586 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
587 NOMINAL, 200000000),
588 CLK_INIT(csi1_clk_src.c),
589 },
590};
591
592static struct rcg_clk csi2_clk_src = {
593 .cmd_rcgr_reg = CSI2_CMD_RCGR,
594 .set_rate = set_rate_hid,
595 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
596 .current_freq = &rcg_dummy_freq,
597 .base = &virt_bases[GCC_BASE],
598 .c = {
599 .dbg_name = "csi2_clk_src",
600 .ops = &clk_ops_rcg,
601 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
602 NOMINAL, 200000000),
603 CLK_INIT(csi2_clk_src.c),
604 },
605};
606
607static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
608 F( 133330000, gpll0, 6, 0, 0),
609 F( 180000000, gpll6, 6, 0, 0),
610 F( 228570000, gpll0, 3.5, 0, 0),
611 F( 266670000, gpll0, 3, 0, 0),
612 F( 308570000, gpll6, 3.5, 0, 0),
613 F_END
614};
615
616static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
617 F( 166150000, gpll6, 6.5, 0, 0),
618 F( 240000000, gpll6, 4.5, 0, 0),
619 F( 308570000, gpll6, 3.5, 0, 0),
620 F( 320000000, gpll0, 2.5, 0, 0),
621 F( 360000000, gpll6, 3, 0, 0),
622 F_END
623};
624
625static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
626 F( 160000000, gpll0, 5, 0, 0),
627 F( 200000000, gpll0, 4, 0, 0),
628 F( 270000000, gpll6, 4, 0, 0),
629 F( 308570000, gpll6, 3.5, 0, 0),
630 F( 329140000, gpll4_out, 3.5, 0, 0),
631 F( 360000000, gpll6, 3, 0, 0),
632 F_END
633};
634
635static struct rcg_clk vcodec0_clk_src = {
636 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
637 .set_rate = set_rate_mnd,
638 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
639 .current_freq = &rcg_dummy_freq,
640 .base = &virt_bases[GCC_BASE],
641 .c = {
642 .dbg_name = "vcodec0_clk_src",
643 .ops = &clk_ops_rcg_mnd,
644 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
645 NOMINAL, 228570000, NOM_PLUS, 266670000,
646 HIGH, 308570000),
647 CLK_INIT(vcodec0_clk_src.c),
648 },
649};
650
651static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
652 F( 50000000, gpll0, 16, 0, 0),
653 F( 80000000, gpll0, 10, 0, 0),
654 F( 100000000, gpll0, 8, 0, 0),
655 F( 133330000, gpll0, 6, 0, 0),
656 F( 160000000, gpll0, 5, 0, 0),
657 F( 177780000, gpll0, 4.5, 0, 0),
658 F( 200000000, gpll0, 4, 0, 0),
659 F( 266670000, gpll0, 3, 0, 0),
660 F( 308570000, gpll6, 3.5, 0, 0),
661 F( 320000000, gpll0, 2.5, 0, 0),
662 F( 360000000, gpll6, 3, 0, 0),
663 F_END
664};
665
666static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
667 F( 50000000, gpll0, 16, 0, 0),
668 F( 80000000, gpll0, 10, 0, 0),
669 F( 100000000, gpll0, 8, 0, 0),
670 F( 133333333, gpll0, 6, 0, 0),
671 F( 160000000, gpll0, 5, 0, 0),
672 F( 177780000, gpll0, 4.5, 0, 0),
673 F( 200000000, gpll0, 4, 0, 0),
674 F( 266670000, gpll0, 3, 0, 0),
675 F( 308570000, gpll6, 3.5, 0, 0),
676 F( 320000000, gpll0, 2.5, 0, 0),
677 F( 360000000, gpll6, 3, 0, 0),
678 F( 400000000, gpll0, 2, 0, 0),
679 F( 432000000, gpll6, 2.5, 0, 0),
680 F_END
681};
682
683static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
684 F( 50000000, gpll0, 16, 0, 0),
685 F( 80000000, gpll0, 10, 0, 0),
686 F( 100000000, gpll0, 8, 0, 0),
687 F( 133333333, gpll0, 6, 0, 0),
688 F( 160000000, gpll0, 5, 0, 0),
689 F( 177780000, gpll0, 4.5, 0, 0),
690 F( 200000000, gpll0, 4, 0, 0),
691 F( 266670000, gpll0, 3, 0, 0),
692 F( 308570000, gpll6, 3.5, 0, 0),
693 F( 320000000, gpll0, 2.5, 0, 0),
694 F( 329140000, gpll4_out, 3.5, 0, 0),
695 F( 360000000, gpll6, 3, 0, 0),
696 F_END
697};
698
699static struct rcg_clk vfe0_clk_src = {
700 .cmd_rcgr_reg = VFE0_CMD_RCGR,
701 .set_rate = set_rate_hid,
702 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
703 .current_freq = &rcg_dummy_freq,
704 .base = &virt_bases[GCC_BASE],
705 .c = {
706 .dbg_name = "vfe0_clk_src",
707 .ops = &clk_ops_rcg,
708 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
709 NOMINAL, 308570000, NOM_PLUS, 320000000,
710 HIGH, 360000000),
711 CLK_INIT(vfe0_clk_src.c),
712 },
713};
714
715static struct rcg_clk vfe1_clk_src = {
716 .cmd_rcgr_reg = VFE1_CMD_RCGR,
717 .set_rate = set_rate_hid,
718 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
719 .current_freq = &rcg_dummy_freq,
720 .base = &virt_bases[GCC_BASE],
721 .c = {
722 .dbg_name = "vfe1_clk_src",
723 .ops = &clk_ops_rcg,
724 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
725 NOMINAL, 308570000, NOM_PLUS, 320000000,
726 HIGH, 360000000),
727 CLK_INIT(vfe1_clk_src.c),
728 },
729};
730
731static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
732 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
733 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
734 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
735 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
736 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
737 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
738 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
739 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
740 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
741 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
742 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
743 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
744 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
745 F_END
746};
747
748static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
749 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
750 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
751 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
752 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
753 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
754 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
755 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
756 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
757 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
758 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
759 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
760 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
761 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
762 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
763 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
764 F_END
765};
766
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]767static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_sdm439[] = {
768 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
769 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
770 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
771 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
772 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
773 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
774 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
775 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
776 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
777 F_SLEW( 259200000, 1296000000, gpll3, 2.5, 0, 0),
778 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
779 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
780 F_SLEW( 355200000, 710400000, gpll3, 1, 0, 0),
781 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
782 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
783 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
784 F_SLEW( 510000000, 1020000000, gpll3, 1, 0, 0),
785 F_SLEW( 560000000, 1120000000, gpll3, 1, 0, 0),
786 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
787 F_END
788};
789
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]790static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
791 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
792 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
793 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
794 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
795 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
796 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
797 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
798 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
799 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
800 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
801 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
802 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
803 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
804 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
805 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
806 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
807 F_END
808};
809
810static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
811 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
812 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
813 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
814 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
815 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
816 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
817 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
818 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
819 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
820 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
821 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
822 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
823 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
824 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
825 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
826 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
827 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
828 F_END
829};
830
831static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
832 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
833 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
834 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
835 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
836 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
837 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
838 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
839 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
840 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
841 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
842 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
843 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame]844 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]845 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
Odelu Kukatla6110fc32018-12-11 16:48:03 +0530[diff] [blame^]846 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]847 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
848 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
849 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
850 F_END
851};
852
853static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
854 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
855 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
856 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
857 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
858 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
859 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
860 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
861 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
862 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
863 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
864 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
865 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
Odelu Kukatla9c000582018-09-25 18:55:09 +0530[diff] [blame]866 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]867 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
Odelu Kukatla6110fc32018-12-11 16:48:03 +0530[diff] [blame^]868 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]869 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
870 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
871 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
872 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
873 F_END
874};
875
876static struct rcg_clk gfx3d_clk_src = {
877 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
878 .set_rate = set_rate_hid,
879 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
880 .current_freq = &rcg_dummy_freq,
881 .base = &virt_bases[GCC_BASE],
882 .c = {
883 .dbg_name = "gfx3d_clk_src",
884 .ops = &clk_ops_rcg,
885 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
886 NOMINAL, 465000000, NOM_PLUS, 500000000,
887 HIGH, 550000000),
888 CLK_INIT(gfx3d_clk_src.c),
889 },
890};
891
892static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
893 F( 19200000, xo, 1, 0, 0),
894 F( 50000000, gpll0, 16, 0, 0),
895 F_END
896};
897
898static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
899 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
900 .set_rate = set_rate_hid,
901 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
902 .current_freq = &rcg_dummy_freq,
903 .base = &virt_bases[GCC_BASE],
904 .c = {
905 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
906 .ops = &clk_ops_rcg,
907 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
908 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
909 },
910};
911
912static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
913 F( 960000, xo, 10, 1, 2),
914 F( 4800000, xo, 4, 0, 0),
915 F( 9600000, xo, 2, 0, 0),
916 F( 16000000, gpll0, 10, 1, 5),
917 F( 19200000, xo, 1, 0, 0),
918 F( 25000000, gpll0, 16, 1, 2),
919 F( 50000000, gpll0, 16, 0, 0),
920 F_END
921};
922
923static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
924 F( 960000, xo, 10, 1, 2),
925 F( 4800000, xo, 4, 0, 0),
926 F( 9600000, xo, 2, 0, 0),
927 F( 16000000, gpll0, 10, 1, 5),
928 F( 19200000, xo, 1, 0, 0),
929 F( 25000000, gpll0, 16, 1, 2),
930 F( 40000000, gpll0, 10, 1, 2),
931 F( 50000000, gpll0, 16, 0, 0),
932 F_END
933};
934
935static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
936 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
937 .set_rate = set_rate_mnd,
938 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
939 .current_freq = &rcg_dummy_freq,
940 .base = &virt_bases[GCC_BASE],
941 .c = {
942 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
943 .ops = &clk_ops_rcg_mnd,
944 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
945 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
946 },
947};
948
949static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
950 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
951 .set_rate = set_rate_hid,
952 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
953 .current_freq = &rcg_dummy_freq,
954 .base = &virt_bases[GCC_BASE],
955 .c = {
956 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
957 .ops = &clk_ops_rcg,
958 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
959 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
960 },
961};
962
963static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
964 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
965 .set_rate = set_rate_mnd,
966 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
967 .current_freq = &rcg_dummy_freq,
968 .base = &virt_bases[GCC_BASE],
969 .c = {
970 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
971 .ops = &clk_ops_rcg_mnd,
972 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
973 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
974 },
975};
976
977static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
978 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
979 .set_rate = set_rate_hid,
980 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
981 .current_freq = &rcg_dummy_freq,
982 .base = &virt_bases[GCC_BASE],
983 .c = {
984 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
985 .ops = &clk_ops_rcg,
986 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
987 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
988 },
989};
990
991static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
992 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
993 .set_rate = set_rate_mnd,
994 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
995 .current_freq = &rcg_dummy_freq,
996 .base = &virt_bases[GCC_BASE],
997 .c = {
998 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
999 .ops = &clk_ops_rcg_mnd,
1000 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1001 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
1002 },
1003};
1004
1005static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
1006 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
1007 .set_rate = set_rate_hid,
1008 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1009 .current_freq = &rcg_dummy_freq,
1010 .base = &virt_bases[GCC_BASE],
1011 .c = {
1012 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
1013 .ops = &clk_ops_rcg,
1014 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1015 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
1016 },
1017};
1018
1019static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
1020 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
1021 .set_rate = set_rate_mnd,
1022 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1023 .current_freq = &rcg_dummy_freq,
1024 .base = &virt_bases[GCC_BASE],
1025 .c = {
1026 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
1027 .ops = &clk_ops_rcg_mnd,
1028 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1029 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
1030 },
1031};
1032
1033static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
1034 F( 3686400, gpll0, 1, 72, 15625),
1035 F( 7372800, gpll0, 1, 144, 15625),
1036 F( 14745600, gpll0, 1, 288, 15625),
1037 F( 16000000, gpll0, 10, 1, 5),
1038 F( 19200000, xo, 1, 0, 0),
1039 F( 24000000, gpll0, 1, 3, 100),
1040 F( 25000000, gpll0, 16, 1, 2),
1041 F( 32000000, gpll0, 1, 1, 25),
1042 F( 40000000, gpll0, 1, 1, 20),
1043 F( 46400000, gpll0, 1, 29, 500),
1044 F( 48000000, gpll0, 1, 3, 50),
1045 F( 51200000, gpll0, 1, 8, 125),
1046 F( 56000000, gpll0, 1, 7, 100),
1047 F( 58982400, gpll0, 1, 1152, 15625),
1048 F( 60000000, gpll0, 1, 3, 40),
1049 F( 64000000, gpll0, 1, 2, 25),
1050 F_END
1051};
1052
1053static struct rcg_clk blsp1_uart1_apps_clk_src = {
1054 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1055 .set_rate = set_rate_mnd,
1056 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1057 .current_freq = &rcg_dummy_freq,
1058 .base = &virt_bases[GCC_BASE],
1059 .c = {
1060 .dbg_name = "blsp1_uart1_apps_clk_src",
1061 .ops = &clk_ops_rcg_mnd,
1062 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1063 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1064 },
1065};
1066
1067static struct rcg_clk blsp1_uart2_apps_clk_src = {
1068 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1069 .set_rate = set_rate_mnd,
1070 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1071 .current_freq = &rcg_dummy_freq,
1072 .base = &virt_bases[GCC_BASE],
1073 .c = {
1074 .dbg_name = "blsp1_uart2_apps_clk_src",
1075 .ops = &clk_ops_rcg_mnd,
1076 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1077 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1078 },
1079};
1080
1081static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1082 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1083 .set_rate = set_rate_hid,
1084 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1085 .current_freq = &rcg_dummy_freq,
1086 .base = &virt_bases[GCC_BASE],
1087 .c = {
1088 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1089 .ops = &clk_ops_rcg,
1090 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1091 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1092 },
1093};
1094
1095static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1096 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1097 .set_rate = set_rate_mnd,
1098 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1099 .current_freq = &rcg_dummy_freq,
1100 .base = &virt_bases[GCC_BASE],
1101 .c = {
1102 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1103 .ops = &clk_ops_rcg_mnd,
1104 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1105 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1106 },
1107};
1108
1109static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1110 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1111 .set_rate = set_rate_hid,
1112 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1113 .current_freq = &rcg_dummy_freq,
1114 .base = &virt_bases[GCC_BASE],
1115 .c = {
1116 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1117 .ops = &clk_ops_rcg,
1118 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1119 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1120 },
1121};
1122
1123static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1124 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1125 .set_rate = set_rate_mnd,
1126 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1127 .current_freq = &rcg_dummy_freq,
1128 .base = &virt_bases[GCC_BASE],
1129 .c = {
1130 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1131 .ops = &clk_ops_rcg_mnd,
1132 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1133 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1134 },
1135};
1136
1137static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1138 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1139 .set_rate = set_rate_hid,
1140 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1141 .current_freq = &rcg_dummy_freq,
1142 .base = &virt_bases[GCC_BASE],
1143 .c = {
1144 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1145 .ops = &clk_ops_rcg,
1146 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1147 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1148 },
1149};
1150
1151static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1152 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1153 .set_rate = set_rate_mnd,
1154 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1155 .current_freq = &rcg_dummy_freq,
1156 .base = &virt_bases[GCC_BASE],
1157 .c = {
1158 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1159 .ops = &clk_ops_rcg_mnd,
1160 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1161 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1162 },
1163};
1164
1165static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1166 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1167 .set_rate = set_rate_hid,
1168 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1169 .current_freq = &rcg_dummy_freq,
1170 .base = &virt_bases[GCC_BASE],
1171 .c = {
1172 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1173 .ops = &clk_ops_rcg,
1174 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1175 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1176 },
1177};
1178
1179static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1180 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1181 .set_rate = set_rate_mnd,
1182 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1183 .current_freq = &rcg_dummy_freq,
1184 .base = &virt_bases[GCC_BASE],
1185 .c = {
1186 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1187 .ops = &clk_ops_rcg_mnd,
1188 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1189 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1190 },
1191};
1192
1193static struct rcg_clk blsp2_uart1_apps_clk_src = {
1194 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1195 .set_rate = set_rate_mnd,
1196 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1197 .current_freq = &rcg_dummy_freq,
1198 .base = &virt_bases[GCC_BASE],
1199 .c = {
1200 .dbg_name = "blsp2_uart1_apps_clk_src",
1201 .ops = &clk_ops_rcg_mnd,
1202 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1203 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1204 },
1205};
1206
1207static struct rcg_clk blsp2_uart2_apps_clk_src = {
1208 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1209 .set_rate = set_rate_mnd,
1210 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1211 .current_freq = &rcg_dummy_freq,
1212 .base = &virt_bases[GCC_BASE],
1213 .c = {
1214 .dbg_name = "blsp2_uart2_apps_clk_src",
1215 .ops = &clk_ops_rcg_mnd,
1216 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1217 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1218 },
1219};
1220
1221static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1222 F( 19200000, xo, 1, 0, 0),
1223 F( 37500000, gpll0_out_aux, 1, 3, 64),
1224 F_END
1225};
1226
1227static struct rcg_clk cci_clk_src = {
1228 .cmd_rcgr_reg = CCI_CMD_RCGR,
1229 .set_rate = set_rate_mnd,
1230 .freq_tbl = ftbl_gcc_camss_cci_clk,
1231 .current_freq = &rcg_dummy_freq,
1232 .base = &virt_bases[GCC_BASE],
1233 .c = {
1234 .dbg_name = "cci_clk_src",
1235 .ops = &clk_ops_rcg_mnd,
1236 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1237 CLK_INIT(cci_clk_src.c),
1238 },
1239};
1240
1241static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1242 F( 133330000, gpll0, 6, 0, 0),
1243 F( 180000000, gpll6, 6, 0, 0),
1244 F( 266670000, gpll0, 3, 0, 0),
1245 F( 308570000, gpll6, 3.5, 0, 0),
1246 F( 320000000, gpll0, 2.5, 0, 0),
1247 F_END
1248};
1249
1250static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1251 F( 133333333, gpll0, 6, 0, 0),
1252 F( 160000000, gpll0, 5, 0, 0),
1253 F( 200000000, gpll0, 4, 0, 0),
1254 F( 266666667, gpll0, 3, 0, 0),
1255 F( 308570000, gpll6, 3.5, 0, 0),
1256 F( 320000000, gpll0, 2.5, 0, 0),
1257 F( 360000000, gpll6, 3, 0, 0),
1258 F_END
1259};
1260
1261static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1262 F( 133330000, gpll0, 6, 0, 0),
1263 F( 160000000, gpll0, 5, 0, 0),
1264 F( 266670000, gpll0, 3, 0, 0),
1265 F( 308570000, gpll6, 3.5, 0, 0),
1266 F( 320000000, gpll0, 2.5, 0, 0),
1267 F( 360000000, gpll6, 3, 0, 0),
1268 F_END
1269};
1270
1271static struct rcg_clk cpp_clk_src = {
1272 .cmd_rcgr_reg = CPP_CMD_RCGR,
1273 .set_rate = set_rate_hid,
1274 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1275 .current_freq = &rcg_dummy_freq,
1276 .base = &virt_bases[GCC_BASE],
1277 .c = {
1278 .dbg_name = "cpp_clk_src",
1279 .ops = &clk_ops_rcg,
1280 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1281 NOMINAL, 266670000, NOM_PLUS, 308570000,
1282 HIGH, 320000000),
1283 CLK_INIT(cpp_clk_src.c),
1284 },
1285};
1286
1287static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1288 F( 100000000, gpll0, 8, 0, 0),
1289 F( 160000000, gpll0, 5, 0, 0),
1290 F( 200000000, gpll0, 4, 0, 0),
1291 F_END
1292};
1293
1294static struct rcg_clk camss_gp0_clk_src = {
1295 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1296 .set_rate = set_rate_mnd,
1297 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1298 .current_freq = &rcg_dummy_freq,
1299 .base = &virt_bases[GCC_BASE],
1300 .c = {
1301 .dbg_name = "camss_gp0_clk_src",
1302 .ops = &clk_ops_rcg_mnd,
1303 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1304 NOMINAL, 200000000),
1305 CLK_INIT(camss_gp0_clk_src.c),
1306 },
1307};
1308
1309static struct rcg_clk camss_gp1_clk_src = {
1310 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1311 .set_rate = set_rate_mnd,
1312 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1313 .current_freq = &rcg_dummy_freq,
1314 .base = &virt_bases[GCC_BASE],
1315 .c = {
1316 .dbg_name = "camss_gp1_clk_src",
1317 .ops = &clk_ops_rcg_mnd,
1318 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1319 NOMINAL, 200000000),
1320 CLK_INIT(camss_gp1_clk_src.c),
1321 },
1322};
1323
1324static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1325 F( 133330000, gpll0, 6, 0, 0),
1326 F( 266670000, gpll0, 3, 0, 0),
1327 F( 320000000, gpll0, 2.5, 0, 0),
1328 F_END
1329};
1330
1331static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1332 F( 133333333, gpll0, 6, 0, 0),
1333 F( 200000000, gpll0, 4, 0, 0),
1334 F( 266666667, gpll0, 3, 0, 0),
1335 F( 308570000, gpll6, 3.5, 0, 0),
1336 F( 320000000, gpll0, 2.5, 0, 0),
1337 F_END
1338};
1339
1340static struct rcg_clk jpeg0_clk_src = {
1341 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1342 .set_rate = set_rate_hid,
1343 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1344 .current_freq = &rcg_dummy_freq,
1345 .base = &virt_bases[GCC_BASE],
1346 .c = {
1347 .dbg_name = "jpeg0_clk_src",
1348 .ops = &clk_ops_rcg,
1349 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1350 HIGH, 320000000),
1351 CLK_INIT(jpeg0_clk_src.c),
1352 },
1353};
1354
1355static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1356 F( 19200000, xo, 1, 0, 0),
1357 F( 24000000, gpll6, 1, 1, 45),
1358 F( 66670000, gpll0, 12, 0, 0),
1359 F_END
1360};
1361
1362static struct rcg_clk mclk0_clk_src = {
1363 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1364 .set_rate = set_rate_mnd,
1365 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1366 .current_freq = &rcg_dummy_freq,
1367 .base = &virt_bases[GCC_BASE],
1368 .c = {
1369 .dbg_name = "mclk0_clk_src",
1370 .ops = &clk_ops_rcg_mnd,
1371 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1372 CLK_INIT(mclk0_clk_src.c),
1373 },
1374};
1375
1376static struct rcg_clk mclk1_clk_src = {
1377 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1378 .set_rate = set_rate_mnd,
1379 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1380 .current_freq = &rcg_dummy_freq,
1381 .base = &virt_bases[GCC_BASE],
1382 .c = {
1383 .dbg_name = "mclk1_clk_src",
1384 .ops = &clk_ops_rcg_mnd,
1385 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1386 CLK_INIT(mclk1_clk_src.c),
1387 },
1388};
1389
1390static struct rcg_clk mclk2_clk_src = {
1391 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1392 .set_rate = set_rate_mnd,
1393 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1394 .current_freq = &rcg_dummy_freq,
1395 .base = &virt_bases[GCC_BASE],
1396 .c = {
1397 .dbg_name = "mclk2_clk_src",
1398 .ops = &clk_ops_rcg_mnd,
1399 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1400 CLK_INIT(mclk2_clk_src.c),
1401 },
1402};
1403
1404static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1405 F( 100000000, gpll0, 8, 0, 0),
1406 F( 160000000, gpll0, 5, 0, 0),
1407 F( 200000000, gpll0, 4, 0, 0),
1408 F_END
1409};
1410
1411static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1412 F( 100000000, gpll0, 8, 0, 0),
1413 F( 160000000, gpll0, 5, 0, 0),
1414 F( 200000000, gpll0, 4, 0, 0),
1415 F( 266670000, gpll0, 3, 0, 0),
1416 F_END
1417};
1418
1419static struct rcg_clk csi0phytimer_clk_src = {
1420 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1421 .set_rate = set_rate_hid,
1422 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1423 .current_freq = &rcg_dummy_freq,
1424 .base = &virt_bases[GCC_BASE],
1425 .c = {
1426 .dbg_name = "csi0phytimer_clk_src",
1427 .ops = &clk_ops_rcg,
1428 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1429 NOMINAL, 200000000),
1430 CLK_INIT(csi0phytimer_clk_src.c),
1431 },
1432};
1433
1434static struct rcg_clk csi1phytimer_clk_src = {
1435 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1436 .set_rate = set_rate_hid,
1437 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1438 .current_freq = &rcg_dummy_freq,
1439 .base = &virt_bases[GCC_BASE],
1440 .c = {
1441 .dbg_name = "csi1phytimer_clk_src",
1442 .ops = &clk_ops_rcg,
1443 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1444 NOMINAL, 200000000),
1445 CLK_INIT(csi1phytimer_clk_src.c),
1446 },
1447};
1448
1449static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1450 F( 50000000, gpll0, 16, 0, 0),
1451 F( 80000000, gpll0, 10, 0, 0),
1452 F( 100000000, gpll0, 8, 0, 0),
1453 F( 160000000, gpll0, 5, 0, 0),
1454 F_END
1455};
1456
1457static struct rcg_clk crypto_clk_src = {
1458 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1459 .set_rate = set_rate_hid,
1460 .freq_tbl = ftbl_gcc_crypto_clk,
1461 .current_freq = &rcg_dummy_freq,
1462 .base = &virt_bases[GCC_BASE],
1463 .c = {
1464 .dbg_name = "crypto_clk_src",
1465 .ops = &clk_ops_rcg,
1466 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1467 CLK_INIT(crypto_clk_src.c),
1468 },
1469};
1470
1471static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1472 F( 19200000, xo, 1, 0, 0),
1473 F_END
1474};
1475
1476static struct rcg_clk gp1_clk_src = {
1477 .cmd_rcgr_reg = GP1_CMD_RCGR,
1478 .set_rate = set_rate_mnd,
1479 .freq_tbl = ftbl_gcc_gp1_3_clk,
1480 .current_freq = &rcg_dummy_freq,
1481 .base = &virt_bases[GCC_BASE],
1482 .c = {
1483 .dbg_name = "gp1_clk_src",
1484 .ops = &clk_ops_rcg_mnd,
1485 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1486 CLK_INIT(gp1_clk_src.c),
1487 },
1488};
1489
1490static struct rcg_clk gp2_clk_src = {
1491 .cmd_rcgr_reg = GP2_CMD_RCGR,
1492 .set_rate = set_rate_mnd,
1493 .freq_tbl = ftbl_gcc_gp1_3_clk,
1494 .current_freq = &rcg_dummy_freq,
1495 .base = &virt_bases[GCC_BASE],
1496 .c = {
1497 .dbg_name = "gp2_clk_src",
1498 .ops = &clk_ops_rcg_mnd,
1499 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1500 CLK_INIT(gp2_clk_src.c),
1501 },
1502};
1503
1504static struct rcg_clk gp3_clk_src = {
1505 .cmd_rcgr_reg = GP3_CMD_RCGR,
1506 .set_rate = set_rate_mnd,
1507 .freq_tbl = ftbl_gcc_gp1_3_clk,
1508 .current_freq = &rcg_dummy_freq,
1509 .base = &virt_bases[GCC_BASE],
1510 .c = {
1511 .dbg_name = "gp3_clk_src",
1512 .ops = &clk_ops_rcg_mnd,
1513 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1514 CLK_INIT(gp3_clk_src.c),
1515 },
1516};
1517
1518static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1519 {
1520 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1521 | BVAL(4, 0, 0),
1522 .src_clk = &ext_byte0_clk_src.c,
1523 .freq_hz = 0,
1524 },
1525 F_END
1526};
1527
1528static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1529 {
1530 .div_src_val = BVAL(10, 8, xo_source_val)
1531 | BVAL(4, 0, 0),
1532 .src_clk = &xo_clk_src.c,
1533 .freq_hz = 0,
1534 },
1535 {
1536 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1537 | BVAL(4, 0, 0),
1538 .src_clk = &ext_byte0_clk_src.c,
1539 .freq_hz = 0,
1540 },
1541 {
1542 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1543 | BVAL(4, 0, 0),
1544 .src_clk = &ext_byte1_clk_src.c,
1545 .freq_hz = 0,
1546 },
1547 F_END
1548};
1549
1550static struct rcg_clk byte0_clk_src = {
1551 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1552 .set_rate = set_rate_hid,
1553 .current_freq = ftbl_gcc_mdss_byte0_clk,
1554 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1555 .base = &virt_bases[GCC_BASE],
1556 .c = {
1557 .dbg_name = "byte0_clk_src",
1558 .ops = &clk_ops_byte_multiparent,
1559 .flags = CLKFLAG_NO_RATE_CACHE,
1560 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1561 CLK_INIT(byte0_clk_src.c),
1562 },
1563};
1564
1565static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1566 {
1567 .div_src_val = BVAL(10, 8, xo_source_val)
1568 | BVAL(4, 0, 0),
1569 .src_clk = &xo_clk_src.c,
1570 .freq_hz = 0,
1571 },
1572 {
1573 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1574 | BVAL(4, 0, 0),
1575 .src_clk = &ext_byte1_clk_src.c,
1576 .freq_hz = 0,
1577 },
1578 {
1579 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1580 | BVAL(4, 0, 0),
1581 .src_clk = &ext_byte0_clk_src.c,
1582 .freq_hz = 0,
1583 },
1584 F_END
1585};
1586
1587static struct rcg_clk byte1_clk_src = {
1588 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1589 .set_rate = set_rate_hid,
1590 .current_freq = ftbl_gcc_mdss_byte1_clk,
1591 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1592 .base = &virt_bases[GCC_BASE],
1593 .c = {
1594 .dbg_name = "byte1_clk_src",
1595 .ops = &clk_ops_byte_multiparent,
1596 .flags = CLKFLAG_NO_RATE_CACHE,
1597 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1598 CLK_INIT(byte1_clk_src.c),
1599 },
1600};
1601
1602static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1603 F( 19200000, xo, 1, 0, 0),
1604 F_END
1605};
1606
1607static struct rcg_clk esc0_clk_src = {
1608 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1609 .set_rate = set_rate_hid,
1610 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1611 .current_freq = &rcg_dummy_freq,
1612 .base = &virt_bases[GCC_BASE],
1613 .c = {
1614 .dbg_name = "esc0_clk_src",
1615 .ops = &clk_ops_rcg,
1616 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1617 CLK_INIT(esc0_clk_src.c),
1618 },
1619};
1620
1621static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1622 F( 19200000, xo, 1, 0, 0),
1623 F_END
1624};
1625
1626static struct rcg_clk esc1_clk_src = {
1627 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1628 .set_rate = set_rate_hid,
1629 .freq_tbl = ftbl_esc1_clk_src,
1630 .current_freq = &rcg_dummy_freq,
1631 .base = &virt_bases[GCC_BASE],
1632 .c = {
1633 .dbg_name = "esc1_clk_src",
1634 .ops = &clk_ops_rcg,
1635 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1636 CLK_INIT(esc1_clk_src.c),
1637 },
1638};
1639
1640static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1641 F( 50000000, gpll0, 16, 0, 0),
1642 F( 80000000, gpll0, 10, 0, 0),
1643 F( 100000000, gpll0, 8, 0, 0),
1644 F( 145450000, gpll0, 5.5, 0, 0),
1645 F( 160000000, gpll0, 5, 0, 0),
1646 F( 177780000, gpll0, 4.5, 0, 0),
1647 F( 200000000, gpll0, 4, 0, 0),
1648 F( 266670000, gpll0, 3, 0, 0),
1649 F( 320000000, gpll0, 2.5, 0, 0),
1650 F_END
1651};
1652
1653static struct rcg_clk mdp_clk_src = {
1654 .cmd_rcgr_reg = MDP_CMD_RCGR,
1655 .set_rate = set_rate_hid,
1656 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1657 .current_freq = &rcg_dummy_freq,
1658 .base = &virt_bases[GCC_BASE],
1659 .c = {
1660 .dbg_name = "mdp_clk_src",
1661 .ops = &clk_ops_rcg,
1662 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1663 HIGH, 320000000),
1664 CLK_INIT(mdp_clk_src.c),
1665 },
1666};
1667
1668static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1669 {
1670 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1671 | BVAL(4, 0, 0),
1672 .src_clk = &ext_pclk0_clk_src.c,
1673 .freq_hz = 0,
1674 },
1675 F_END
1676};
1677
1678static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1679 {
1680 .div_src_val = BVAL(10, 8, xo_source_val)
1681 | BVAL(4, 0, 0),
1682 .src_clk = &xo_clk_src.c,
1683 .freq_hz = 0,
1684 },
1685 {
1686 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1687 | BVAL(4, 0, 0),
1688 .src_clk = &ext_pclk0_clk_src.c,
1689 .freq_hz = 0,
1690 },
1691 {
1692 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1693 | BVAL(4, 0, 0),
1694 .src_clk = &ext_pclk1_clk_src.c,
1695 .freq_hz = 0,
1696 },
1697 F_END
1698};
1699
1700static struct rcg_clk pclk0_clk_src = {
1701 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1702 .set_rate = set_rate_mnd,
1703 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1704 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1705 .base = &virt_bases[GCC_BASE],
1706 .c = {
1707 .dbg_name = "pclk0_clk_src",
1708 .ops = &clk_ops_pixel_multiparent,
1709 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1710 .flags = CLKFLAG_NO_RATE_CACHE,
1711 CLK_INIT(pclk0_clk_src.c),
1712 },
1713};
1714
1715static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1716 {
1717 .div_src_val = BVAL(10, 8, xo_source_val)
1718 | BVAL(4, 0, 0),
1719 .src_clk = &xo_clk_src.c,
1720 .freq_hz = 0,
1721 },
1722 {
1723 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1724 | BVAL(4, 0, 0),
1725 .src_clk = &ext_pclk1_clk_src.c,
1726 .freq_hz = 0,
1727 },
1728 {
1729 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1730 | BVAL(4, 0, 0),
1731 .src_clk = &ext_pclk0_clk_src.c,
1732 .freq_hz = 0,
1733 },
1734 F_END
1735};
1736
1737static struct rcg_clk pclk1_clk_src = {
1738 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1739 .set_rate = set_rate_mnd,
1740 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1741 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1742 .base = &virt_bases[GCC_BASE],
1743 .c = {
1744 .dbg_name = "pclk1_clk_src",
1745 .ops = &clk_ops_pixel_multiparent,
1746 .flags = CLKFLAG_NO_RATE_CACHE,
1747 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1748 CLK_INIT(pclk1_clk_src.c),
1749 },
1750};
1751
1752static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1753 F( 19200000, xo, 1, 0, 0),
1754 F_END
1755};
1756
1757static struct rcg_clk vsync_clk_src = {
1758 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1759 .set_rate = set_rate_hid,
1760 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1761 .current_freq = &rcg_dummy_freq,
1762 .base = &virt_bases[GCC_BASE],
1763 .c = {
1764 .dbg_name = "vsync_clk_src",
1765 .ops = &clk_ops_rcg,
1766 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1767 CLK_INIT(vsync_clk_src.c),
1768 },
1769};
1770
1771static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1772 F( 64000000, gpll0, 12.5, 0, 0),
1773 F_END
1774};
1775
1776static struct rcg_clk pdm2_clk_src = {
1777 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1778 .set_rate = set_rate_hid,
1779 .freq_tbl = ftbl_gcc_pdm2_clk,
1780 .current_freq = &rcg_dummy_freq,
1781 .base = &virt_bases[GCC_BASE],
1782 .c = {
1783 .dbg_name = "pdm2_clk_src",
1784 .ops = &clk_ops_rcg,
1785 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1786 CLK_INIT(pdm2_clk_src.c),
1787 },
1788};
1789
1790static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1791 F( 144000, xo, 16, 3, 25),
1792 F( 400000, xo, 12, 1, 4),
1793 F( 20000000, gpll0, 10, 1, 4),
1794 F( 25000000, gpll0, 16, 1, 2),
1795 F( 50000000, gpll0, 16, 0, 0),
1796 F( 100000000, gpll0, 8, 0, 0),
1797 F( 177770000, gpll0, 4.5, 0, 0),
1798 F( 192000000, gpll4, 6, 0, 0),
1799 F( 200000000, gpll0, 4, 0, 0),
1800 F( 384000000, gpll4, 3, 0, 0),
1801 F_END
1802};
1803
1804static struct rcg_clk sdcc1_apps_clk_src = {
1805 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1806 .set_rate = set_rate_mnd,
1807 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1808 .current_freq = &rcg_dummy_freq,
1809 .base = &virt_bases[GCC_BASE],
1810 .c = {
1811 .dbg_name = "sdcc1_apps_clk_src",
1812 .ops = &clk_ops_rcg_mnd,
1813 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1814 CLK_INIT(sdcc1_apps_clk_src.c),
1815 },
1816};
1817
1818static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1819 F( 100000000, gpll0_out_main, 8, 0, 0),
1820 F( 200000000, gpll0_out_main, 4, 0, 0),
1821 F_END
1822};
1823
1824static struct rcg_clk sdcc1_ice_core_clk_src = {
1825 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1826 .set_rate = set_rate_mnd,
1827 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1828 .current_freq = &rcg_dummy_freq,
1829 .base = &virt_bases[GCC_BASE],
1830 .c = {
1831 .dbg_name = "sdcc1_ice_core_clk_src",
1832 .ops = &clk_ops_rcg_mnd,
1833 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1834 CLK_INIT(sdcc1_ice_core_clk_src.c),
1835 },
1836};
1837
1838static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1839 F( 144000, xo, 16, 3, 25),
1840 F( 400000, xo, 12, 1, 4),
1841 F( 20000000, gpll0, 10, 1, 4),
1842 F( 25000000, gpll0, 16, 1, 2),
1843 F( 50000000, gpll0, 16, 0, 0),
1844 F( 100000000, gpll0, 8, 0, 0),
1845 F( 177770000, gpll0, 4.5, 0, 0),
1846 F( 200000000, gpll0, 4, 0, 0),
1847 F_END
1848};
1849
1850static struct rcg_clk sdcc2_apps_clk_src = {
1851 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1852 .set_rate = set_rate_mnd,
1853 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1854 .current_freq = &rcg_dummy_freq,
1855 .base = &virt_bases[GCC_BASE],
1856 .c = {
1857 .dbg_name = "sdcc2_apps_clk_src",
1858 .ops = &clk_ops_rcg_mnd,
1859 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1860 CLK_INIT(sdcc2_apps_clk_src.c),
1861 },
1862};
1863
1864static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1865 F( 60000000, gpll6_out_main, 9, 1, 2),
1866 F_END
1867};
1868
1869static struct rcg_clk usb_fs_ic_clk_src = {
1870 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1871 .set_rate = set_rate_mnd,
1872 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1873 .current_freq = &rcg_dummy_freq,
1874 .base = &virt_bases[GCC_BASE],
1875 .c = {
1876 .dbg_name = "usb_fs_ic_clk_src",
1877 .ops = &clk_ops_rcg_mnd,
1878 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1879 CLK_INIT(usb_fs_ic_clk_src.c),
1880 },
1881};
1882
1883static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1884 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1885 F_END
1886};
1887
1888static struct rcg_clk usb_fs_system_clk_src = {
1889 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1890 .set_rate = set_rate_mnd,
1891 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1892 .current_freq = &rcg_dummy_freq,
1893 .base = &virt_bases[GCC_BASE],
1894 .c = {
1895 .dbg_name = "usb_fs_system_clk_src",
1896 .ops = &clk_ops_rcg_mnd,
1897 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1898 CLK_INIT(usb_fs_system_clk_src.c),
1899 },
1900};
1901
1902static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1903 F( 57140000, gpll0, 14, 0, 0),
1904 F( 100000000, gpll0, 8, 0, 0),
1905 F( 133330000, gpll0, 6, 0, 0),
1906 F( 177780000, gpll0, 4.5, 0, 0),
1907 F_END
1908};
1909
1910static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1911 F( 80000000, gpll0, 10, 0, 0),
1912 F( 100000000, gpll0, 8, 0, 0),
1913 F( 133330000, gpll0, 6, 0, 0),
1914 F( 177780000, gpll0, 4.5, 0, 0),
1915 F_END
1916};
1917
1918static struct rcg_clk usb_hs_system_clk_src = {
1919 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1920 .set_rate = set_rate_hid,
1921 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1922 .current_freq = &rcg_dummy_freq,
1923 .base = &virt_bases[GCC_BASE],
1924 .c = {
1925 .dbg_name = "usb_hs_system_clk_src",
1926 .ops = &clk_ops_rcg,
1927 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1928 HIGH, 177780000),
1929 CLK_INIT(usb_hs_system_clk_src.c),
1930 },
1931};
1932
1933static struct branch_clk gcc_bimc_gpu_clk = {
1934 .cbcr_reg = BIMC_GPU_CBCR,
1935 .has_sibling = 1,
1936 .base = &virt_bases[GCC_BASE],
1937 .c = {
1938 .dbg_name = "gcc_bimc_gpu_clk",
1939 .ops = &clk_ops_branch,
1940 CLK_INIT(gcc_bimc_gpu_clk.c),
1941 },
1942};
1943
1944static struct branch_clk gcc_dcc_clk = {
1945 .cbcr_reg = DCC_CBCR,
1946 .has_sibling = 1,
1947 .base = &virt_bases[GCC_BASE],
1948 .c = {
1949 .dbg_name = "gcc_dcc_clk",
1950 .ops = &clk_ops_branch,
1951 CLK_INIT(gcc_dcc_clk.c),
1952 },
1953};
1954
1955static struct local_vote_clk gcc_blsp1_ahb_clk = {
1956 .cbcr_reg = BLSP1_AHB_CBCR,
1957 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1958 .en_mask = BIT(10),
1959 .base = &virt_bases[GCC_BASE],
1960 .c = {
1961 .dbg_name = "gcc_blsp1_ahb_clk",
1962 .ops = &clk_ops_vote,
1963 CLK_INIT(gcc_blsp1_ahb_clk.c),
1964 },
1965};
1966
1967static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1968 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1969 .has_sibling = 0,
1970 .base = &virt_bases[GCC_BASE],
1971 .c = {
1972 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1973 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1974 .ops = &clk_ops_branch,
1975 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1976 },
1977};
1978
1979static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1980 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1981 .has_sibling = 0,
1982 .base = &virt_bases[GCC_BASE],
1983 .c = {
1984 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1985 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1986 .ops = &clk_ops_branch,
1987 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1988 },
1989};
1990
1991static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1992 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1993 .has_sibling = 0,
1994 .base = &virt_bases[GCC_BASE],
1995 .c = {
1996 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1997 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1998 .ops = &clk_ops_branch,
1999 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
2000 },
2001};
2002
2003static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
2004 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
2005 .has_sibling = 0,
2006 .base = &virt_bases[GCC_BASE],
2007 .c = {
2008 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
2009 .parent = &blsp1_qup2_spi_apps_clk_src.c,
2010 .ops = &clk_ops_branch,
2011 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
2012 },
2013};
2014
2015static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
2016 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
2017 .has_sibling = 0,
2018 .base = &virt_bases[GCC_BASE],
2019 .c = {
2020 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
2021 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
2022 .ops = &clk_ops_branch,
2023 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
2024 },
2025};
2026
2027static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
2028 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
2029 .has_sibling = 0,
2030 .base = &virt_bases[GCC_BASE],
2031 .c = {
2032 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
2033 .parent = &blsp1_qup3_spi_apps_clk_src.c,
2034 .ops = &clk_ops_branch,
2035 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
2036 },
2037};
2038
2039static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2040 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2041 .has_sibling = 0,
2042 .base = &virt_bases[GCC_BASE],
2043 .c = {
2044 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2045 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2046 .ops = &clk_ops_branch,
2047 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2048 },
2049};
2050
2051static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2052 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2053 .has_sibling = 0,
2054 .base = &virt_bases[GCC_BASE],
2055 .c = {
2056 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2057 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2058 .ops = &clk_ops_branch,
2059 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2060 },
2061};
2062
2063static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2064 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2065 .has_sibling = 0,
2066 .base = &virt_bases[GCC_BASE],
2067 .c = {
2068 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2069 .parent = &blsp1_uart1_apps_clk_src.c,
2070 .ops = &clk_ops_branch,
2071 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2072 },
2073};
2074
2075static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2076 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2077 .has_sibling = 0,
2078 .base = &virt_bases[GCC_BASE],
2079 .c = {
2080 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2081 .parent = &blsp1_uart2_apps_clk_src.c,
2082 .ops = &clk_ops_branch,
2083 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2084 },
2085};
2086
2087static struct local_vote_clk gcc_blsp2_ahb_clk = {
2088 .cbcr_reg = BLSP2_AHB_CBCR,
2089 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2090 .en_mask = BIT(20),
2091 .base = &virt_bases[GCC_BASE],
2092 .c = {
2093 .dbg_name = "gcc_blsp2_ahb_clk",
2094 .ops = &clk_ops_vote,
2095 CLK_INIT(gcc_blsp2_ahb_clk.c),
2096 },
2097};
2098
2099static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2100 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2101 .has_sibling = 0,
2102 .base = &virt_bases[GCC_BASE],
2103 .c = {
2104 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2105 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2106 .ops = &clk_ops_branch,
2107 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2108 },
2109};
2110
2111static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2112 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2113 .has_sibling = 0,
2114 .base = &virt_bases[GCC_BASE],
2115 .c = {
2116 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2117 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2118 .ops = &clk_ops_branch,
2119 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2120 },
2121};
2122
2123static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2124 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2125 .has_sibling = 0,
2126 .base = &virt_bases[GCC_BASE],
2127 .c = {
2128 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2129 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2130 .ops = &clk_ops_branch,
2131 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2132 },
2133};
2134
2135static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2136 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2137 .has_sibling = 0,
2138 .base = &virt_bases[GCC_BASE],
2139 .c = {
2140 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2141 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2142 .ops = &clk_ops_branch,
2143 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2144 },
2145};
2146
2147static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2148 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2149 .has_sibling = 0,
2150 .base = &virt_bases[GCC_BASE],
2151 .c = {
2152 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2153 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2156 },
2157};
2158
2159static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2160 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2161 .has_sibling = 0,
2162 .base = &virt_bases[GCC_BASE],
2163 .c = {
2164 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2165 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2166 .ops = &clk_ops_branch,
2167 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2168 },
2169};
2170
2171static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2172 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2173 .has_sibling = 0,
2174 .base = &virt_bases[GCC_BASE],
2175 .c = {
2176 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2177 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2178 .ops = &clk_ops_branch,
2179 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2180 },
2181};
2182
2183static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2184 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2185 .has_sibling = 0,
2186 .base = &virt_bases[GCC_BASE],
2187 .c = {
2188 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2189 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2190 .ops = &clk_ops_branch,
2191 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2192 },
2193};
2194
2195static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2196 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2197 .has_sibling = 0,
2198 .base = &virt_bases[GCC_BASE],
2199 .c = {
2200 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2201 .parent = &blsp2_uart1_apps_clk_src.c,
2202 .ops = &clk_ops_branch,
2203 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2204 },
2205};
2206
2207static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2208 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2209 .has_sibling = 0,
2210 .base = &virt_bases[GCC_BASE],
2211 .c = {
2212 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2213 .parent = &blsp2_uart2_apps_clk_src.c,
2214 .ops = &clk_ops_branch,
2215 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2216 },
2217};
2218
2219static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2220 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2221 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2222 .en_mask = BIT(7),
2223 .base = &virt_bases[GCC_BASE],
2224 .c = {
2225 .dbg_name = "gcc_boot_rom_ahb_clk",
2226 .ops = &clk_ops_vote,
2227 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2228 },
2229};
2230
2231static struct branch_clk gcc_camss_cci_ahb_clk = {
2232 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2233 .has_sibling = 1,
2234 .base = &virt_bases[GCC_BASE],
2235 .c = {
2236 .dbg_name = "gcc_camss_cci_ahb_clk",
2237 .parent = &camss_top_ahb_clk_src.c,
2238 .ops = &clk_ops_branch,
2239 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2240 },
2241};
2242
2243static struct branch_clk gcc_camss_cci_clk = {
2244 .cbcr_reg = CAMSS_CCI_CBCR,
2245 .has_sibling = 0,
2246 .base = &virt_bases[GCC_BASE],
2247 .c = {
2248 .dbg_name = "gcc_camss_cci_clk",
2249 .parent = &cci_clk_src.c,
2250 .ops = &clk_ops_branch,
2251 CLK_INIT(gcc_camss_cci_clk.c),
2252 },
2253};
2254
2255static struct branch_clk gcc_camss_cpp_ahb_clk = {
2256 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2257 .has_sibling = 1,
2258 .base = &virt_bases[GCC_BASE],
2259 .c = {
2260 .dbg_name = "gcc_camss_cpp_ahb_clk",
2261 .parent = &camss_top_ahb_clk_src.c,
2262 .ops = &clk_ops_branch,
2263 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2264 },
2265};
2266
2267static struct branch_clk gcc_camss_cpp_axi_clk = {
2268 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2269 .has_sibling = 1,
2270 .base = &virt_bases[GCC_BASE],
2271 .c = {
2272 .dbg_name = "gcc_camss_cpp_axi_clk",
2273 .ops = &clk_ops_branch,
2274 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2275 },
2276};
2277
2278static struct branch_clk gcc_camss_cpp_clk = {
2279 .cbcr_reg = CAMSS_CPP_CBCR,
2280 .has_sibling = 0,
2281 .base = &virt_bases[GCC_BASE],
2282 .c = {
2283 .dbg_name = "gcc_camss_cpp_clk",
2284 .parent = &cpp_clk_src.c,
2285 .ops = &clk_ops_branch,
2286 CLK_INIT(gcc_camss_cpp_clk.c),
2287 },
2288};
2289
2290static struct branch_clk gcc_camss_csi0_ahb_clk = {
2291 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2292 .has_sibling = 1,
2293 .base = &virt_bases[GCC_BASE],
2294 .c = {
2295 .dbg_name = "gcc_camss_csi0_ahb_clk",
2296 .parent = &camss_top_ahb_clk_src.c,
2297 .ops = &clk_ops_branch,
2298 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2299 },
2300};
2301
2302static struct branch_clk gcc_camss_csi0_clk = {
2303 .cbcr_reg = CAMSS_CSI0_CBCR,
2304 .has_sibling = 1,
2305 .base = &virt_bases[GCC_BASE],
2306 .c = {
2307 .dbg_name = "gcc_camss_csi0_clk",
2308 .parent = &csi0_clk_src.c,
2309 .ops = &clk_ops_branch,
2310 CLK_INIT(gcc_camss_csi0_clk.c),
2311 },
2312};
2313
2314static struct branch_clk gcc_camss_csi0phy_clk = {
2315 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2316 .has_sibling = 1,
2317 .base = &virt_bases[GCC_BASE],
2318 .c = {
2319 .dbg_name = "gcc_camss_csi0phy_clk",
2320 .parent = &csi0_clk_src.c,
2321 .ops = &clk_ops_branch,
2322 CLK_INIT(gcc_camss_csi0phy_clk.c),
2323 },
2324};
2325
2326static struct branch_clk gcc_camss_csi0pix_clk = {
2327 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2328 .has_sibling = 1,
2329 .base = &virt_bases[GCC_BASE],
2330 .c = {
2331 .dbg_name = "gcc_camss_csi0pix_clk",
2332 .parent = &csi0_clk_src.c,
2333 .ops = &clk_ops_branch,
2334 CLK_INIT(gcc_camss_csi0pix_clk.c),
2335 },
2336};
2337
2338static struct branch_clk gcc_camss_csi0rdi_clk = {
2339 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2340 .has_sibling = 1,
2341 .base = &virt_bases[GCC_BASE],
2342 .c = {
2343 .dbg_name = "gcc_camss_csi0rdi_clk",
2344 .parent = &csi0_clk_src.c,
2345 .ops = &clk_ops_branch,
2346 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2347 },
2348};
2349
2350static struct branch_clk gcc_camss_csi1_ahb_clk = {
2351 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2352 .has_sibling = 1,
2353 .base = &virt_bases[GCC_BASE],
2354 .c = {
2355 .dbg_name = "gcc_camss_csi1_ahb_clk",
2356 .parent = &camss_top_ahb_clk_src.c,
2357 .ops = &clk_ops_branch,
2358 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2359 },
2360};
2361
2362static struct branch_clk gcc_camss_csi1_clk = {
2363 .cbcr_reg = CAMSS_CSI1_CBCR,
2364 .has_sibling = 1,
2365 .base = &virt_bases[GCC_BASE],
2366 .c = {
2367 .dbg_name = "gcc_camss_csi1_clk",
2368 .parent = &csi1_clk_src.c,
2369 .ops = &clk_ops_branch,
2370 CLK_INIT(gcc_camss_csi1_clk.c),
2371 },
2372};
2373
2374static struct branch_clk gcc_camss_csi1phy_clk = {
2375 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2376 .has_sibling = 1,
2377 .base = &virt_bases[GCC_BASE],
2378 .c = {
2379 .dbg_name = "gcc_camss_csi1phy_clk",
2380 .parent = &csi1_clk_src.c,
2381 .ops = &clk_ops_branch,
2382 CLK_INIT(gcc_camss_csi1phy_clk.c),
2383 },
2384};
2385
2386static struct branch_clk gcc_camss_csi1pix_clk = {
2387 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2388 .has_sibling = 1,
2389 .base = &virt_bases[GCC_BASE],
2390 .c = {
2391 .dbg_name = "gcc_camss_csi1pix_clk",
2392 .parent = &csi1_clk_src.c,
2393 .ops = &clk_ops_branch,
2394 CLK_INIT(gcc_camss_csi1pix_clk.c),
2395 },
2396};
2397
2398static struct branch_clk gcc_camss_csi1rdi_clk = {
2399 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2400 .has_sibling = 1,
2401 .base = &virt_bases[GCC_BASE],
2402 .c = {
2403 .dbg_name = "gcc_camss_csi1rdi_clk",
2404 .parent = &csi1_clk_src.c,
2405 .ops = &clk_ops_branch,
2406 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2407 },
2408};
2409
2410static struct branch_clk gcc_camss_csi2_ahb_clk = {
2411 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2412 .has_sibling = 1,
2413 .base = &virt_bases[GCC_BASE],
2414 .c = {
2415 .dbg_name = "gcc_camss_csi2_ahb_clk",
2416 .parent = &camss_top_ahb_clk_src.c,
2417 .ops = &clk_ops_branch,
2418 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2419 },
2420};
2421
2422static struct branch_clk gcc_camss_csi2_clk = {
2423 .cbcr_reg = CAMSS_CSI2_CBCR,
2424 .has_sibling = 1,
2425 .base = &virt_bases[GCC_BASE],
2426 .c = {
2427 .dbg_name = "gcc_camss_csi2_clk",
2428 .parent = &csi2_clk_src.c,
2429 .ops = &clk_ops_branch,
2430 CLK_INIT(gcc_camss_csi2_clk.c),
2431 },
2432};
2433
2434static struct branch_clk gcc_camss_csi2phy_clk = {
2435 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2436 .has_sibling = 1,
2437 .base = &virt_bases[GCC_BASE],
2438 .c = {
2439 .dbg_name = "gcc_camss_csi2phy_clk",
2440 .parent = &csi2_clk_src.c,
2441 .ops = &clk_ops_branch,
2442 CLK_INIT(gcc_camss_csi2phy_clk.c),
2443 },
2444};
2445
2446static struct branch_clk gcc_camss_csi2pix_clk = {
2447 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2448 .has_sibling = 1,
2449 .base = &virt_bases[GCC_BASE],
2450 .c = {
2451 .dbg_name = "gcc_camss_csi2pix_clk",
2452 .parent = &csi2_clk_src.c,
2453 .ops = &clk_ops_branch,
2454 CLK_INIT(gcc_camss_csi2pix_clk.c),
2455 },
2456};
2457
2458static struct branch_clk gcc_camss_csi2rdi_clk = {
2459 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2460 .has_sibling = 1,
2461 .base = &virt_bases[GCC_BASE],
2462 .c = {
2463 .dbg_name = "gcc_camss_csi2rdi_clk",
2464 .parent = &csi2_clk_src.c,
2465 .ops = &clk_ops_branch,
2466 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2467 },
2468};
2469
2470static struct branch_clk gcc_camss_csi_vfe0_clk = {
2471 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2472 .has_sibling = 1,
2473 .base = &virt_bases[GCC_BASE],
2474 .c = {
2475 .dbg_name = "gcc_camss_csi_vfe0_clk",
2476 .parent = &vfe0_clk_src.c,
2477 .ops = &clk_ops_branch,
2478 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2479 },
2480};
2481
2482static struct branch_clk gcc_camss_csi_vfe1_clk = {
2483 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2484 .has_sibling = 1,
2485 .base = &virt_bases[GCC_BASE],
2486 .c = {
2487 .dbg_name = "gcc_camss_csi_vfe1_clk",
2488 .parent = &vfe1_clk_src.c,
2489 .ops = &clk_ops_branch,
2490 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2491 },
2492};
2493
2494static struct branch_clk gcc_camss_gp0_clk = {
2495 .cbcr_reg = CAMSS_GP0_CBCR,
2496 .has_sibling = 0,
2497 .base = &virt_bases[GCC_BASE],
2498 .c = {
2499 .dbg_name = "gcc_camss_gp0_clk",
2500 .parent = &camss_gp0_clk_src.c,
2501 .ops = &clk_ops_branch,
2502 CLK_INIT(gcc_camss_gp0_clk.c),
2503 },
2504};
2505
2506static struct branch_clk gcc_camss_gp1_clk = {
2507 .cbcr_reg = CAMSS_GP1_CBCR,
2508 .has_sibling = 0,
2509 .base = &virt_bases[GCC_BASE],
2510 .c = {
2511 .dbg_name = "gcc_camss_gp1_clk",
2512 .parent = &camss_gp1_clk_src.c,
2513 .ops = &clk_ops_branch,
2514 CLK_INIT(gcc_camss_gp1_clk.c),
2515 },
2516};
2517
2518static struct branch_clk gcc_camss_ispif_ahb_clk = {
2519 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2520 .has_sibling = 0,
2521 .base = &virt_bases[GCC_BASE],
2522 .c = {
2523 .dbg_name = "gcc_camss_ispif_ahb_clk",
2524 .parent = &camss_top_ahb_clk_src.c,
2525 .ops = &clk_ops_branch,
2526 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2527 },
2528};
2529
2530static struct branch_clk gcc_camss_jpeg0_clk = {
2531 .cbcr_reg = CAMSS_JPEG0_CBCR,
2532 .has_sibling = 0,
2533 .base = &virt_bases[GCC_BASE],
2534 .c = {
2535 .dbg_name = "gcc_camss_jpeg0_clk",
2536 .parent = &jpeg0_clk_src.c,
2537 .ops = &clk_ops_branch,
2538 CLK_INIT(gcc_camss_jpeg0_clk.c),
2539 },
2540};
2541
2542static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2543 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2544 .has_sibling = 1,
2545 .base = &virt_bases[GCC_BASE],
2546 .c = {
2547 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2548 .parent = &camss_top_ahb_clk_src.c,
2549 .ops = &clk_ops_branch,
2550 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2551 },
2552};
2553
2554static struct branch_clk gcc_camss_jpeg_axi_clk = {
2555 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2556 .has_sibling = 1,
2557 .base = &virt_bases[GCC_BASE],
2558 .c = {
2559 .dbg_name = "gcc_camss_jpeg_axi_clk",
2560 .ops = &clk_ops_branch,
2561 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2562 },
2563};
2564
2565static struct branch_clk gcc_camss_mclk0_clk = {
2566 .cbcr_reg = CAMSS_MCLK0_CBCR,
2567 .has_sibling = 0,
2568 .base = &virt_bases[GCC_BASE],
2569 .c = {
2570 .dbg_name = "gcc_camss_mclk0_clk",
2571 .parent = &mclk0_clk_src.c,
2572 .ops = &clk_ops_branch,
2573 CLK_INIT(gcc_camss_mclk0_clk.c),
2574 },
2575};
2576
2577static struct branch_clk gcc_camss_mclk1_clk = {
2578 .cbcr_reg = CAMSS_MCLK1_CBCR,
2579 .has_sibling = 0,
2580 .base = &virt_bases[GCC_BASE],
2581 .c = {
2582 .dbg_name = "gcc_camss_mclk1_clk",
2583 .parent = &mclk1_clk_src.c,
2584 .ops = &clk_ops_branch,
2585 CLK_INIT(gcc_camss_mclk1_clk.c),
2586 },
2587};
2588
2589static struct branch_clk gcc_camss_mclk2_clk = {
2590 .cbcr_reg = CAMSS_MCLK2_CBCR,
2591 .has_sibling = 0,
2592 .base = &virt_bases[GCC_BASE],
2593 .c = {
2594 .dbg_name = "gcc_camss_mclk2_clk",
2595 .parent = &mclk2_clk_src.c,
2596 .ops = &clk_ops_branch,
2597 CLK_INIT(gcc_camss_mclk2_clk.c),
2598 },
2599};
2600
2601static struct branch_clk gcc_camss_micro_ahb_clk = {
2602 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2603 .bcr_reg = CAMSS_MICRO_BCR,
2604 .has_sibling = 1,
2605 .base = &virt_bases[GCC_BASE],
2606 .c = {
2607 .dbg_name = "gcc_camss_micro_ahb_clk",
2608 .parent = &camss_top_ahb_clk_src.c,
2609 .ops = &clk_ops_branch,
2610 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2611 },
2612};
2613
2614static struct branch_clk gcc_camss_csi0phytimer_clk = {
2615 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2616 .has_sibling = 0,
2617 .base = &virt_bases[GCC_BASE],
2618 .c = {
2619 .dbg_name = "gcc_camss_csi0phytimer_clk",
2620 .parent = &csi0phytimer_clk_src.c,
2621 .ops = &clk_ops_branch,
2622 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2623 },
2624};
2625
2626static struct branch_clk gcc_camss_csi1phytimer_clk = {
2627 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2628 .has_sibling = 0,
2629 .base = &virt_bases[GCC_BASE],
2630 .c = {
2631 .dbg_name = "gcc_camss_csi1phytimer_clk",
2632 .parent = &csi1phytimer_clk_src.c,
2633 .ops = &clk_ops_branch,
2634 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2635 },
2636};
2637
2638static struct branch_clk gcc_camss_ahb_clk = {
2639 .cbcr_reg = CAMSS_AHB_CBCR,
2640 .has_sibling = 1,
2641 .base = &virt_bases[GCC_BASE],
2642 .c = {
2643 .dbg_name = "gcc_camss_ahb_clk",
2644 .ops = &clk_ops_branch,
2645 CLK_INIT(gcc_camss_ahb_clk.c),
2646 },
2647};
2648
2649static struct branch_clk gcc_camss_top_ahb_clk = {
2650 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2651 .has_sibling = 1,
2652 .base = &virt_bases[GCC_BASE],
2653 .c = {
2654 .dbg_name = "gcc_camss_top_ahb_clk",
2655 .parent = &camss_top_ahb_clk_src.c,
2656 .ops = &clk_ops_branch,
2657 CLK_INIT(gcc_camss_top_ahb_clk.c),
2658 },
2659};
2660
2661static struct branch_clk gcc_camss_vfe0_clk = {
2662 .cbcr_reg = CAMSS_VFE0_CBCR,
2663 .has_sibling = 1,
2664 .base = &virt_bases[GCC_BASE],
2665 .c = {
2666 .dbg_name = "gcc_camss_vfe0_clk",
2667 .parent = &vfe0_clk_src.c,
2668 .ops = &clk_ops_branch,
2669 CLK_INIT(gcc_camss_vfe0_clk.c),
2670 },
2671};
2672
2673static struct branch_clk gcc_camss_vfe_ahb_clk = {
2674 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2675 .has_sibling = 1,
2676 .base = &virt_bases[GCC_BASE],
2677 .c = {
2678 .dbg_name = "gcc_camss_vfe_ahb_clk",
2679 .ops = &clk_ops_branch,
2680 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2681 },
2682};
2683
2684static struct branch_clk gcc_camss_vfe_axi_clk = {
2685 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2686 .has_sibling = 1,
2687 .base = &virt_bases[GCC_BASE],
2688 .c = {
2689 .dbg_name = "gcc_camss_vfe_axi_clk",
2690 .ops = &clk_ops_branch,
2691 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2692 },
2693};
2694
2695static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2696 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2697 .has_sibling = 1,
2698 .base = &virt_bases[GCC_BASE],
2699 .c = {
2700 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2701 .parent = &camss_top_ahb_clk_src.c,
2702 .ops = &clk_ops_branch,
2703 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2704 },
2705};
2706
2707static struct branch_clk gcc_camss_vfe1_axi_clk = {
2708 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2709 .has_sibling = 1,
2710 .base = &virt_bases[GCC_BASE],
2711 .c = {
2712 .dbg_name = "gcc_camss_vfe1_axi_clk",
2713 .ops = &clk_ops_branch,
2714 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2715 },
2716};
2717
2718static struct branch_clk gcc_camss_vfe1_clk = {
2719 .cbcr_reg = CAMSS_VFE1_CBCR,
2720 .has_sibling = 1,
2721 .base = &virt_bases[GCC_BASE],
2722 .c = {
2723 .dbg_name = "gcc_camss_vfe1_clk",
2724 .parent = &vfe1_clk_src.c,
2725 .ops = &clk_ops_branch,
2726 CLK_INIT(gcc_camss_vfe1_clk.c),
2727 },
2728};
2729
2730static struct local_vote_clk gcc_crypto_ahb_clk = {
2731 .cbcr_reg = CRYPTO_AHB_CBCR,
2732 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2733 .en_mask = BIT(0),
2734 .base = &virt_bases[GCC_BASE],
2735 .c = {
2736 .dbg_name = "gcc_crypto_ahb_clk",
2737 .parent = &crypto_clk_src.c,
2738 .ops = &clk_ops_vote,
2739 CLK_INIT(gcc_crypto_ahb_clk.c),
2740 },
2741};
2742
2743static struct local_vote_clk gcc_crypto_axi_clk = {
2744 .cbcr_reg = CRYPTO_AXI_CBCR,
2745 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2746 .en_mask = BIT(1),
2747 .base = &virt_bases[GCC_BASE],
2748 .c = {
2749 .dbg_name = "gcc_crypto_axi_clk",
2750 .ops = &clk_ops_vote,
2751 CLK_INIT(gcc_crypto_axi_clk.c),
2752 },
2753};
2754
2755static struct local_vote_clk gcc_crypto_clk = {
2756 .cbcr_reg = CRYPTO_CBCR,
2757 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2758 .en_mask = BIT(2),
2759 .base = &virt_bases[GCC_BASE],
2760 .c = {
2761 .dbg_name = "gcc_crypto_clk",
2762 .parent = &crypto_clk_src.c,
2763 .ops = &clk_ops_vote,
2764 CLK_INIT(gcc_crypto_clk.c),
2765 },
2766};
2767
2768static struct gate_clk gcc_oxili_gmem_clk = {
2769 .en_reg = OXILI_GMEM_CBCR,
2770 .en_mask = BIT(0),
2771 .delay_us = 50,
2772 .base = &virt_bases[GCC_BASE],
2773 .c = {
2774 .dbg_name = "gcc_oxili_gmem_clk",
2775 .parent = &gfx3d_clk_src.c,
2776 .ops = &clk_ops_gate,
2777 CLK_INIT(gcc_oxili_gmem_clk.c),
2778 },
2779};
2780
2781static struct branch_clk gcc_gp1_clk = {
2782 .cbcr_reg = GP1_CBCR,
2783 .has_sibling = 0,
2784 .base = &virt_bases[GCC_BASE],
2785 .c = {
2786 .dbg_name = "gcc_gp1_clk",
2787 .parent = &gp1_clk_src.c,
2788 .ops = &clk_ops_branch,
2789 CLK_INIT(gcc_gp1_clk.c),
2790 },
2791};
2792
2793static struct branch_clk gcc_gp2_clk = {
2794 .cbcr_reg = GP2_CBCR,
2795 .has_sibling = 0,
2796 .base = &virt_bases[GCC_BASE],
2797 .c = {
2798 .dbg_name = "gcc_gp2_clk",
2799 .parent = &gp2_clk_src.c,
2800 .ops = &clk_ops_branch,
2801 CLK_INIT(gcc_gp2_clk.c),
2802 },
2803};
2804
2805static struct branch_clk gcc_gp3_clk = {
2806 .cbcr_reg = GP3_CBCR,
2807 .has_sibling = 0,
2808 .base = &virt_bases[GCC_BASE],
2809 .c = {
2810 .dbg_name = "gcc_gp3_clk",
2811 .parent = &gp3_clk_src.c,
2812 .ops = &clk_ops_branch,
2813 CLK_INIT(gcc_gp3_clk.c),
2814 },
2815};
2816
2817static struct branch_clk gcc_mdss_ahb_clk = {
2818 .cbcr_reg = MDSS_AHB_CBCR,
2819 .has_sibling = 1,
2820 .base = &virt_bases[GCC_BASE],
2821 .c = {
2822 .dbg_name = "gcc_mdss_ahb_clk",
2823 .ops = &clk_ops_branch,
2824 CLK_INIT(gcc_mdss_ahb_clk.c),
2825 },
2826};
2827
2828static struct branch_clk gcc_mdss_axi_clk = {
2829 .cbcr_reg = MDSS_AXI_CBCR,
2830 .has_sibling = 1,
2831 .base = &virt_bases[GCC_BASE],
2832 .c = {
2833 .dbg_name = "gcc_mdss_axi_clk",
2834 .ops = &clk_ops_branch,
2835 CLK_INIT(gcc_mdss_axi_clk.c),
2836 },
2837};
2838
2839static struct branch_clk gcc_mdss_byte0_clk = {
2840 .cbcr_reg = MDSS_BYTE0_CBCR,
2841 .has_sibling = 0,
2842 .base = &virt_bases[GCC_BASE],
2843 .c = {
2844 .dbg_name = "gcc_mdss_byte0_clk",
2845 .parent = &byte0_clk_src.c,
2846 .ops = &clk_ops_branch,
2847 .flags = CLKFLAG_NO_RATE_CACHE,
2848 CLK_INIT(gcc_mdss_byte0_clk.c),
2849 },
2850};
2851
2852static struct branch_clk gcc_mdss_byte1_clk = {
2853 .cbcr_reg = MDSS_BYTE1_CBCR,
2854 .has_sibling = 0,
2855 .base = &virt_bases[GCC_BASE],
2856 .c = {
2857 .dbg_name = "gcc_mdss_byte1_clk",
2858 .parent = &byte1_clk_src.c,
2859 .ops = &clk_ops_branch,
2860 .flags = CLKFLAG_NO_RATE_CACHE,
2861 CLK_INIT(gcc_mdss_byte1_clk.c),
2862 },
2863};
2864
2865static struct branch_clk gcc_mdss_esc0_clk = {
2866 .cbcr_reg = MDSS_ESC0_CBCR,
2867 .has_sibling = 0,
2868 .base = &virt_bases[GCC_BASE],
2869 .c = {
2870 .dbg_name = "gcc_mdss_esc0_clk",
2871 .parent = &esc0_clk_src.c,
2872 .ops = &clk_ops_branch,
2873 CLK_INIT(gcc_mdss_esc0_clk.c),
2874 },
2875};
2876
2877static struct branch_clk gcc_mdss_esc1_clk = {
2878 .cbcr_reg = MDSS_ESC1_CBCR,
2879 .has_sibling = 0,
2880 .base = &virt_bases[GCC_BASE],
2881 .c = {
2882 .dbg_name = "gcc_mdss_esc1_clk",
2883 .parent = &esc1_clk_src.c,
2884 .ops = &clk_ops_branch,
2885 CLK_INIT(gcc_mdss_esc1_clk.c),
2886 },
2887};
2888
2889static struct branch_clk gcc_mdss_mdp_clk = {
2890 .cbcr_reg = MDSS_MDP_CBCR,
2891 .has_sibling = 0,
2892 .base = &virt_bases[GCC_BASE],
2893 .c = {
2894 .dbg_name = "gcc_mdss_mdp_clk",
2895 .parent = &mdp_clk_src.c,
2896 .ops = &clk_ops_branch,
2897 CLK_INIT(gcc_mdss_mdp_clk.c),
2898 },
2899};
2900
2901static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2902static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2903
2904static struct branch_clk gcc_mdss_pclk0_clk = {
2905 .cbcr_reg = MDSS_PCLK0_CBCR,
2906 .has_sibling = 0,
2907 .base = &virt_bases[GCC_BASE],
2908 .c = {
2909 .dbg_name = "gcc_mdss_pclk0_clk",
2910 .parent = &pclk0_clk_src.c,
2911 .ops = &clk_ops_branch,
2912 .flags = CLKFLAG_NO_RATE_CACHE,
2913 CLK_INIT(gcc_mdss_pclk0_clk.c),
2914 },
2915};
2916
2917static struct branch_clk gcc_mdss_pclk1_clk = {
2918 .cbcr_reg = MDSS_PCLK1_CBCR,
2919 .has_sibling = 0,
2920 .base = &virt_bases[GCC_BASE],
2921 .c = {
2922 .dbg_name = "gcc_mdss_pclk1_clk",
2923 .parent = &pclk1_clk_src.c,
2924 .ops = &clk_ops_branch,
2925 .flags = CLKFLAG_NO_RATE_CACHE,
2926 CLK_INIT(gcc_mdss_pclk1_clk.c),
2927 },
2928};
2929
2930static struct branch_clk gcc_mdss_vsync_clk = {
2931 .cbcr_reg = MDSS_VSYNC_CBCR,
2932 .has_sibling = 0,
2933 .base = &virt_bases[GCC_BASE],
2934 .c = {
2935 .dbg_name = "gcc_mdss_vsync_clk",
2936 .parent = &vsync_clk_src.c,
2937 .ops = &clk_ops_branch,
2938 CLK_INIT(gcc_mdss_vsync_clk.c),
2939 },
2940};
2941
2942static struct branch_clk gcc_mss_cfg_ahb_clk = {
2943 .cbcr_reg = MSS_CFG_AHB_CBCR,
2944 .has_sibling = 1,
2945 .base = &virt_bases[GCC_BASE],
2946 .c = {
2947 .dbg_name = "gcc_mss_cfg_ahb_clk",
2948 .ops = &clk_ops_branch,
2949 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2950 },
2951};
2952
2953static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2954 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2955 .has_sibling = 1,
2956 .base = &virt_bases[GCC_BASE],
2957 .c = {
2958 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2959 .ops = &clk_ops_branch,
2960 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2961 },
2962};
2963
2964static struct local_vote_clk gcc_apss_tcu_clk;
2965static struct branch_clk gcc_bimc_gfx_clk = {
2966 .cbcr_reg = BIMC_GFX_CBCR,
2967 .has_sibling = 1,
2968 .base = &virt_bases[GCC_BASE],
2969 .c = {
2970 .dbg_name = "gcc_bimc_gfx_clk",
2971 .ops = &clk_ops_branch,
2972 CLK_INIT(gcc_bimc_gfx_clk.c),
2973 .depends = &gcc_apss_tcu_clk.c,
2974 },
2975};
2976
2977static struct branch_clk gcc_oxili_ahb_clk = {
2978 .cbcr_reg = OXILI_AHB_CBCR,
2979 .has_sibling = 1,
2980 .base = &virt_bases[GCC_BASE],
2981 .c = {
2982 .dbg_name = "gcc_oxili_ahb_clk",
2983 .ops = &clk_ops_branch,
2984 CLK_INIT(gcc_oxili_ahb_clk.c),
2985 },
2986};
2987
2988static struct branch_clk gcc_oxili_gfx3d_clk = {
2989 .cbcr_reg = OXILI_GFX3D_CBCR,
2990 .has_sibling = 0,
2991 .base = &virt_bases[GCC_BASE],
2992 .c = {
2993 .dbg_name = "gcc_oxili_gfx3d_clk",
2994 .parent = &gfx3d_clk_src.c,
2995 .ops = &clk_ops_branch,
2996 CLK_INIT(gcc_oxili_gfx3d_clk.c),
2997 },
2998};
2999
3000static struct branch_clk gcc_oxili_timer_clk = {
3001 .cbcr_reg = OXILI_TIMER_CBCR,
3002 .has_sibling = 0,
3003 .base = &virt_bases[GCC_BASE],
3004 .c = {
3005 .dbg_name = "gcc_oxili_timer_clk",
3006 .parent = &xo_clk_src.c,
3007 .ops = &clk_ops_branch,
3008 CLK_INIT(gcc_oxili_timer_clk.c),
3009 },
3010};
3011
3012static struct branch_clk gcc_oxili_aon_clk = {
3013 .cbcr_reg = OXILI_AON_CBCR,
3014 .has_sibling = 0,
3015 .base = &virt_bases[GCC_BASE],
3016 .c = {
3017 .dbg_name = "gcc_oxili_aon_clk",
3018 .parent = &gfx3d_clk_src.c,
3019 .ops = &clk_ops_branch,
3020 CLK_INIT(gcc_oxili_aon_clk.c),
3021 },
3022};
3023
3024static struct branch_clk gcc_pdm2_clk = {
3025 .cbcr_reg = PDM2_CBCR,
3026 .has_sibling = 0,
3027 .base = &virt_bases[GCC_BASE],
3028 .c = {
3029 .dbg_name = "gcc_pdm2_clk",
3030 .parent = &pdm2_clk_src.c,
3031 .ops = &clk_ops_branch,
3032 CLK_INIT(gcc_pdm2_clk.c),
3033 },
3034};
3035
3036static struct branch_clk gcc_pdm_ahb_clk = {
3037 .cbcr_reg = PDM_AHB_CBCR,
3038 .has_sibling = 1,
3039 .base = &virt_bases[GCC_BASE],
3040 .c = {
3041 .dbg_name = "gcc_pdm_ahb_clk",
3042 .ops = &clk_ops_branch,
3043 CLK_INIT(gcc_pdm_ahb_clk.c),
3044 },
3045};
3046
3047static struct local_vote_clk gcc_prng_ahb_clk = {
3048 .cbcr_reg = PRNG_AHB_CBCR,
3049 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3050 .en_mask = BIT(8),
3051 .base = &virt_bases[GCC_BASE],
3052 .c = {
3053 .dbg_name = "gcc_prng_ahb_clk",
3054 .ops = &clk_ops_vote,
3055 CLK_INIT(gcc_prng_ahb_clk.c),
3056 },
3057};
3058
3059static struct local_vote_clk gcc_qdss_dap_clk = {
3060 .cbcr_reg = QDSS_DAP_CBCR,
3061 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3062 .en_mask = BIT(21),
3063 .base = &virt_bases[GCC_BASE],
3064 .c = {
3065 .dbg_name = "gcc_qdss_dap_clk",
3066 .ops = &clk_ops_vote,
3067 CLK_INIT(gcc_qdss_dap_clk.c),
3068 },
3069};
3070
3071static struct branch_clk gcc_sdcc1_ahb_clk = {
3072 .cbcr_reg = SDCC1_AHB_CBCR,
3073 .has_sibling = 1,
3074 .base = &virt_bases[GCC_BASE],
3075 .c = {
3076 .dbg_name = "gcc_sdcc1_ahb_clk",
3077 .ops = &clk_ops_branch,
3078 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3079 },
3080};
3081
3082static struct branch_clk gcc_sdcc1_apps_clk = {
3083 .cbcr_reg = SDCC1_APPS_CBCR,
3084 .has_sibling = 0,
3085 .base = &virt_bases[GCC_BASE],
3086 .c = {
3087 .dbg_name = "gcc_sdcc1_apps_clk",
3088 .parent = &sdcc1_apps_clk_src.c,
3089 .ops = &clk_ops_branch,
3090 CLK_INIT(gcc_sdcc1_apps_clk.c),
3091 },
3092};
3093
3094static struct branch_clk gcc_sdcc1_ice_core_clk = {
3095 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3096 .has_sibling = 0,
3097 .base = &virt_bases[GCC_BASE],
3098 .c = {
3099 .dbg_name = "gcc_sdcc1_ice_core_clk",
3100 .parent = &sdcc1_ice_core_clk_src.c,
3101 .ops = &clk_ops_branch,
3102 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3103 }
3104};
3105
3106static struct branch_clk gcc_sdcc2_ahb_clk = {
3107 .cbcr_reg = SDCC2_AHB_CBCR,
3108 .has_sibling = 1,
3109 .base = &virt_bases[GCC_BASE],
3110 .c = {
3111 .dbg_name = "gcc_sdcc2_ahb_clk",
3112 .ops = &clk_ops_branch,
3113 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3114 },
3115};
3116
3117static struct branch_clk gcc_sdcc2_apps_clk = {
3118 .cbcr_reg = SDCC2_APPS_CBCR,
3119 .has_sibling = 0,
3120 .base = &virt_bases[GCC_BASE],
3121 .c = {
3122 .dbg_name = "gcc_sdcc2_apps_clk",
3123 .parent = &sdcc2_apps_clk_src.c,
3124 .ops = &clk_ops_branch,
3125 CLK_INIT(gcc_sdcc2_apps_clk.c),
3126 },
3127};
3128
3129static struct local_vote_clk gcc_cpp_tbu_clk = {
3130 .cbcr_reg = CPP_TBU_CBCR,
3131 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3132 .en_mask = BIT(14),
3133 .base = &virt_bases[GCC_BASE],
3134 .c = {
3135 .dbg_name = "gcc_cpp_tbu_clk",
3136 .ops = &clk_ops_vote,
3137 CLK_INIT(gcc_cpp_tbu_clk.c),
3138 },
3139};
3140
3141static struct local_vote_clk gcc_gfx_tbu_clk = {
3142 .cbcr_reg = GFX_TBU_CBCR,
3143 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3144 .en_mask = BIT(3),
3145 .base = &virt_bases[GCC_BASE],
3146 .c = {
3147 .dbg_name = "gcc_gfx_tbu_clk",
3148 .ops = &clk_ops_vote,
3149 CLK_INIT(gcc_gfx_tbu_clk.c),
3150 },
3151};
3152
3153static struct local_vote_clk gcc_gfx_tcu_clk = {
3154 .cbcr_reg = GFX_TCU_CBCR,
3155 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3156 .en_mask = BIT(2),
3157 .base = &virt_bases[GCC_BASE],
3158 .c = {
3159 .dbg_name = "gcc_gfx_tcu_clk",
3160 .ops = &clk_ops_vote,
3161 CLK_INIT(gcc_gfx_tcu_clk.c),
3162 },
3163};
3164
3165static struct local_vote_clk gcc_apss_tcu_clk = {
3166 .cbcr_reg = APSS_TCU_CBCR,
3167 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3168 .en_mask = BIT(1),
3169 .base = &virt_bases[GCC_BASE],
3170 .c = {
3171 .dbg_name = "gcc_apss_tcu_clk",
3172 .ops = &clk_ops_vote,
3173 CLK_INIT(gcc_apss_tcu_clk.c),
3174 },
3175};
3176
3177static struct local_vote_clk gcc_gtcu_ahb_clk = {
3178 .cbcr_reg = GTCU_AHB_CBCR,
3179 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3180 .en_mask = BIT(13),
3181 .base = &virt_bases[GCC_BASE],
3182 .c = {
3183 .dbg_name = "gcc_gtcu_ahb_clk",
3184 .ops = &clk_ops_vote,
3185 CLK_INIT(gcc_gtcu_ahb_clk.c),
3186 },
3187};
3188
3189static struct local_vote_clk gcc_ipa_tbu_clk = {
3190 .cbcr_reg = IPA_TBU_CBCR,
3191 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3192 .en_mask = BIT(16),
3193 .base = &virt_bases[GCC_BASE],
3194 .c = {
3195 .dbg_name = "gcc_ipa_tbu_clk",
3196 .ops = &clk_ops_vote,
3197 CLK_INIT(gcc_ipa_tbu_clk.c),
3198 },
3199};
3200
3201static struct local_vote_clk gcc_jpeg_tbu_clk = {
3202 .cbcr_reg = JPEG_TBU_CBCR,
3203 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3204 .en_mask = BIT(10),
3205 .base = &virt_bases[GCC_BASE],
3206 .c = {
3207 .dbg_name = "gcc_jpeg_tbu_clk",
3208 .ops = &clk_ops_vote,
3209 CLK_INIT(gcc_jpeg_tbu_clk.c),
3210 },
3211};
3212
3213static struct local_vote_clk gcc_mdp_tbu_clk = {
3214 .cbcr_reg = MDP_TBU_CBCR,
3215 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3216 .en_mask = BIT(4),
3217 .base = &virt_bases[GCC_BASE],
3218 .c = {
3219 .dbg_name = "gcc_mdp_tbu_clk",
3220 .ops = &clk_ops_vote,
3221 CLK_INIT(gcc_mdp_tbu_clk.c),
3222 },
3223};
3224
3225static struct local_vote_clk gcc_smmu_cfg_clk = {
3226 .cbcr_reg = SMMU_CFG_CBCR,
3227 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3228 .en_mask = BIT(12),
3229 .base = &virt_bases[GCC_BASE],
3230 .c = {
3231 .dbg_name = "gcc_smmu_cfg_clk",
3232 .ops = &clk_ops_vote,
3233 CLK_INIT(gcc_smmu_cfg_clk.c),
3234 },
3235};
3236
3237static struct local_vote_clk gcc_venus_tbu_clk = {
3238 .cbcr_reg = VENUS_TBU_CBCR,
3239 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3240 .en_mask = BIT(5),
3241 .base = &virt_bases[GCC_BASE],
3242 .c = {
3243 .dbg_name = "gcc_venus_tbu_clk",
3244 .ops = &clk_ops_vote,
3245 CLK_INIT(gcc_venus_tbu_clk.c),
3246 },
3247};
3248
3249static struct local_vote_clk gcc_vfe1_tbu_clk = {
3250 .cbcr_reg = VFE1_TBU_CBCR,
3251 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3252 .en_mask = BIT(17),
3253 .base = &virt_bases[GCC_BASE],
3254 .c = {
3255 .dbg_name = "gcc_vfe1_tbu_clk",
3256 .ops = &clk_ops_vote,
3257 CLK_INIT(gcc_vfe1_tbu_clk.c),
3258 },
3259};
3260
3261static struct local_vote_clk gcc_vfe_tbu_clk = {
3262 .cbcr_reg = VFE_TBU_CBCR,
3263 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3264 .en_mask = BIT(9),
3265 .base = &virt_bases[GCC_BASE],
3266 .c = {
3267 .dbg_name = "gcc_vfe_tbu_clk",
3268 .ops = &clk_ops_vote,
3269 CLK_INIT(gcc_vfe_tbu_clk.c),
3270 },
3271};
3272
3273static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3274 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3275 .has_sibling = 1,
3276 .base = &virt_bases[GCC_BASE],
3277 .c = {
3278 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3279 .ops = &clk_ops_branch,
3280 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3281 },
3282};
3283
3284static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3285 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3286 .has_sibling = 1,
3287 .base = &virt_bases[GCC_BASE],
3288 .c = {
3289 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3290 .ops = &clk_ops_branch,
3291 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3292 },
3293};
3294
3295static struct branch_clk gcc_usb_fs_ahb_clk = {
3296 .cbcr_reg = USB_FS_AHB_CBCR,
3297 .has_sibling = 1,
3298 .base = &virt_bases[GCC_BASE],
3299 .c = {
3300 .dbg_name = "gcc_usb_fs_ahb_clk",
3301 .ops = &clk_ops_branch,
3302 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3303 },
3304};
3305
3306static struct branch_clk gcc_usb_fs_ic_clk = {
3307 .cbcr_reg = USB_FS_IC_CBCR,
3308 .has_sibling = 0,
3309 .base = &virt_bases[GCC_BASE],
3310 .c = {
3311 .dbg_name = "gcc_usb_fs_ic_clk",
3312 .parent = &usb_fs_ic_clk_src.c,
3313 .ops = &clk_ops_branch,
3314 CLK_INIT(gcc_usb_fs_ic_clk.c),
3315 },
3316};
3317
3318static struct branch_clk gcc_usb_fs_system_clk = {
3319 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3320 .bcr_reg = USB_FS_BCR,
3321 .has_sibling = 0,
3322 .base = &virt_bases[GCC_BASE],
3323 .c = {
3324 .dbg_name = "gcc_usb_fs_system_clk",
3325 .parent = &usb_fs_system_clk_src.c,
3326 .ops = &clk_ops_branch,
3327 CLK_INIT(gcc_usb_fs_system_clk.c),
3328 },
3329};
3330
3331static struct branch_clk gcc_usb_hs_ahb_clk = {
3332 .cbcr_reg = USB_HS_AHB_CBCR,
3333 .has_sibling = 1,
3334 .base = &virt_bases[GCC_BASE],
3335 .c = {
3336 .dbg_name = "gcc_usb_hs_ahb_clk",
3337 .ops = &clk_ops_branch,
3338 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3339 },
3340};
3341
3342static struct branch_clk gcc_usb_hs_system_clk = {
3343 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3344 .bcr_reg = USB_HS_BCR,
3345 .has_sibling = 0,
3346 .base = &virt_bases[GCC_BASE],
3347 .c = {
3348 .dbg_name = "gcc_usb_hs_system_clk",
3349 .parent = &usb_hs_system_clk_src.c,
3350 .ops = &clk_ops_branch,
3351 CLK_INIT(gcc_usb_hs_system_clk.c),
3352 },
3353};
3354
3355static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3356 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3357 .base = &virt_bases[GCC_BASE],
3358 .c = {
3359 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3360 .ops = &clk_ops_rst,
3361 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3362 },
3363};
3364
3365static struct reset_clk gcc_qusb2_phy_clk = {
3366 .reset_reg = QUSB2_PHY_BCR,
3367 .base = &virt_bases[GCC_BASE],
3368 .c = {
3369 .dbg_name = "gcc_qusb2_phy_clk",
3370 .ops = &clk_ops_rst,
3371 CLK_INIT(gcc_qusb2_phy_clk.c),
3372 },
3373};
3374
3375static struct branch_clk gcc_venus0_ahb_clk = {
3376 .cbcr_reg = VENUS0_AHB_CBCR,
3377 .has_sibling = 1,
3378 .base = &virt_bases[GCC_BASE],
3379 .c = {
3380 .dbg_name = "gcc_venus0_ahb_clk",
3381 .ops = &clk_ops_branch,
3382 CLK_INIT(gcc_venus0_ahb_clk.c),
3383 },
3384};
3385
3386static struct branch_clk gcc_venus0_axi_clk = {
3387 .cbcr_reg = VENUS0_AXI_CBCR,
3388 .has_sibling = 1,
3389 .base = &virt_bases[GCC_BASE],
3390 .c = {
3391 .dbg_name = "gcc_venus0_axi_clk",
3392 .ops = &clk_ops_branch,
3393 CLK_INIT(gcc_venus0_axi_clk.c),
3394 },
3395};
3396
3397static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3398 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3399 .has_sibling = 1,
3400 .base = &virt_bases[GCC_BASE],
3401 .c = {
3402 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3403 .parent = &vcodec0_clk_src.c,
3404 .ops = &clk_ops_branch,
3405 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3406 },
3407};
3408
3409static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3410 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3411 .has_sibling = 1,
3412 .base = &virt_bases[GCC_BASE],
3413 .c = {
3414 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3415 .parent = &vcodec0_clk_src.c,
3416 .ops = &clk_ops_branch,
3417 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3418 },
3419};
3420
3421static struct branch_clk gcc_venus0_vcodec0_clk = {
3422 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3423 .has_sibling = 0,
3424 .base = &virt_bases[GCC_BASE],
3425 .c = {
3426 .dbg_name = "gcc_venus0_vcodec0_clk",
3427 .parent = &vcodec0_clk_src.c,
3428 .ops = &clk_ops_branch,
3429 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3430 },
3431};
3432
3433static struct clk_ops clk_ops_debug_mux;
3434
3435static void __iomem *meas_base;
3436
3437static struct measure_clk apc0_m_clk = {
3438 .c = {
3439 .ops = &clk_ops_empty,
3440 .dbg_name = "apc0_m_clk",
3441 CLK_INIT(apc0_m_clk.c),
3442 },
3443};
3444
3445static struct measure_clk apc1_m_clk = {
3446 .c = {
3447 .ops = &clk_ops_empty,
3448 .dbg_name = "apc1_m_clk",
3449 CLK_INIT(apc1_m_clk.c),
3450 },
3451};
3452
3453static struct measure_clk cci_m_clk = {
3454 .c = {
3455 .ops = &clk_ops_empty,
3456 .dbg_name = "cci_m_clk",
3457 CLK_INIT(cci_m_clk.c),
3458 },
3459};
3460
3461static struct mux_clk apss_debug_ter_mux = {
3462 .ops = &mux_reg_ops,
3463 .mask = 0x3,
3464 .shift = 8,
3465 MUX_SRC_LIST(
3466 {&apc0_m_clk.c, 0},
3467 {&apc1_m_clk.c, 1},
3468 {&cci_m_clk.c, 2},
3469 ),
3470 .base = &meas_base,
3471 .c = {
3472 .dbg_name = "apss_debug_ter_mux",
3473 .ops = &clk_ops_gen_mux,
3474 CLK_INIT(apss_debug_ter_mux.c),
3475 },
3476};
3477
3478static struct mux_clk apss_debug_sec_mux = {
3479 .ops = &mux_reg_ops,
3480 .mask = 0x7,
3481 .shift = 12,
3482 MUX_SRC_LIST(
3483 {&apss_debug_ter_mux.c, 0},
3484 ),
3485 MUX_REC_SRC_LIST(
3486 &apss_debug_ter_mux.c,
3487 ),
3488 .base = &meas_base,
3489 .c = {
3490 .dbg_name = "apss_debug_sec_mux",
3491 .ops = &clk_ops_gen_mux,
3492 CLK_INIT(apss_debug_sec_mux.c),
3493 },
3494};
3495
3496static struct mux_clk apss_debug_pri_mux = {
3497 .ops = &mux_reg_ops,
3498 .mask = 0x3,
3499 .shift = 16,
3500 MUX_SRC_LIST(
3501 {&apss_debug_sec_mux.c, 0},
3502 ),
3503 MUX_REC_SRC_LIST(
3504 &apss_debug_sec_mux.c,
3505 ),
3506 .base = &meas_base,
3507 .c = {
3508 .dbg_name = "apss_debug_pri_mux",
3509 .ops = &clk_ops_gen_mux,
3510 CLK_INIT(apss_debug_pri_mux.c),
3511 },
3512};
3513
3514static struct measure_clk_data debug_mux_priv = {
3515 .cxo = &xo_clk_src.c,
3516 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3517 .plltest_val = 0x51A00,
3518 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3519 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3520 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3521 .base = &virt_bases[GCC_BASE],
3522};
3523
3524static struct mux_clk gcc_debug_mux = {
3525 .priv = &debug_mux_priv,
3526 .ops = &mux_reg_ops,
3527 .offset = GCC_DEBUG_CLK_CTL,
3528 .mask = 0x1FF,
3529 .en_offset = GCC_DEBUG_CLK_CTL,
3530 .en_mask = BIT(16),
3531 .base = &virt_bases[GCC_BASE],
3532 MUX_REC_SRC_LIST(
3533 &apss_debug_pri_mux.c,
3534 ),
3535 MUX_SRC_LIST(
3536 { &apss_debug_pri_mux.c, 0x016A},
3537 { &snoc_clk.c, 0x0000 },
3538 { &sysmmnoc_clk.c, 0x0001 },
3539 { &pnoc_clk.c, 0x0008 },
3540 { &bimc_clk.c, 0x0154 },
3541 { &gcc_gp1_clk.c, 0x0010 },
3542 { &gcc_gp2_clk.c, 0x0011 },
3543 { &gcc_gp3_clk.c, 0x0012 },
3544 { &gcc_bimc_gfx_clk.c, 0x002d },
3545 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3546 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3547 { &gcc_apss_tcu_clk.c, 0x0050 },
3548 { &gcc_mdp_tbu_clk.c, 0x0051 },
3549 { &gcc_gfx_tbu_clk.c, 0x0052 },
3550 { &gcc_gfx_tcu_clk.c, 0x0053 },
3551 { &gcc_venus_tbu_clk.c, 0x0054 },
3552 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3553 { &gcc_vfe_tbu_clk.c, 0x005a },
3554 { &gcc_smmu_cfg_clk.c, 0x005b },
3555 { &gcc_jpeg_tbu_clk.c, 0x005c },
3556 { &gcc_usb_hs_system_clk.c, 0x0060 },
3557 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3558 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3559 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3560 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3561 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3562 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3563 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3564 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3565 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3566 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3567 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3568 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3569 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3570 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3571 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3572 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3573 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3574 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3575 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3576 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3577 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3578 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3579 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3580 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3581 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3582 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3583 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3584 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3585 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3586 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3587 { &gcc_camss_ahb_clk.c, 0x00a8 },
3588 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3589 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3590 { &gcc_camss_gp0_clk.c, 0x00ab },
3591 { &gcc_camss_gp1_clk.c, 0x00ac },
3592 { &gcc_camss_mclk0_clk.c, 0x00ad },
3593 { &gcc_camss_mclk1_clk.c, 0x00ae },
3594 { &gcc_camss_cci_clk.c, 0x00af },
3595 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3596 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3597 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3598 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3599 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3600 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3601 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3602 { &gcc_camss_cpp_clk.c, 0x00b9 },
3603 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3604 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3605 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3606 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3607 { &gcc_camss_csi0_clk.c, 0x00c0 },
3608 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3609 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3610 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3611 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3612 { &gcc_camss_csi1_clk.c, 0x00c5 },
3613 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3614 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3615 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3616 { &gcc_pdm2_clk.c, 0x00d2 },
3617 { &gcc_prng_ahb_clk.c, 0x00d8 },
3618 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3619 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3620 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3621 { &gcc_camss_csi2_clk.c, 0x00e3 },
3622 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3623 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3624 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3625 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3626 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3627 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3628 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3629 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3630 { &gcc_crypto_clk.c, 0x0138 },
3631 { &gcc_crypto_axi_clk.c, 0x0139 },
3632 { &gcc_crypto_ahb_clk.c, 0x013a },
3633 { &gcc_bimc_gpu_clk.c, 0x0157 },
3634 { &gcc_ipa_tbu_clk.c, 0x0198 },
3635 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3636 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3637 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3638 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3639 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3640 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3641 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3642 { &gcc_camss_mclk2_clk.c, 0x01bd },
3643 { &gcc_oxili_timer_clk.c, 0x01e9 },
3644 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3645 { &gcc_oxili_ahb_clk.c, 0x01eb },
3646 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3647 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3648 { &gcc_venus0_axi_clk.c, 0x01f2 },
3649 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3650 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3651 { &gcc_mdss_axi_clk.c, 0x01f7 },
3652 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3653 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3654 { &gcc_mdss_vsync_clk.c, 0x01fb },
3655 { &gcc_mdss_byte0_clk.c, 0x01fc },
3656 { &gcc_mdss_esc0_clk.c, 0x01fd },
3657 { &wcnss_m_clk.c, 0x0ec },
3658 ),
3659 .c = {
3660 .dbg_name = "gcc_debug_mux",
3661 .ops = &clk_ops_debug_mux,
3662 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3663 CLK_INIT(gcc_debug_mux.c),
3664 },
3665};
3666
3667static struct mux_clk gcc_debug_mux_8937 = {
3668 .priv = &debug_mux_priv,
3669 .ops = &mux_reg_ops,
3670 .offset = GCC_DEBUG_CLK_CTL,
3671 .mask = 0x1FF,
3672 .en_offset = GCC_DEBUG_CLK_CTL,
3673 .en_mask = BIT(16),
3674 .base = &virt_bases[GCC_BASE],
3675 MUX_REC_SRC_LIST(
3676 &apss_debug_pri_mux.c,
3677 ),
3678 MUX_SRC_LIST(
3679 { &apss_debug_pri_mux.c, 0x016A},
3680 { &snoc_clk.c, 0x0000 },
3681 { &sysmmnoc_clk.c, 0x0001 },
3682 { &pnoc_clk.c, 0x0008 },
3683 { &bimc_clk.c, 0x015A },
3684 { &ipa_clk.c, 0x1B0 },
3685 { &gcc_gp1_clk.c, 0x0010 },
3686 { &gcc_gp2_clk.c, 0x0011 },
3687 { &gcc_gp3_clk.c, 0x0012 },
3688 { &gcc_bimc_gfx_clk.c, 0x002d },
3689 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3690 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3691 { &gcc_qdss_dap_clk.c, 0x0049 },
3692 { &gcc_apss_tcu_clk.c, 0x0050 },
3693 { &gcc_mdp_tbu_clk.c, 0x0051 },
3694 { &gcc_gfx_tbu_clk.c, 0x0052 },
3695 { &gcc_gfx_tcu_clk.c, 0x0053 },
3696 { &gcc_venus_tbu_clk.c, 0x0054 },
3697 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3698 { &gcc_vfe_tbu_clk.c, 0x005a },
3699 { &gcc_smmu_cfg_clk.c, 0x005b },
3700 { &gcc_jpeg_tbu_clk.c, 0x005c },
3701 { &gcc_usb_hs_system_clk.c, 0x0060 },
3702 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3703 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3704 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3705 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3706 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3707 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3708 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3709 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3710 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3711 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3712 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3713 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3714 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3715 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3716 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3717 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3718 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3719 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3720 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3721 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3722 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3723 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3724 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3725 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3726 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3727 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3728 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3729 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3730 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3731 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3732 { &gcc_camss_ahb_clk.c, 0x00a8 },
3733 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3734 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3735 { &gcc_camss_gp0_clk.c, 0x00ab },
3736 { &gcc_camss_gp1_clk.c, 0x00ac },
3737 { &gcc_camss_mclk0_clk.c, 0x00ad },
3738 { &gcc_camss_mclk1_clk.c, 0x00ae },
3739 { &gcc_camss_cci_clk.c, 0x00af },
3740 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3741 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3742 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3743 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3744 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3745 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3746 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3747 { &gcc_camss_cpp_clk.c, 0x00b9 },
3748 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3749 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3750 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3751 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3752 { &gcc_camss_csi0_clk.c, 0x00c0 },
3753 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3754 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3755 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3756 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3757 { &gcc_camss_csi1_clk.c, 0x00c5 },
3758 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3759 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3760 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3761 { &gcc_pdm2_clk.c, 0x00d2 },
3762 { &gcc_prng_ahb_clk.c, 0x00d8 },
3763 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3764 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3765 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3766 { &gcc_camss_csi2_clk.c, 0x00e3 },
3767 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3768 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3769 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3770 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3771 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3772 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3773 { &gcc_crypto_clk.c, 0x0138 },
3774 { &gcc_crypto_axi_clk.c, 0x0139 },
3775 { &gcc_crypto_ahb_clk.c, 0x013a },
3776 { &gcc_bimc_gpu_clk.c, 0x0157 },
3777 { &gcc_ipa_tbu_clk.c, 0x0198 },
3778 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3779 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3780 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3781 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3782 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3783 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3784 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3785 { &gcc_dcc_clk.c, 0x01b9 },
3786 { &gcc_camss_mclk2_clk.c, 0x01bd },
3787 { &gcc_oxili_timer_clk.c, 0x01e9 },
3788 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3789 { &gcc_oxili_aon_clk.c, 0x00ee },
3790 { &gcc_oxili_ahb_clk.c, 0x01eb },
3791 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3792 { &gcc_venus0_axi_clk.c, 0x01f2 },
3793 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3794 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3795 { &gcc_mdss_axi_clk.c, 0x01f7 },
3796 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3797 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3798 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3799 { &gcc_mdss_vsync_clk.c, 0x01fb },
3800 { &gcc_mdss_byte0_clk.c, 0x01fc },
3801 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3802 { &gcc_mdss_esc0_clk.c, 0x01fd },
3803 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3804 { &wcnss_m_clk.c, 0x0ec },
3805 ),
3806 .c = {
3807 .dbg_name = "gcc_debug_mux_8937",
3808 .ops = &clk_ops_debug_mux,
3809 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3810 CLK_INIT(gcc_debug_mux_8937.c),
3811 },
3812};
3813
3814/* Clock lookup */
3815static struct clk_lookup msm_clocks_lookup_common[] = {
3816 /* RPM clocks */
3817 CLK_LIST(xo_clk_src),
3818 CLK_LIST(xo_a_clk_src),
3819 CLK_LIST(xo_otg_clk),
3820 CLK_LIST(xo_lpm_clk),
3821 CLK_LIST(xo_pil_mss_clk),
3822 CLK_LIST(xo_pil_pronto_clk),
3823 CLK_LIST(xo_wlan_clk),
3824 CLK_LIST(xo_pil_lpass_clk),
3825
3826 CLK_LIST(sysmmnoc_msmbus_clk),
3827 CLK_LIST(snoc_msmbus_clk),
3828 CLK_LIST(snoc_msmbus_a_clk),
3829 CLK_LIST(sysmmnoc_msmbus_a_clk),
3830 CLK_LIST(pnoc_msmbus_clk),
3831 CLK_LIST(pnoc_msmbus_a_clk),
3832 CLK_LIST(bimc_msmbus_clk),
3833 CLK_LIST(bimc_msmbus_a_clk),
3834 CLK_LIST(pnoc_keepalive_a_clk),
3835
3836 CLK_LIST(pnoc_usb_a_clk),
3837 CLK_LIST(snoc_usb_a_clk),
3838 CLK_LIST(bimc_usb_a_clk),
3839 CLK_LIST(pnoc_usb_clk),
3840 CLK_LIST(snoc_usb_clk),
3841 CLK_LIST(bimc_usb_clk),
3842
3843 CLK_LIST(snoc_wcnss_a_clk),
3844 CLK_LIST(bimc_wcnss_a_clk),
3845
3846 CLK_LIST(qdss_clk),
3847 CLK_LIST(qdss_a_clk),
3848
3849 CLK_LIST(snoc_clk),
3850 CLK_LIST(sysmmnoc_clk),
3851 CLK_LIST(pnoc_clk),
3852 CLK_LIST(bimc_clk),
3853 CLK_LIST(snoc_a_clk),
3854 CLK_LIST(sysmmnoc_a_clk),
3855 CLK_LIST(pnoc_a_clk),
3856 CLK_LIST(bimc_a_clk),
3857
3858 CLK_LIST(bb_clk1),
3859 CLK_LIST(bb_clk1_a),
3860 CLK_LIST(bb_clk2),
3861 CLK_LIST(bb_clk2_a),
3862 CLK_LIST(rf_clk2),
3863 CLK_LIST(rf_clk2_a),
3864 CLK_LIST(div_clk2),
3865 CLK_LIST(div_clk2_a),
3866
3867 CLK_LIST(bb_clk1_pin),
3868 CLK_LIST(bb_clk1_a_pin),
3869 CLK_LIST(bb_clk2_pin),
3870 CLK_LIST(bb_clk2_a_pin),
3871
3872 CLK_LIST(gpll0_clk_src),
3873 CLK_LIST(gpll0_ao_clk_src),
3874 CLK_LIST(gpll6_clk_src),
3875 CLK_LIST(gpll4_clk_src),
3876 CLK_LIST(gpll3_clk_src),
3877 CLK_LIST(a53ss_c1_pll),
3878 CLK_LIST(gcc_blsp1_ahb_clk),
3879 CLK_LIST(gcc_blsp2_ahb_clk),
3880 CLK_LIST(gcc_boot_rom_ahb_clk),
3881 CLK_LIST(gcc_crypto_ahb_clk),
3882 CLK_LIST(gcc_crypto_axi_clk),
3883 CLK_LIST(gcc_crypto_clk),
3884 CLK_LIST(gcc_prng_ahb_clk),
3885 CLK_LIST(gcc_cpp_tbu_clk),
3886 CLK_LIST(gcc_apss_tcu_clk),
3887 CLK_LIST(gcc_jpeg_tbu_clk),
3888 CLK_LIST(gcc_mdp_tbu_clk),
3889 CLK_LIST(gcc_smmu_cfg_clk),
3890 CLK_LIST(gcc_venus_tbu_clk),
3891 CLK_LIST(gcc_vfe1_tbu_clk),
3892 CLK_LIST(gcc_vfe_tbu_clk),
3893 CLK_LIST(camss_top_ahb_clk_src),
3894 CLK_LIST(apss_ahb_clk_src),
3895 CLK_LIST(csi0_clk_src),
3896 CLK_LIST(csi1_clk_src),
3897 CLK_LIST(csi2_clk_src),
3898 CLK_LIST(vcodec0_clk_src),
3899 CLK_LIST(vfe0_clk_src),
3900 CLK_LIST(vfe1_clk_src),
3901 CLK_LIST(gfx3d_clk_src),
3902 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3903 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3904 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3905 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3906 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3907 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3908 CLK_LIST(blsp1_uart1_apps_clk_src),
3909 CLK_LIST(blsp1_uart2_apps_clk_src),
3910 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3911 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3912 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3913 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3914 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3915 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3916 CLK_LIST(blsp2_uart1_apps_clk_src),
3917 CLK_LIST(blsp2_uart2_apps_clk_src),
3918 CLK_LIST(cci_clk_src),
3919 CLK_LIST(cpp_clk_src),
3920 CLK_LIST(camss_gp0_clk_src),
3921 CLK_LIST(camss_gp1_clk_src),
3922 CLK_LIST(jpeg0_clk_src),
3923 CLK_LIST(mclk0_clk_src),
3924 CLK_LIST(mclk1_clk_src),
3925 CLK_LIST(mclk2_clk_src),
3926 CLK_LIST(csi0phytimer_clk_src),
3927 CLK_LIST(csi1phytimer_clk_src),
3928 CLK_LIST(crypto_clk_src),
3929 CLK_LIST(gp1_clk_src),
3930 CLK_LIST(gp2_clk_src),
3931 CLK_LIST(gp3_clk_src),
3932 CLK_LIST(esc0_clk_src),
3933 CLK_LIST(mdp_clk_src),
3934 CLK_LIST(vsync_clk_src),
3935 CLK_LIST(pdm2_clk_src),
3936 CLK_LIST(sdcc1_apps_clk_src),
3937 CLK_LIST(sdcc1_ice_core_clk_src),
3938 CLK_LIST(sdcc2_apps_clk_src),
3939 CLK_LIST(usb_hs_system_clk_src),
3940 CLK_LIST(gcc_bimc_gpu_clk),
3941 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3942 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3943 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3944 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3945 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3946 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3947 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3948 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3949 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3950 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3951 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3952 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3953 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3954 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3955 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3956 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3957 CLK_LIST(gcc_camss_cci_ahb_clk),
3958 CLK_LIST(gcc_camss_cci_clk),
3959 CLK_LIST(gcc_camss_cpp_ahb_clk),
3960 CLK_LIST(gcc_camss_cpp_axi_clk),
3961 CLK_LIST(gcc_camss_cpp_clk),
3962 CLK_LIST(gcc_camss_csi0_ahb_clk),
3963 CLK_LIST(gcc_camss_csi0_clk),
3964 CLK_LIST(gcc_camss_csi0phy_clk),
3965 CLK_LIST(gcc_camss_csi0pix_clk),
3966 CLK_LIST(gcc_camss_csi0rdi_clk),
3967 CLK_LIST(gcc_camss_csi1_ahb_clk),
3968 CLK_LIST(gcc_camss_csi1_clk),
3969 CLK_LIST(gcc_camss_csi1phy_clk),
3970 CLK_LIST(gcc_camss_csi1pix_clk),
3971 CLK_LIST(gcc_camss_csi1rdi_clk),
3972 CLK_LIST(gcc_camss_csi2_ahb_clk),
3973 CLK_LIST(gcc_camss_csi2_clk),
3974 CLK_LIST(gcc_camss_csi2phy_clk),
3975 CLK_LIST(gcc_camss_csi2pix_clk),
3976 CLK_LIST(gcc_camss_csi2rdi_clk),
3977 CLK_LIST(gcc_camss_csi_vfe0_clk),
3978 CLK_LIST(gcc_camss_csi_vfe1_clk),
3979 CLK_LIST(gcc_camss_gp0_clk),
3980 CLK_LIST(gcc_camss_gp1_clk),
3981 CLK_LIST(gcc_camss_ispif_ahb_clk),
3982 CLK_LIST(gcc_camss_jpeg0_clk),
3983 CLK_LIST(gcc_camss_jpeg_ahb_clk),
3984 CLK_LIST(gcc_camss_jpeg_axi_clk),
3985 CLK_LIST(gcc_camss_mclk0_clk),
3986 CLK_LIST(gcc_camss_mclk1_clk),
3987 CLK_LIST(gcc_camss_mclk2_clk),
3988 CLK_LIST(gcc_camss_micro_ahb_clk),
3989 CLK_LIST(gcc_camss_csi0phytimer_clk),
3990 CLK_LIST(gcc_camss_csi1phytimer_clk),
3991 CLK_LIST(gcc_camss_ahb_clk),
3992 CLK_LIST(gcc_camss_top_ahb_clk),
3993 CLK_LIST(gcc_camss_vfe0_clk),
3994 CLK_LIST(gcc_camss_vfe_ahb_clk),
3995 CLK_LIST(gcc_camss_vfe_axi_clk),
3996 CLK_LIST(gcc_camss_vfe1_ahb_clk),
3997 CLK_LIST(gcc_camss_vfe1_axi_clk),
3998 CLK_LIST(gcc_camss_vfe1_clk),
3999 CLK_LIST(gcc_gp1_clk),
4000 CLK_LIST(gcc_gp2_clk),
4001 CLK_LIST(gcc_gp3_clk),
4002 CLK_LIST(gcc_mdss_ahb_clk),
4003 CLK_LIST(gcc_mdss_axi_clk),
4004 CLK_LIST(gcc_mdss_esc0_clk),
4005 CLK_LIST(gcc_mdss_mdp_clk),
4006 CLK_LIST(gcc_mdss_vsync_clk),
4007 CLK_LIST(gcc_mss_cfg_ahb_clk),
4008 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
4009 CLK_LIST(gcc_bimc_gfx_clk),
4010 CLK_LIST(gcc_oxili_ahb_clk),
4011 CLK_LIST(gcc_oxili_gfx3d_clk),
4012 CLK_LIST(gcc_pdm2_clk),
4013 CLK_LIST(gcc_pdm_ahb_clk),
4014 CLK_LIST(gcc_sdcc1_ahb_clk),
4015 CLK_LIST(gcc_sdcc1_apps_clk),
4016 CLK_LIST(gcc_sdcc1_ice_core_clk),
4017 CLK_LIST(gcc_sdcc2_ahb_clk),
4018 CLK_LIST(gcc_sdcc2_apps_clk),
4019 CLK_LIST(gcc_usb2a_phy_sleep_clk),
4020 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
4021 CLK_LIST(gcc_usb_hs_ahb_clk),
4022 CLK_LIST(gcc_usb_hs_system_clk),
4023 CLK_LIST(gcc_venus0_ahb_clk),
4024 CLK_LIST(gcc_venus0_axi_clk),
4025 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
4026 CLK_LIST(gcc_venus0_vcodec0_clk),
4027
4028 /* Reset clks */
4029 CLK_LIST(gcc_usb2_hs_phy_only_clk),
4030 CLK_LIST(gcc_qusb2_phy_clk),
4031
4032 /* WCNSS Debug */
4033 CLK_LIST(wcnss_m_clk),
4034};
4035
4036static struct clk_lookup msm_clocks_lookup_8952[] = {
4037 CLK_LIST(a53ss_c0_pll),
4038 CLK_LIST(a53ss_cci_pll),
4039 CLK_LIST(ipa_clk),
4040 CLK_LIST(ipa_a_clk),
4041 CLK_LIST(gpll0_clk_src_8952),
4042 CLK_LIST(gpll0_ao_clk_src_8952),
4043 CLK_LIST(gcc_oxili_gmem_clk),
4044 CLK_LIST(usb_fs_ic_clk_src),
4045 CLK_LIST(gcc_usb_fs_ic_clk),
4046 CLK_LIST(usb_fs_system_clk_src),
4047 CLK_LIST(gcc_usb_fs_system_clk),
4048 CLK_LIST(gcc_gfx_tcu_clk),
4049 CLK_LIST(gcc_gfx_tbu_clk),
4050 CLK_LIST(gcc_gtcu_ahb_clk),
4051 CLK_LIST(gcc_ipa_tbu_clk),
4052 CLK_LIST(gcc_usb_fs_ahb_clk),
4053 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4054 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4055 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4056 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4057 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4058 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4059 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4060 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4061 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4062 CLK_LIST(gcc_oxili_timer_clk),
4063};
4064
4065static struct clk_lookup msm_clocks_lookup_8937[] = {
4066 CLK_LIST(gpll0_clk_src_8937),
4067 CLK_LIST(gpll0_ao_clk_src_8937),
4068 CLK_LIST(gpll0_sleep_clk_src),
4069 CLK_LIST(a53ss_c0_pll),
4070 CLK_LIST(esc1_clk_src),
4071 CLK_LIST(gcc_mdss_esc1_clk),
4072 CLK_LIST(gcc_dcc_clk),
4073 CLK_LIST(gcc_oxili_aon_clk),
4074 CLK_LIST(gcc_qdss_dap_clk),
4075 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4076 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4077 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4078 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4079 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4080 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4081 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4082 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4083 CLK_LIST(gcc_oxili_timer_clk),
4084};
4085
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4086static struct clk_lookup msm_clocks_lookup_sdm429[] = {
4087 CLK_LIST(gpll0_clk_src_8937),
4088 CLK_LIST(gpll0_ao_clk_src_8937),
4089 CLK_LIST(gpll0_sleep_clk_src),
4090 CLK_LIST(esc1_clk_src),
4091 CLK_LIST(gcc_mdss_esc1_clk),
4092 CLK_LIST(gcc_dcc_clk),
4093 CLK_LIST(gcc_oxili_aon_clk),
4094 CLK_LIST(gcc_qdss_dap_clk),
4095 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4096 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4097 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4098 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4099 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4100 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4101 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4102 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4103 CLK_LIST(gcc_oxili_timer_clk),
4104};
4105
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4106static struct clk_lookup msm_clocks_lookup_8917[] = {
4107 CLK_LIST(gpll0_clk_src_8937),
4108 CLK_LIST(gpll0_ao_clk_src_8937),
4109 CLK_LIST(gpll0_sleep_clk_src),
4110 CLK_LIST(bimc_gpu_clk),
4111 CLK_LIST(bimc_gpu_a_clk),
4112 CLK_LIST(gcc_dcc_clk),
4113 CLK_LIST(gcc_qdss_dap_clk),
4114 CLK_LIST(gcc_gfx_tcu_clk),
4115 CLK_LIST(gcc_gfx_tbu_clk),
4116 CLK_LIST(gcc_gtcu_ahb_clk),
4117};
4118
4119static struct clk_lookup msm_clocks_lookup_8920[] = {
4120 CLK_LIST(gpll0_clk_src_8937),
4121 CLK_LIST(gpll0_ao_clk_src_8937),
4122 CLK_LIST(gpll0_sleep_clk_src),
4123 CLK_LIST(bimc_gpu_clk),
4124 CLK_LIST(bimc_gpu_a_clk),
4125 CLK_LIST(gcc_dcc_clk),
4126 CLK_LIST(gcc_qdss_dap_clk),
4127 CLK_LIST(gcc_gfx_tcu_clk),
4128 CLK_LIST(gcc_gfx_tbu_clk),
4129 CLK_LIST(gcc_gtcu_ahb_clk),
4130 CLK_LIST(ipa_clk),
4131 CLK_LIST(ipa_a_clk),
4132 CLK_LIST(gcc_ipa_tbu_clk),
4133};
4134
4135static struct clk_lookup msm_clocks_lookup_8940[] = {
4136 CLK_LIST(gpll0_clk_src_8937),
4137 CLK_LIST(gpll0_ao_clk_src_8937),
4138 CLK_LIST(gpll0_sleep_clk_src),
4139 CLK_LIST(a53ss_c0_pll),
4140 CLK_LIST(esc1_clk_src),
4141 CLK_LIST(gcc_mdss_esc1_clk),
4142 CLK_LIST(gcc_dcc_clk),
4143 CLK_LIST(gcc_oxili_aon_clk),
4144 CLK_LIST(gcc_qdss_dap_clk),
4145 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4146 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4147 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4148 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4149 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4150 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4151 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4152 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4153 CLK_LIST(gcc_oxili_timer_clk),
4154 CLK_LIST(ipa_clk),
4155 CLK_LIST(ipa_a_clk),
4156 CLK_LIST(gcc_ipa_tbu_clk),
4157};
4158
4159/* Please note that the order of reg-names is important */
4160static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4161{
4162 int i, count;
4163 const char *str;
4164 struct resource *res;
4165 struct device *dev = &pdev->dev;
4166
4167 count = of_property_count_strings(dev->of_node, "reg-names");
4168 if (count < nbases) {
4169 dev_err(dev, "missing reg-names property, expected %d strings\n",
4170 nbases);
4171 return -EINVAL;
4172 }
4173
4174 for (i = 0; i < nbases; i++) {
4175 of_property_read_string_index(dev->of_node, "reg-names", i,
4176 &str);
4177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4178 if (!res) {
4179 dev_err(dev, "Unable to retrieve register base.\n");
4180 return -ENOMEM;
4181 }
4182
4183 virt_bases[i] = devm_ioremap(dev, res->start,
4184 resource_size(res));
4185 if (!virt_bases[i]) {
4186 dev_err(dev, "Failed to map in CC registers.\n");
4187 return -ENOMEM;
4188 }
4189 }
4190
4191 return 0;
4192}
4193
4194static const struct msm_reset_map gcc_8952_resets[] = {
4195 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4196 [GCC_USB_FS_BCR] = {0x3F000},
4197 [GCC_USB_HS_BCR] = {0x41000},
4198 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4199 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4200};
4201
4202static void override_for_8917(int speed_bin)
4203{
4204 gpll3_clk_src.c.rate = 930000000;
4205
4206 OVERRIDE_FMAX3(csi0,
4207 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4208 /* Frequency Table same as 8937 */
4209 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4210 OVERRIDE_FMAX3(csi1,
4211 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4212 /* Frequency Table same as 8937 */
4213 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4214 OVERRIDE_FMAX3(csi2,
4215 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4216 /* Frequency Table same as 8937 */
4217 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4218
4219 OVERRIDE_FMAX5(vfe0,
4220 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4221 NOM_PLUS, 329140000, HIGH, 360000000);
4222 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4223 OVERRIDE_FMAX5(vfe1,
4224 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4225 NOM_PLUS, 329140000, HIGH, 360000000);
4226 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4227 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4228 OVERRIDE_FMAX5(vcodec0,
4229 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4230 NOM_PLUS, 329140000, HIGH, 360000000);
4231 OVERRIDE_FMAX4(cpp,
4232 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4233 NOM_PLUS, 360000000);
4234 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4235 OVERRIDE_FMAX5(jpeg0,
4236 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4237 NOM_PLUS, 308570000, HIGH, 320000000);
4238 /* Frequency Table same as 8937 */
4239 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4240
4241 if (speed_bin) {
4242 OVERRIDE_FMAX5(gfx3d,
4243 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4244 NOM_PLUS, 523200000, HIGH, 650000000);
4245 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4246 } else {
4247 OVERRIDE_FMAX5(gfx3d,
4248 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4249 NOM_PLUS, 523200000, HIGH, 598000000);
4250 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4251 }
4252
4253 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4254
4255 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4256 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4257 NOMINAL, 266670000);
4258 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4259 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4260 NOMINAL, 266670000);
4261 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4262 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4263 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4264
4265 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4266 /* Frequency Table same as 8937 */
4267 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4268 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4269
4270 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4271 /* Frequency Table same as 8937 */
4272 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4273 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4274
4275 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4276 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4277 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4278 HIGH, 177780000);
4279}
4280
4281static void override_for_8937(int speed_bin)
4282{
4283 gpll3_clk_src.c.rate = 900000000;
4284 gpll3_clk_src.vco_tbl = p_vco_8937;
4285 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4286 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4287
4288 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4289 OVERRIDE_FMAX3(csi0,
4290 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4291 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4292 OVERRIDE_FMAX3(csi1,
4293 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4294 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4295 OVERRIDE_FMAX3(csi2,
4296 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4297 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4298 OVERRIDE_FMAX4(vfe0,
4299 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4300 NOM_PLUS, 432000000);
4301 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4302 OVERRIDE_FMAX4(vfe1,
4303 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4304 NOM_PLUS, 432000000);
4305 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4306
4307 if (speed_bin) {
4308 OVERRIDE_FMAX6(gfx3d,
4309 LOWER, 216000000, LOW, 300000000,
4310 NOMINAL, 375000000, NOM_PLUS, 400000000,
4311 HIGH, 450000000, SUPER_TUR, 475000000);
4312 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4313 } else {
4314 OVERRIDE_FMAX5(gfx3d,
4315 LOWER, 216000000, LOW, 300000000,
4316 NOMINAL, 375000000, NOM_PLUS, 400000000,
4317 HIGH, 450000000);
4318 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4319 }
4320
4321 OVERRIDE_FMAX5(cpp,
4322 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4323 NOM_PLUS, 342860000, HIGH, 360000000);
4324 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4325 OVERRIDE_FMAX5(jpeg0,
4326 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4327 NOM_PLUS, 308570000, HIGH, 320000000);
4328 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4329 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4330 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4331 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4332 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4333 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4334 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4335 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4336 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4337 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4338 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4339 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4340 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4341 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4342 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4343 OVERRIDE_FMAX5(vcodec0,
4344 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4345 NOM_PLUS, 320000000, HIGH, 360000000);
4346 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4347 NOMINAL, 400000000);
4348}
4349
4350static void get_speed_bin(struct platform_device *pdev, int *bin)
4351{
4352 struct resource *res;
4353 void __iomem *base;
4354 u32 config_efuse;
4355
4356 *bin = 0;
4357
4358 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4359 if (!res) {
4360 dev_info(&pdev->dev,
4361 "No GPU speed binning available. Defaulting to 0.\n");
4362 return;
4363 }
4364
4365 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4366 if (!base) {
4367 dev_warn(&pdev->dev,
4368 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4369 return;
4370 }
4371
4372 config_efuse = readl_relaxed(base);
4373 devm_iounmap(&pdev->dev, base);
4374 *bin = (config_efuse >> 31) & 0x1;
4375
4376 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4377}
4378
4379static int msm_gcc_probe(struct platform_device *pdev)
4380{
4381 struct resource *res;
4382 int ret;
4383 int speed_bin;
4384 u32 regval, nbases = N_BASES;
4385 bool compat_bin = false;
4386 bool compat_bin2 = false;
4387 bool compat_bin3 = false;
4388 bool compat_bin4 = false;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4389 bool compat_bin5 = false;
4390 bool compat_bin6 = false;
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4391
4392 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4393 "qcom,gcc-8937");
4394
4395 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4396 "qcom,gcc-8917");
4397
4398 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4399 "qcom,gcc-8940");
4400
4401 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4402 "qcom,gcc-8920");
4403
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4404 compat_bin5 = of_device_is_compatible(pdev->dev.of_node,
4405 "qcom,gcc-sdm429");
4406
4407 compat_bin6 = of_device_is_compatible(pdev->dev.of_node,
4408 "qcom,gcc-sdm439");
4409
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4410 ret = vote_bimc(&bimc_clk, INT_MAX);
4411 if (ret < 0)
4412 return ret;
4413
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4414 if (compat_bin2 || compat_bin4 || compat_bin5)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4415 nbases = APCS_C0_PLL_BASE;
4416
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]4417 if (compat_bin5 || compat_bin6) {
4418 a53ss_c0_pll.c.ops = &clk_ops_acpu_pll;
4419 a53ss_c1_pll.c.ops = &clk_ops_acpu_pll;
4420 }
4421
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4422 ret = get_mmio_addr(pdev, nbases);
4423 if (ret)
4424 return ret;
4425
4426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4427 if (!res) {
4428 dev_err(&pdev->dev, "Register base not defined\n");
4429 return -ENOMEM;
4430 }
4431
4432 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4433 resource_size(res));
4434 if (!virt_bases[GCC_BASE]) {
4435 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4436 return -ENOMEM;
4437 }
4438
4439 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4440 if (IS_ERR(vdd_dig.regulator[0])) {
4441 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4442 dev_err(&pdev->dev,
4443 "Unable to get vdd_dig regulator!!!\n");
4444 return PTR_ERR(vdd_dig.regulator[0]);
4445 }
4446
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4447 if (!compat_bin2 && !compat_bin4 && !compat_bin5) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4448 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4449 "vdd_sr2_pll");
4450 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4451 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4452 dev_err(&pdev->dev,
4453 "Unable to get vdd_sr2_pll regulator!!!\n");
4454 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4455 }
4456
4457 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4458 "vdd_sr2_dig");
4459 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4460 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4461 dev_err(&pdev->dev,
4462 "Unable to get vdd_sr2_dig regulator!!!\n");
4463 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4464 }
4465 }
4466
4467 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4468 "vdd_hf_pll");
4469 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4470 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4471 dev_err(&pdev->dev,
4472 "Unable to get vdd_sr2_pll regulator!!!\n");
4473 return PTR_ERR(vdd_hf_pll.regulator[0]);
4474 }
4475
4476 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4477 "vdd_hf_dig");
4478 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4479 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4480 dev_err(&pdev->dev,
4481 "Unable to get vdd_hf_dig regulator!!!\n");
4482 return PTR_ERR(vdd_hf_pll.regulator[1]);
4483 }
4484
4485 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4486 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4487 regval |= BIT(0);
4488 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4489
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4490 if (compat_bin || compat_bin3 || compat_bin5 || compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4491 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4492 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4493 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4494 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4495 regval &= ~BIT(0);
4496 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4497
4498 if (compat_bin5 || compat_bin6)
4499 speed_bin = 0;
4500 else
4501 get_speed_bin(pdev, &speed_bin);
4502
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4503 override_for_8937(speed_bin);
4504
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4505 if (compat_bin5 || compat_bin6) {
4506 vdd_dig.num_levels = VDD_DIG_NUM_439;
4507 vdd_dig.cur_level = VDD_DIG_NUM_439;
4508 vdd_sr2_pll.num_levels = VDD_SR2_PLL_NUM_439;
4509 vdd_sr2_pll.cur_level = VDD_SR2_PLL_NUM_439;
4510 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
4511 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
4512
Odelu Kukatlaff4c6a02018-06-28 12:45:16 +0530[diff] [blame]4513 gpll3_clk_src.test_ctl_hi_val = 0x400000;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4514 gpll3_clk_src.vco_tbl = p_vco;
4515 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
4516 gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;
4517 gpll3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 1400000000;
4518 gfx3d_clk_src.freq_tbl =
4519 ftbl_gcc_oxili_gfx3d_clk_sdm439;
4520
4521 gfx3d_clk_src.c.fmax[VDD_DIG_LOWER] = 320000000;
4522 gfx3d_clk_src.c.fmax[VDD_DIG_LOW] = 400000000;
4523 gfx3d_clk_src.c.fmax[VDD_DIG_NOMINAL] = 510000000;
4524 gfx3d_clk_src.c.fmax[VDD_DIG_NOM_PLUS] = 560000000;
4525 gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 650000000;
4526 }
4527
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4528 if (compat_bin3) {
4529 if (speed_bin) {
4530 gfx3d_clk_src.freq_tbl =
4531 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4532 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4533 500000000;
4534 } else {
4535 gfx3d_clk_src.freq_tbl =
4536 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4537 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4538 475000000;
4539 }
4540 }
4541 } else if (compat_bin2 || compat_bin4) {
4542 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4543 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4544 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4545 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4546 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4547 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4548 get_speed_bin(pdev, &speed_bin);
4549 override_for_8917(speed_bin);
4550
4551 if (compat_bin2) {
4552 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4553 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4554 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4555 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4556 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4557 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4558 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4559 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4560 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4561 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4562 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4563 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4564 }
4565 } else {
4566 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4567 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4568 }
4569
4570 ret = of_msm_clock_register(pdev->dev.of_node,
4571 msm_clocks_lookup_common,
4572 ARRAY_SIZE(msm_clocks_lookup_common));
4573 if (ret)
4574 return ret;
4575
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4576 if (compat_bin || compat_bin6)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4577 ret = of_msm_clock_register(pdev->dev.of_node,
4578 msm_clocks_lookup_8937,
4579 ARRAY_SIZE(msm_clocks_lookup_8937));
4580 else if (compat_bin2)
4581 ret = of_msm_clock_register(pdev->dev.of_node,
4582 msm_clocks_lookup_8917,
4583 ARRAY_SIZE(msm_clocks_lookup_8917));
4584 else if (compat_bin3)
4585 ret = of_msm_clock_register(pdev->dev.of_node,
4586 msm_clocks_lookup_8940,
4587 ARRAY_SIZE(msm_clocks_lookup_8940));
4588 else if (compat_bin4)
4589 ret = of_msm_clock_register(pdev->dev.of_node,
4590 msm_clocks_lookup_8920,
4591 ARRAY_SIZE(msm_clocks_lookup_8920));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4592 else if (compat_bin5)
4593 ret = of_msm_clock_register(pdev->dev.of_node,
4594 msm_clocks_lookup_sdm429,
4595 ARRAY_SIZE(msm_clocks_lookup_sdm429));
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4596 else
4597 ret = of_msm_clock_register(pdev->dev.of_node,
4598 msm_clocks_lookup_8952,
4599 ARRAY_SIZE(msm_clocks_lookup_8952));
4600 if (ret)
4601 return ret;
4602
4603 ret = enable_rpm_scaling();
4604 if (ret)
4605 return ret;
4606
4607 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4608 clk_prepare_enable(&apss_ahb_clk_src.c);
4609
4610 /*
4611 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4612 */
4613 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4614 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4615
4616 clk_prepare_enable(&xo_a_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4617
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4618 if (!compat_bin && !compat_bin3 && !compat_bin5 && !compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4619 /* Configure Sleep and Wakeup cycles for GMEM clock */
4620 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4621 regval ^= 0xFF0;
4622 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4623 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4624 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4625 } else {
4626 /* Configure Sleep and Wakeup cycles for OXILI clock */
4627 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4628 regval &= ~0xF0;
4629 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4630 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4631 }
4632
4633 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4634 if (ret)
4635 return ret;
4636
4637 msm_reset_controller_register(pdev, gcc_8952_resets,
4638 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4639
4640 dev_info(&pdev->dev, "Registered GCC clocks\n");
4641
4642 return 0;
4643}
4644
4645static const struct of_device_id msm_clock_gcc_match_table[] = {
4646 { .compatible = "qcom,gcc-8952" },
4647 { .compatible = "qcom,gcc-8937" },
4648 { .compatible = "qcom,gcc-8917" },
4649 { .compatible = "qcom,gcc-8940" },
4650 { .compatible = "qcom,gcc-8920" },
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4651 { .compatible = "qcom,gcc-sdm439" },
4652 { .compatible = "qcom,gcc-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4653 {}
4654};
4655
4656static struct platform_driver msm_clock_gcc_driver = {
4657 .probe = msm_gcc_probe,
4658 .driver = {
4659 .name = "qcom,gcc-8952",
4660 .of_match_table = msm_clock_gcc_match_table,
4661 .owner = THIS_MODULE,
4662 },
4663};
4664
4665static int msm_gcc_spm_probe(struct platform_device *pdev)
4666{
4667 struct resource *res = NULL;
4668 bool compat_bin = false;
4669
4670 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4671 "qcom,spm-8952");
4672
4673 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4674 if (!res) {
4675 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4676 return -ENOMEM;
4677 }
4678
4679 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4680 resource_size(res));
4681 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4682 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4683 return -ENOMEM;
4684 }
4685
4686 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4687 if (!res) {
4688 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4689 return -ENOMEM;
4690 }
4691
4692 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4693 resource_size(res));
4694 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4695 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4696 return -ENOMEM;
4697 }
4698
4699 if (compat_bin) {
4700 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4701 "spm_cci_base");
4702 if (!res) {
4703 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4704 return -ENOMEM;
4705 }
4706
4707 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4708 res->start, resource_size(res));
4709 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4710 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4711 return -ENOMEM;
4712 }
4713 }
4714
4715 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4716
4717 return 0;
4718}
4719
4720static const struct of_device_id msm_clock_spm_match_table[] = {
4721 { .compatible = "qcom,gcc-spm-8952" },
4722 { .compatible = "qcom,gcc-spm-8937" },
4723 {}
4724};
4725
4726static struct platform_driver msm_clock_spm_driver = {
4727 .probe = msm_gcc_spm_probe,
4728 .driver = {
4729 .name = "qcom,gcc-spm-8952",
4730 .of_match_table = msm_clock_spm_match_table,
4731 .owner = THIS_MODULE,
4732 },
4733};
4734
4735static int __init msm_gcc_init(void)
4736{
4737 int ret;
4738
4739 ret = platform_driver_register(&msm_clock_gcc_driver);
4740 if (!ret)
4741 ret = platform_driver_register(&msm_clock_spm_driver);
4742
4743 return ret;
4744}
4745
4746static struct clk_lookup msm_clocks_measure[] = {
4747 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4748 CLK_LIST(apss_debug_pri_mux),
4749 CLK_LIST(apc0_m_clk),
4750 CLK_LIST(apc1_m_clk),
4751 CLK_LIST(cci_m_clk),
4752};
4753
4754static struct clk_lookup msm_clocks_measure_8937[] = {
4755 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4756 CLK_LIST(apss_debug_pri_mux),
4757 CLK_LIST(apc0_m_clk),
4758 CLK_LIST(apc1_m_clk),
4759 CLK_LIST(cci_m_clk),
4760};
4761
4762static int msm_clock_debug_probe(struct platform_device *pdev)
4763{
4764 int ret;
4765 struct resource *res;
4766 bool compat_bin = false, compat_bin2 = false;
4767 bool compat_bin3 = false;
4768 bool compat_bin4 = false;
4769
4770 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4771 "qcom,cc-debug-8937");
4772
4773 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4774 "qcom,cc-debug-8917");
4775
4776 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4777 "qcom,cc-debug-8940");
4778
4779 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4780 "qcom,cc-debug-8920");
4781
4782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4783 if (!res) {
4784 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4785 return -EINVAL;
4786 }
4787
4788 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4789 if (!meas_base) {
4790 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4791 return -ENOMEM;
4792 }
4793
4794 clk_ops_debug_mux = clk_ops_gen_mux;
4795 clk_ops_debug_mux.get_rate = measure_get_rate;
4796
4797 if (compat_bin2)
4798 gcc_debug_mux_8937.post_div = 0x3;
4799
4800 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4801 ret = of_msm_clock_register(pdev->dev.of_node,
4802 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4803 else
4804 ret = of_msm_clock_register(pdev->dev.of_node,
4805 msm_clocks_measure_8937,
4806 ARRAY_SIZE(msm_clocks_measure_8937));
4807 if (ret) {
4808 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4809 return ret;
4810 }
4811
4812 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4813 return ret;
4814}
4815
4816static const struct of_device_id msm_clock_debug_match_table[] = {
4817 { .compatible = "qcom,cc-debug-8952" },
4818 { .compatible = "qcom,cc-debug-8937" },
4819 { .compatible = "qcom,cc-debug-8917" },
4820 { .compatible = "qcom,cc-debug-8940" },
4821 { .compatible = "qcom,cc-debug-8920" },
4822 {}
4823};
4824
4825static struct platform_driver msm_clock_debug_driver = {
4826 .probe = msm_clock_debug_probe,
4827 .driver = {
4828 .name = "qcom,cc-debug-8952",
4829 .of_match_table = msm_clock_debug_match_table,
4830 .owner = THIS_MODULE,
4831 },
4832};
4833
4834static int __init msm_clock_debug_init(void)
4835{
4836 return platform_driver_register(&msm_clock_debug_driver);
4837}
4838
4839/* MDSS DSI_PHY_PLL */
4840static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4841 CLK_LIST(ext_pclk0_clk_src),
4842 CLK_LIST(ext_byte0_clk_src),
4843 CLK_LIST(byte0_clk_src),
4844 CLK_LIST(pclk0_clk_src),
4845 CLK_LIST(gcc_mdss_pclk0_clk),
4846 CLK_LIST(gcc_mdss_byte0_clk),
4847 CLK_LIST(mdss_mdp_vote_clk),
4848 CLK_LIST(mdss_rotator_vote_clk),
4849};
4850
4851static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4852 CLK_LIST(ext_pclk1_clk_src),
4853 CLK_LIST(ext_byte1_clk_src),
4854 CLK_LIST(byte1_clk_src),
4855 CLK_LIST(pclk1_clk_src),
4856 CLK_LIST(gcc_mdss_pclk1_clk),
4857 CLK_LIST(gcc_mdss_byte1_clk),
4858};
4859
4860static int msm_gcc_mdss_probe(struct platform_device *pdev)
4861{
4862 int ret = 0;
4863 struct clk *curr_p;
4864 bool compat_bin = false;
4865
4866 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4867 "qcom,gcc-mdss-8937");
4868 if (!compat_bin)
4869 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4870 "qcom,gcc-mdss-8940");
4871
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4872 if (!compat_bin)
4873 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4874 "qcom,gcc-mdss-sdm439");
4875
4876 if (!compat_bin)
4877 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4878 "qcom,gcc-mdss-sdm429");
4879
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4880 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4881 "pclk0_src");
4882 if (IS_ERR(curr_p)) {
4883 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4884 return PTR_ERR(curr_p);
4885 }
4886
4887 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4888 "byte0_src");
4889 if (IS_ERR(curr_p)) {
4890 dev_err(&pdev->dev, "Failed to get byte source.\n");
4891 ret = PTR_ERR(curr_p);
4892 goto byte0_fail;
4893 }
4894
4895 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4896 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4897
4898 if (compat_bin) {
4899 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4900 "pclk1_src");
4901 if (IS_ERR(curr_p)) {
4902 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4903 ret = PTR_ERR(curr_p);
4904 goto fail;
4905 }
4906
4907 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4908 "byte1_src");
4909 if (IS_ERR(curr_p)) {
4910 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4911 ret = PTR_ERR(curr_p);
4912 goto byte1_fail;
4913 }
4914
4915 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4916 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4917 }
4918
4919 ret = of_msm_clock_register(pdev->dev.of_node,
4920 msm_clocks_gcc_mdss_common,
4921 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4922 if (ret)
4923 goto fail;
4924
4925 if (compat_bin) {
4926 ret = of_msm_clock_register(pdev->dev.of_node,
4927 msm_clocks_gcc_mdss_8937,
4928 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4929 if (ret)
4930 goto fail_8937;
4931 }
4932
4933 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4934
4935 return ret;
4936fail_8937:
4937 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4938byte1_fail:
4939 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4940fail:
4941 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4942byte0_fail:
4943 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4944 return ret;
4945
4946}
4947
4948static const struct of_device_id msm_clock_mdss_match_table[] = {
4949 { .compatible = "qcom,gcc-mdss-8952" },
4950 { .compatible = "qcom,gcc-mdss-8937" },
4951 { .compatible = "qcom,gcc-mdss-8917" },
4952 { .compatible = "qcom,gcc-mdss-8940" },
4953 { .compatible = "qcom,gcc-mdss-8920" },
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4954 { .compatible = "qcom,gcc-mdss-sdm439" },
4955 { .compatible = "qcom,gcc-mdss-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4956 {}
4957};
4958
4959static struct platform_driver msm_clock_gcc_mdss_driver = {
4960 .probe = msm_gcc_mdss_probe,
4961 .driver = {
4962 .name = "gcc-mdss-8952",
4963 .of_match_table = msm_clock_mdss_match_table,
4964 .owner = THIS_MODULE,
4965 },
4966};
4967
4968static int __init msm_gcc_mdss_init(void)
4969{
4970 return platform_driver_register(&msm_clock_gcc_mdss_driver);
4971}
4972arch_initcall(msm_gcc_init);
4973fs_initcall_sync(msm_gcc_mdss_init);
4974late_initcall(msm_clock_debug_init);