Devdutt Patnaik | 9e653b1 | 2017-05-30 22:13:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/power_supply.h> |
| 25 | #include <linux/regulator/consumer.h> |
| 26 | #include <linux/regulator/driver.h> |
| 27 | #include <linux/regulator/machine.h> |
| 28 | #include <linux/usb/phy.h> |
| 29 | #include <linux/reset.h> |
| 30 | |
| 31 | #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) |
| 32 | #define SLEEPM BIT(0) |
| 33 | |
| 34 | #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) |
| 35 | #define ATERESET BIT(0) |
| 36 | #define POR BIT(1) |
| 37 | |
| 38 | #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) |
| 39 | #define VATESTENB_MASK (0x3 << 0) |
| 40 | #define RETENABLEN BIT(3) |
| 41 | #define FSEL_MASK (0x7 << 4) |
| 42 | #define FSEL_DEFAULT (0x3 << 4) |
| 43 | |
| 44 | #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) |
| 45 | #define VBUSVLDEXTSEL0 BIT(4) |
| 46 | #define PLLBTUNE BIT(5) |
| 47 | |
| 48 | #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) |
| 49 | #define VREGBYPASS BIT(0) |
| 50 | |
| 51 | #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) |
| 52 | #define VBUSVLDEXT0 BIT(0) |
| 53 | |
| 54 | #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) |
| 55 | #define USB2_SUSPEND_N BIT(2) |
| 56 | #define USB2_SUSPEND_N_SEL BIT(3) |
| 57 | |
| 58 | #define USB2_PHY_USB_PHY_HS_PHY_TEST0 (0x80) |
| 59 | #define TESTDATAIN_MASK (0xff << 0) |
| 60 | |
| 61 | #define USB2_PHY_USB_PHY_HS_PHY_TEST1 (0x84) |
| 62 | #define TESTDATAOUTSEL BIT(4) |
| 63 | #define TOGGLE_2WR BIT(6) |
| 64 | |
| 65 | #define USB2_PHY_USB_PHY_CFG0 (0x94) |
| 66 | #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) |
| 67 | |
| 68 | #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) |
| 69 | #define REFCLK_SEL_MASK (0x3 << 0) |
| 70 | #define REFCLK_SEL_DEFAULT (0x2 << 0) |
| 71 | |
| 72 | #define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */ |
| 73 | #define USB_HSPHY_3P3_VOL_MAX 3300000 /* uV */ |
| 74 | #define USB_HSPHY_3P3_HPM_LOAD 16000 /* uA */ |
| 75 | #define USB_HSPHY_3P3_VOL_FSHOST 3150000 /* uV */ |
| 76 | |
| 77 | #define USB_HSPHY_1P8_VOL_MIN 1800000 /* uV */ |
| 78 | #define USB_HSPHY_1P8_VOL_MAX 1800000 /* uV */ |
| 79 | #define USB_HSPHY_1P8_HPM_LOAD 19000 /* uA */ |
| 80 | |
| 81 | struct msm_hsphy { |
| 82 | struct usb_phy phy; |
| 83 | void __iomem *base; |
| 84 | |
| 85 | struct clk *ref_clk_src; |
| 86 | struct clk *cfg_ahb_clk; |
| 87 | struct reset_control *phy_reset; |
| 88 | |
| 89 | struct regulator *vdd; |
| 90 | struct regulator *vdda33; |
| 91 | struct regulator *vdda18; |
| 92 | int vdd_levels[3]; /* none, low, high */ |
| 93 | |
| 94 | bool clocks_enabled; |
| 95 | bool power_enabled; |
| 96 | bool suspended; |
| 97 | bool cable_connected; |
| 98 | |
| 99 | /* emulation targets specific */ |
| 100 | void __iomem *emu_phy_base; |
| 101 | int *emu_init_seq; |
| 102 | int emu_init_seq_len; |
| 103 | int *emu_dcm_reset_seq; |
| 104 | int emu_dcm_reset_seq_len; |
| 105 | }; |
| 106 | |
| 107 | static void msm_hsphy_enable_clocks(struct msm_hsphy *phy, bool on) |
| 108 | { |
| 109 | dev_dbg(phy->phy.dev, "%s(): clocks_enabled:%d on:%d\n", |
| 110 | __func__, phy->clocks_enabled, on); |
| 111 | |
| 112 | if (!phy->clocks_enabled && on) { |
| 113 | clk_prepare_enable(phy->ref_clk_src); |
| 114 | |
| 115 | if (phy->cfg_ahb_clk) |
| 116 | clk_prepare_enable(phy->cfg_ahb_clk); |
| 117 | |
| 118 | phy->clocks_enabled = true; |
| 119 | } |
| 120 | |
| 121 | if (phy->clocks_enabled && !on) { |
| 122 | if (phy->cfg_ahb_clk) |
| 123 | clk_disable_unprepare(phy->cfg_ahb_clk); |
| 124 | |
| 125 | clk_disable_unprepare(phy->ref_clk_src); |
| 126 | phy->clocks_enabled = false; |
| 127 | } |
| 128 | |
| 129 | } |
| 130 | static int msm_hsphy_config_vdd(struct msm_hsphy *phy, int high) |
| 131 | { |
| 132 | int min, ret; |
| 133 | |
| 134 | min = high ? 1 : 0; /* low or none? */ |
| 135 | ret = regulator_set_voltage(phy->vdd, phy->vdd_levels[min], |
| 136 | phy->vdd_levels[2]); |
| 137 | if (ret) { |
| 138 | dev_err(phy->phy.dev, "unable to set voltage for hsusb vdd\n"); |
| 139 | return ret; |
| 140 | } |
| 141 | |
| 142 | dev_dbg(phy->phy.dev, "%s: min_vol:%d max_vol:%d\n", __func__, |
| 143 | phy->vdd_levels[min], phy->vdd_levels[2]); |
| 144 | |
| 145 | return ret; |
| 146 | } |
| 147 | |
| 148 | static int msm_hsphy_enable_power(struct msm_hsphy *phy, bool on) |
| 149 | { |
| 150 | int ret = 0; |
| 151 | |
| 152 | dev_dbg(phy->phy.dev, "%s turn %s regulators. power_enabled:%d\n", |
| 153 | __func__, on ? "on" : "off", phy->power_enabled); |
| 154 | |
| 155 | if (phy->power_enabled == on) { |
| 156 | dev_dbg(phy->phy.dev, "PHYs' regulators are already ON.\n"); |
| 157 | return 0; |
| 158 | } |
| 159 | |
| 160 | if (!on) |
| 161 | goto disable_vdda33; |
| 162 | |
| 163 | ret = msm_hsphy_config_vdd(phy, true); |
| 164 | if (ret) { |
| 165 | dev_err(phy->phy.dev, "Unable to config VDD:%d\n", |
| 166 | ret); |
| 167 | goto err_vdd; |
| 168 | } |
| 169 | |
| 170 | ret = regulator_enable(phy->vdd); |
| 171 | if (ret) { |
| 172 | dev_err(phy->phy.dev, "Unable to enable VDD\n"); |
| 173 | goto unconfig_vdd; |
| 174 | } |
| 175 | |
| 176 | ret = regulator_set_load(phy->vdda18, USB_HSPHY_1P8_HPM_LOAD); |
| 177 | if (ret < 0) { |
| 178 | dev_err(phy->phy.dev, "Unable to set HPM of vdda18:%d\n", ret); |
| 179 | goto disable_vdd; |
| 180 | } |
| 181 | |
| 182 | ret = regulator_set_voltage(phy->vdda18, USB_HSPHY_1P8_VOL_MIN, |
| 183 | USB_HSPHY_1P8_VOL_MAX); |
| 184 | if (ret) { |
| 185 | dev_err(phy->phy.dev, |
| 186 | "Unable to set voltage for vdda18:%d\n", ret); |
| 187 | goto put_vdda18_lpm; |
| 188 | } |
| 189 | |
| 190 | ret = regulator_enable(phy->vdda18); |
| 191 | if (ret) { |
| 192 | dev_err(phy->phy.dev, "Unable to enable vdda18:%d\n", ret); |
| 193 | goto unset_vdda18; |
| 194 | } |
| 195 | |
| 196 | ret = regulator_set_load(phy->vdda33, USB_HSPHY_3P3_HPM_LOAD); |
| 197 | if (ret < 0) { |
| 198 | dev_err(phy->phy.dev, "Unable to set HPM of vdda33:%d\n", ret); |
| 199 | goto disable_vdda18; |
| 200 | } |
| 201 | |
| 202 | ret = regulator_set_voltage(phy->vdda33, USB_HSPHY_3P3_VOL_MIN, |
| 203 | USB_HSPHY_3P3_VOL_MAX); |
| 204 | if (ret) { |
| 205 | dev_err(phy->phy.dev, |
| 206 | "Unable to set voltage for vdda33:%d\n", ret); |
| 207 | goto put_vdda33_lpm; |
| 208 | } |
| 209 | |
| 210 | ret = regulator_enable(phy->vdda33); |
| 211 | if (ret) { |
| 212 | dev_err(phy->phy.dev, "Unable to enable vdda33:%d\n", ret); |
| 213 | goto unset_vdd33; |
| 214 | } |
| 215 | |
| 216 | phy->power_enabled = true; |
| 217 | |
| 218 | pr_debug("%s(): HSUSB PHY's regulators are turned ON.\n", __func__); |
| 219 | return ret; |
| 220 | |
| 221 | disable_vdda33: |
| 222 | ret = regulator_disable(phy->vdda33); |
| 223 | if (ret) |
| 224 | dev_err(phy->phy.dev, "Unable to disable vdda33:%d\n", ret); |
| 225 | |
| 226 | unset_vdd33: |
| 227 | ret = regulator_set_voltage(phy->vdda33, 0, USB_HSPHY_3P3_VOL_MAX); |
| 228 | if (ret) |
| 229 | dev_err(phy->phy.dev, |
| 230 | "Unable to set (0) voltage for vdda33:%d\n", ret); |
| 231 | |
| 232 | put_vdda33_lpm: |
| 233 | ret = regulator_set_load(phy->vdda33, 0); |
| 234 | if (ret < 0) |
| 235 | dev_err(phy->phy.dev, "Unable to set (0) HPM of vdda33\n"); |
| 236 | |
| 237 | disable_vdda18: |
| 238 | ret = regulator_disable(phy->vdda18); |
| 239 | if (ret) |
| 240 | dev_err(phy->phy.dev, "Unable to disable vdda18:%d\n", ret); |
| 241 | |
| 242 | unset_vdda18: |
| 243 | ret = regulator_set_voltage(phy->vdda18, 0, USB_HSPHY_1P8_VOL_MAX); |
| 244 | if (ret) |
| 245 | dev_err(phy->phy.dev, |
| 246 | "Unable to set (0) voltage for vdda18:%d\n", ret); |
| 247 | |
| 248 | put_vdda18_lpm: |
| 249 | ret = regulator_set_load(phy->vdda18, 0); |
| 250 | if (ret < 0) |
| 251 | dev_err(phy->phy.dev, "Unable to set LPM of vdda18\n"); |
| 252 | |
| 253 | disable_vdd: |
| 254 | if (ret) |
| 255 | dev_err(phy->phy.dev, "Unable to disable vdd:%d\n", |
| 256 | ret); |
| 257 | |
| 258 | unconfig_vdd: |
| 259 | ret = msm_hsphy_config_vdd(phy, false); |
| 260 | if (ret) |
| 261 | dev_err(phy->phy.dev, "Unable unconfig VDD:%d\n", |
| 262 | ret); |
| 263 | err_vdd: |
| 264 | phy->power_enabled = false; |
| 265 | dev_dbg(phy->phy.dev, "HSUSB PHY's regulators are turned OFF.\n"); |
| 266 | return ret; |
| 267 | } |
| 268 | |
| 269 | static void msm_usb_write_readback(void __iomem *base, u32 offset, |
| 270 | const u32 mask, u32 val) |
| 271 | { |
| 272 | u32 write_val, tmp = readl_relaxed(base + offset); |
| 273 | |
| 274 | tmp &= ~mask; /* retain other bits */ |
| 275 | write_val = tmp | val; |
| 276 | |
| 277 | writel_relaxed(write_val, base + offset); |
| 278 | |
| 279 | /* Read back to see if val was written */ |
| 280 | tmp = readl_relaxed(base + offset); |
| 281 | tmp &= mask; /* clear other bits */ |
| 282 | |
| 283 | if (tmp != val) |
| 284 | pr_err("%s: write: %x to QSCRATCH: %x FAILED\n", |
| 285 | __func__, val, offset); |
| 286 | } |
| 287 | |
| 288 | static void msm_hsphy_reset(struct msm_hsphy *phy) |
| 289 | { |
| 290 | int ret; |
| 291 | |
| 292 | ret = reset_control_assert(phy->phy_reset); |
| 293 | if (ret) |
| 294 | dev_err(phy->phy.dev, "%s: phy_reset assert failed\n", |
| 295 | __func__); |
| 296 | usleep_range(100, 150); |
| 297 | |
| 298 | ret = reset_control_deassert(phy->phy_reset); |
| 299 | if (ret) |
| 300 | dev_err(phy->phy.dev, "%s: phy_reset deassert failed\n", |
| 301 | __func__); |
| 302 | } |
| 303 | |
| 304 | static void hsusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt, |
| 305 | unsigned long delay) |
| 306 | { |
| 307 | int i; |
| 308 | |
| 309 | pr_debug("Seq count:%d\n", cnt); |
| 310 | for (i = 0; i < cnt; i = i+2) { |
| 311 | pr_debug("write 0x%02x to 0x%02x\n", seq[i], seq[i+1]); |
| 312 | writel_relaxed(seq[i], base + seq[i+1]); |
| 313 | if (delay) |
| 314 | usleep_range(delay, (delay + 2000)); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | static int msm_hsphy_emu_init(struct usb_phy *uphy) |
| 319 | { |
| 320 | struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy); |
| 321 | int ret; |
| 322 | |
| 323 | dev_dbg(uphy->dev, "%s\n", __func__); |
| 324 | |
| 325 | ret = msm_hsphy_enable_power(phy, true); |
| 326 | if (ret) |
| 327 | return ret; |
| 328 | |
| 329 | msm_hsphy_enable_clocks(phy, true); |
| 330 | msm_hsphy_reset(phy); |
| 331 | |
| 332 | if (phy->emu_init_seq) { |
| 333 | hsusb_phy_write_seq(phy->base, |
| 334 | phy->emu_init_seq, |
| 335 | phy->emu_init_seq_len, 10000); |
| 336 | |
| 337 | /* Wait for 5ms as per QUSB2 RUMI sequence */ |
| 338 | usleep_range(5000, 7000); |
| 339 | |
| 340 | if (phy->emu_dcm_reset_seq) |
| 341 | hsusb_phy_write_seq(phy->emu_phy_base, |
| 342 | phy->emu_dcm_reset_seq, |
| 343 | phy->emu_dcm_reset_seq_len, 10000); |
| 344 | } |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | static int msm_hsphy_init(struct usb_phy *uphy) |
| 350 | { |
| 351 | struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy); |
| 352 | int ret; |
| 353 | |
| 354 | dev_dbg(uphy->dev, "%s\n", __func__); |
| 355 | |
| 356 | ret = msm_hsphy_enable_power(phy, true); |
| 357 | if (ret) |
| 358 | return ret; |
| 359 | |
| 360 | msm_hsphy_enable_clocks(phy, true); |
| 361 | msm_hsphy_reset(phy); |
| 362 | |
| 363 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0, |
| 364 | UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN); |
| 365 | |
| 366 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, |
| 367 | POR, POR); |
| 368 | |
| 369 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, |
| 370 | FSEL_MASK, 0); |
| 371 | |
| 372 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, |
| 373 | PLLBTUNE, PLLBTUNE); |
| 374 | |
| 375 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, |
| 376 | REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT); |
| 377 | |
| 378 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, |
| 379 | VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); |
| 380 | |
| 381 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, |
| 382 | VBUSVLDEXT0, VBUSVLDEXT0); |
| 383 | |
| 384 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, |
| 385 | VREGBYPASS, VREGBYPASS); |
| 386 | |
| 387 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, |
| 388 | ATERESET, ATERESET); |
| 389 | |
| 390 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST1, |
| 391 | TESTDATAOUTSEL, TESTDATAOUTSEL); |
| 392 | |
| 393 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST1, |
| 394 | TOGGLE_2WR, TOGGLE_2WR); |
| 395 | |
| 396 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, |
| 397 | VATESTENB_MASK, 0); |
| 398 | |
| 399 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST0, |
| 400 | TESTDATAIN_MASK, 0); |
| 401 | |
| 402 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
| 403 | USB2_SUSPEND_N_SEL, USB2_SUSPEND_N_SEL); |
| 404 | |
| 405 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
| 406 | USB2_SUSPEND_N, USB2_SUSPEND_N); |
| 407 | |
| 408 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, |
| 409 | SLEEPM, SLEEPM); |
| 410 | |
| 411 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, |
| 412 | POR, 0); |
| 413 | |
| 414 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, |
| 415 | USB2_SUSPEND_N_SEL, 0); |
| 416 | |
| 417 | msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0, |
| 418 | UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | static int msm_hsphy_set_suspend(struct usb_phy *uphy, int suspend) |
| 424 | { |
| 425 | return 0; |
| 426 | } |
| 427 | |
| 428 | static int msm_hsphy_notify_connect(struct usb_phy *uphy, |
| 429 | enum usb_device_speed speed) |
| 430 | { |
| 431 | struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy); |
| 432 | |
| 433 | phy->cable_connected = true; |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static int msm_hsphy_notify_disconnect(struct usb_phy *uphy, |
| 439 | enum usb_device_speed speed) |
| 440 | { |
| 441 | struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy); |
| 442 | |
| 443 | phy->cable_connected = false; |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static int msm_hsphy_probe(struct platform_device *pdev) |
| 449 | { |
| 450 | struct msm_hsphy *phy; |
| 451 | struct device *dev = &pdev->dev; |
| 452 | struct resource *res; |
| 453 | int ret = 0, size = 0; |
| 454 | |
| 455 | |
| 456 | phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
| 457 | if (!phy) { |
| 458 | ret = -ENOMEM; |
| 459 | goto err_ret; |
| 460 | } |
| 461 | |
| 462 | phy->phy.dev = dev; |
| 463 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 464 | "hsusb_phy_base"); |
| 465 | if (!res) { |
| 466 | dev_err(dev, "missing memory base resource\n"); |
| 467 | ret = -ENODEV; |
| 468 | goto err_ret; |
| 469 | } |
| 470 | |
| 471 | phy->base = devm_ioremap_resource(dev, res); |
| 472 | if (IS_ERR(phy->base)) { |
| 473 | dev_err(dev, "ioremap failed\n"); |
| 474 | ret = -ENODEV; |
| 475 | goto err_ret; |
| 476 | } |
| 477 | |
| 478 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 479 | "emu_phy_base"); |
| 480 | if (res) { |
| 481 | phy->emu_phy_base = devm_ioremap_resource(dev, res); |
| 482 | if (IS_ERR(phy->emu_phy_base)) { |
| 483 | dev_dbg(dev, "couldn't ioremap emu_phy_base\n"); |
| 484 | phy->emu_phy_base = NULL; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | /* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */ |
| 489 | phy->ref_clk_src = devm_clk_get(dev, "ref_clk_src"); |
| 490 | if (IS_ERR(phy->ref_clk_src)) { |
| 491 | dev_dbg(dev, "clk get failed for ref_clk_src\n"); |
| 492 | ret = PTR_ERR(phy->ref_clk_src); |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | if (of_property_match_string(pdev->dev.of_node, |
| 497 | "clock-names", "cfg_ahb_clk") >= 0) { |
| 498 | phy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk"); |
| 499 | if (IS_ERR(phy->cfg_ahb_clk)) { |
| 500 | ret = PTR_ERR(phy->cfg_ahb_clk); |
| 501 | if (ret != -EPROBE_DEFER) |
| 502 | dev_err(dev, |
| 503 | "clk get failed for cfg_ahb_clk ret %d\n", ret); |
| 504 | return ret; |
| 505 | } |
| 506 | } |
| 507 | |
| 508 | phy->phy_reset = devm_reset_control_get(dev, "phy_reset"); |
| 509 | if (IS_ERR(phy->phy_reset)) |
| 510 | return PTR_ERR(phy->phy_reset); |
| 511 | |
| 512 | of_get_property(dev->of_node, "qcom,emu-init-seq", &size); |
| 513 | if (size) { |
| 514 | phy->emu_init_seq = devm_kzalloc(dev, |
| 515 | size, GFP_KERNEL); |
| 516 | if (phy->emu_init_seq) { |
| 517 | phy->emu_init_seq_len = |
| 518 | (size / sizeof(*phy->emu_init_seq)); |
| 519 | if (phy->emu_init_seq_len % 2) { |
| 520 | dev_err(dev, "invalid emu_init_seq_len\n"); |
| 521 | return -EINVAL; |
| 522 | } |
| 523 | |
| 524 | of_property_read_u32_array(dev->of_node, |
| 525 | "qcom,emu-init-seq", |
| 526 | phy->emu_init_seq, |
| 527 | phy->emu_init_seq_len); |
| 528 | } else { |
| 529 | dev_dbg(dev, |
| 530 | "error allocating memory for emu_init_seq\n"); |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | size = 0; |
| 535 | of_get_property(dev->of_node, "qcom,emu-dcm-reset-seq", &size); |
| 536 | if (size) { |
| 537 | phy->emu_dcm_reset_seq = devm_kzalloc(dev, |
| 538 | size, GFP_KERNEL); |
| 539 | if (phy->emu_dcm_reset_seq) { |
| 540 | phy->emu_dcm_reset_seq_len = |
| 541 | (size / sizeof(*phy->emu_dcm_reset_seq)); |
| 542 | if (phy->emu_dcm_reset_seq_len % 2) { |
| 543 | dev_err(dev, "invalid emu_dcm_reset_seq_len\n"); |
| 544 | return -EINVAL; |
| 545 | } |
| 546 | |
| 547 | of_property_read_u32_array(dev->of_node, |
| 548 | "qcom,emu-dcm-reset-seq", |
| 549 | phy->emu_dcm_reset_seq, |
| 550 | phy->emu_dcm_reset_seq_len); |
| 551 | } else { |
| 552 | dev_dbg(dev, |
| 553 | "error allocating memory for emu_dcm_reset_seq\n"); |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", |
| 558 | (u32 *) phy->vdd_levels, |
| 559 | ARRAY_SIZE(phy->vdd_levels)); |
| 560 | if (ret) { |
| 561 | dev_err(dev, "error reading qcom,vdd-voltage-level property\n"); |
| 562 | goto err_ret; |
| 563 | } |
| 564 | |
| 565 | |
| 566 | phy->vdd = devm_regulator_get(dev, "vdd"); |
| 567 | if (IS_ERR(phy->vdd)) { |
| 568 | dev_err(dev, "unable to get vdd supply\n"); |
| 569 | ret = PTR_ERR(phy->vdd); |
| 570 | goto err_ret; |
| 571 | } |
| 572 | |
| 573 | phy->vdda33 = devm_regulator_get(dev, "vdda33"); |
| 574 | if (IS_ERR(phy->vdda33)) { |
| 575 | dev_err(dev, "unable to get vdda33 supply\n"); |
| 576 | ret = PTR_ERR(phy->vdda33); |
| 577 | goto err_ret; |
| 578 | } |
| 579 | |
| 580 | phy->vdda18 = devm_regulator_get(dev, "vdda18"); |
| 581 | if (IS_ERR(phy->vdda18)) { |
| 582 | dev_err(dev, "unable to get vdda18 supply\n"); |
| 583 | ret = PTR_ERR(phy->vdda18); |
| 584 | goto err_ret; |
| 585 | } |
| 586 | |
| 587 | platform_set_drvdata(pdev, phy); |
| 588 | |
| 589 | if (phy->emu_init_seq) |
| 590 | phy->phy.init = msm_hsphy_emu_init; |
| 591 | else |
| 592 | phy->phy.init = msm_hsphy_init; |
| 593 | phy->phy.set_suspend = msm_hsphy_set_suspend; |
| 594 | phy->phy.notify_connect = msm_hsphy_notify_connect; |
| 595 | phy->phy.notify_disconnect = msm_hsphy_notify_disconnect; |
| 596 | phy->phy.type = USB_PHY_TYPE_USB2; |
| 597 | |
| 598 | ret = usb_add_phy_dev(&phy->phy); |
| 599 | if (ret) |
| 600 | return ret; |
| 601 | |
| 602 | return 0; |
| 603 | |
| 604 | err_ret: |
| 605 | return ret; |
| 606 | } |
| 607 | |
| 608 | static int msm_hsphy_remove(struct platform_device *pdev) |
| 609 | { |
| 610 | struct msm_hsphy *phy = platform_get_drvdata(pdev); |
| 611 | |
| 612 | if (!phy) |
| 613 | return 0; |
| 614 | |
| 615 | usb_remove_phy(&phy->phy); |
| 616 | clk_disable_unprepare(phy->ref_clk_src); |
| 617 | |
| 618 | msm_hsphy_enable_clocks(phy, false); |
| 619 | msm_hsphy_enable_power(phy, false); |
| 620 | |
| 621 | kfree(phy); |
| 622 | |
| 623 | return 0; |
| 624 | } |
| 625 | |
| 626 | static const struct of_device_id msm_usb_id_table[] = { |
| 627 | { |
| 628 | .compatible = "qcom,usb-hsphy-snps-femto", |
| 629 | }, |
| 630 | { }, |
| 631 | }; |
| 632 | MODULE_DEVICE_TABLE(of, msm_usb_id_table); |
| 633 | |
| 634 | static struct platform_driver msm_hsphy_driver = { |
| 635 | .probe = msm_hsphy_probe, |
| 636 | .remove = msm_hsphy_remove, |
| 637 | .driver = { |
| 638 | .name = "msm-usb-hsphy", |
| 639 | .of_match_table = of_match_ptr(msm_usb_id_table), |
| 640 | }, |
| 641 | }; |
| 642 | |
| 643 | module_platform_driver(msm_hsphy_driver); |
| 644 | |
| 645 | MODULE_DESCRIPTION("MSM USB HS PHY driver"); |
| 646 | MODULE_LICENSE("GPL v2"); |