addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/scatterlist.h> |
| 26 | #include <linux/of.h> |
| 27 | #include <linux/pm_runtime.h> |
| 28 | #include <linux/io.h> |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 29 | #include <linux/dmaengine.h> |
| 30 | |
| 31 | #define DRIVER_NAME "rockchip-spi" |
| 32 | |
| 33 | /* SPI register offsets */ |
| 34 | #define ROCKCHIP_SPI_CTRLR0 0x0000 |
| 35 | #define ROCKCHIP_SPI_CTRLR1 0x0004 |
| 36 | #define ROCKCHIP_SPI_SSIENR 0x0008 |
| 37 | #define ROCKCHIP_SPI_SER 0x000c |
| 38 | #define ROCKCHIP_SPI_BAUDR 0x0010 |
| 39 | #define ROCKCHIP_SPI_TXFTLR 0x0014 |
| 40 | #define ROCKCHIP_SPI_RXFTLR 0x0018 |
| 41 | #define ROCKCHIP_SPI_TXFLR 0x001c |
| 42 | #define ROCKCHIP_SPI_RXFLR 0x0020 |
| 43 | #define ROCKCHIP_SPI_SR 0x0024 |
| 44 | #define ROCKCHIP_SPI_IPR 0x0028 |
| 45 | #define ROCKCHIP_SPI_IMR 0x002c |
| 46 | #define ROCKCHIP_SPI_ISR 0x0030 |
| 47 | #define ROCKCHIP_SPI_RISR 0x0034 |
| 48 | #define ROCKCHIP_SPI_ICR 0x0038 |
| 49 | #define ROCKCHIP_SPI_DMACR 0x003c |
| 50 | #define ROCKCHIP_SPI_DMATDLR 0x0040 |
| 51 | #define ROCKCHIP_SPI_DMARDLR 0x0044 |
| 52 | #define ROCKCHIP_SPI_TXDR 0x0400 |
| 53 | #define ROCKCHIP_SPI_RXDR 0x0800 |
| 54 | |
| 55 | /* Bit fields in CTRLR0 */ |
| 56 | #define CR0_DFS_OFFSET 0 |
| 57 | |
| 58 | #define CR0_CFS_OFFSET 2 |
| 59 | |
| 60 | #define CR0_SCPH_OFFSET 6 |
| 61 | |
| 62 | #define CR0_SCPOL_OFFSET 7 |
| 63 | |
| 64 | #define CR0_CSM_OFFSET 8 |
| 65 | #define CR0_CSM_KEEP 0x0 |
| 66 | /* ss_n be high for half sclk_out cycles */ |
| 67 | #define CR0_CSM_HALF 0X1 |
| 68 | /* ss_n be high for one sclk_out cycle */ |
| 69 | #define CR0_CSM_ONE 0x2 |
| 70 | |
| 71 | /* ss_n to sclk_out delay */ |
| 72 | #define CR0_SSD_OFFSET 10 |
| 73 | /* |
| 74 | * The period between ss_n active and |
| 75 | * sclk_out active is half sclk_out cycles |
| 76 | */ |
| 77 | #define CR0_SSD_HALF 0x0 |
| 78 | /* |
| 79 | * The period between ss_n active and |
| 80 | * sclk_out active is one sclk_out cycle |
| 81 | */ |
| 82 | #define CR0_SSD_ONE 0x1 |
| 83 | |
| 84 | #define CR0_EM_OFFSET 11 |
| 85 | #define CR0_EM_LITTLE 0x0 |
| 86 | #define CR0_EM_BIG 0x1 |
| 87 | |
| 88 | #define CR0_FBM_OFFSET 12 |
| 89 | #define CR0_FBM_MSB 0x0 |
| 90 | #define CR0_FBM_LSB 0x1 |
| 91 | |
| 92 | #define CR0_BHT_OFFSET 13 |
| 93 | #define CR0_BHT_16BIT 0x0 |
| 94 | #define CR0_BHT_8BIT 0x1 |
| 95 | |
| 96 | #define CR0_RSD_OFFSET 14 |
| 97 | |
| 98 | #define CR0_FRF_OFFSET 16 |
| 99 | #define CR0_FRF_SPI 0x0 |
| 100 | #define CR0_FRF_SSP 0x1 |
| 101 | #define CR0_FRF_MICROWIRE 0x2 |
| 102 | |
| 103 | #define CR0_XFM_OFFSET 18 |
| 104 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) |
| 105 | #define CR0_XFM_TR 0x0 |
| 106 | #define CR0_XFM_TO 0x1 |
| 107 | #define CR0_XFM_RO 0x2 |
| 108 | |
| 109 | #define CR0_OPM_OFFSET 20 |
| 110 | #define CR0_OPM_MASTER 0x0 |
| 111 | #define CR0_OPM_SLAVE 0x1 |
| 112 | |
| 113 | #define CR0_MTM_OFFSET 0x21 |
| 114 | |
| 115 | /* Bit fields in SER, 2bit */ |
| 116 | #define SER_MASK 0x3 |
| 117 | |
| 118 | /* Bit fields in SR, 5bit */ |
| 119 | #define SR_MASK 0x1f |
| 120 | #define SR_BUSY (1 << 0) |
| 121 | #define SR_TF_FULL (1 << 1) |
| 122 | #define SR_TF_EMPTY (1 << 2) |
| 123 | #define SR_RF_EMPTY (1 << 3) |
| 124 | #define SR_RF_FULL (1 << 4) |
| 125 | |
| 126 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ |
| 127 | #define INT_MASK 0x1f |
| 128 | #define INT_TF_EMPTY (1 << 0) |
| 129 | #define INT_TF_OVERFLOW (1 << 1) |
| 130 | #define INT_RF_UNDERFLOW (1 << 2) |
| 131 | #define INT_RF_OVERFLOW (1 << 3) |
| 132 | #define INT_RF_FULL (1 << 4) |
| 133 | |
| 134 | /* Bit fields in ICR, 4bit */ |
| 135 | #define ICR_MASK 0x0f |
| 136 | #define ICR_ALL (1 << 0) |
| 137 | #define ICR_RF_UNDERFLOW (1 << 1) |
| 138 | #define ICR_RF_OVERFLOW (1 << 2) |
| 139 | #define ICR_TF_OVERFLOW (1 << 3) |
| 140 | |
| 141 | /* Bit fields in DMACR */ |
| 142 | #define RF_DMA_EN (1 << 0) |
| 143 | #define TF_DMA_EN (1 << 1) |
| 144 | |
| 145 | #define RXBUSY (1 << 0) |
| 146 | #define TXBUSY (1 << 1) |
| 147 | |
Addy Ke | f9cfd52 | 2014-10-15 19:25:49 +0800 | [diff] [blame] | 148 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
| 149 | #define MAX_SCLK_OUT 50000000 |
| 150 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 151 | enum rockchip_ssi_type { |
| 152 | SSI_MOTO_SPI = 0, |
| 153 | SSI_TI_SSP, |
| 154 | SSI_NS_MICROWIRE, |
| 155 | }; |
| 156 | |
| 157 | struct rockchip_spi_dma_data { |
| 158 | struct dma_chan *ch; |
| 159 | enum dma_transfer_direction direction; |
| 160 | dma_addr_t addr; |
| 161 | }; |
| 162 | |
| 163 | struct rockchip_spi { |
| 164 | struct device *dev; |
| 165 | struct spi_master *master; |
| 166 | |
| 167 | struct clk *spiclk; |
| 168 | struct clk *apb_pclk; |
| 169 | |
| 170 | void __iomem *regs; |
| 171 | /*depth of the FIFO buffer */ |
| 172 | u32 fifo_len; |
| 173 | /* max bus freq supported */ |
| 174 | u32 max_freq; |
| 175 | /* supported slave numbers */ |
| 176 | enum rockchip_ssi_type type; |
| 177 | |
| 178 | u16 mode; |
| 179 | u8 tmode; |
| 180 | u8 bpw; |
| 181 | u8 n_bytes; |
Julius Werner | 76b17e6 | 2015-03-26 16:30:25 -0700 | [diff] [blame] | 182 | u8 rsd_nsecs; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 183 | unsigned len; |
| 184 | u32 speed; |
| 185 | |
| 186 | const void *tx; |
| 187 | const void *tx_end; |
| 188 | void *rx; |
| 189 | void *rx_end; |
| 190 | |
| 191 | u32 state; |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 192 | /* protect state */ |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 193 | spinlock_t lock; |
| 194 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 195 | u32 use_dma; |
| 196 | struct sg_table tx_sg; |
| 197 | struct sg_table rx_sg; |
| 198 | struct rockchip_spi_dma_data dma_rx; |
| 199 | struct rockchip_spi_dma_data dma_tx; |
| 200 | }; |
| 201 | |
| 202 | static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) |
| 203 | { |
| 204 | writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); |
| 205 | } |
| 206 | |
| 207 | static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) |
| 208 | { |
| 209 | writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); |
| 210 | } |
| 211 | |
| 212 | static inline void flush_fifo(struct rockchip_spi *rs) |
| 213 | { |
| 214 | while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) |
| 215 | readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); |
| 216 | } |
| 217 | |
Addy Ke | 2df08e7 | 2014-07-11 10:08:24 +0800 | [diff] [blame] | 218 | static inline void wait_for_idle(struct rockchip_spi *rs) |
| 219 | { |
| 220 | unsigned long timeout = jiffies + msecs_to_jiffies(5); |
| 221 | |
| 222 | do { |
| 223 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) |
| 224 | return; |
Doug Anderson | 64bc011 | 2014-09-03 13:44:25 -0700 | [diff] [blame] | 225 | } while (!time_after(jiffies, timeout)); |
Addy Ke | 2df08e7 | 2014-07-11 10:08:24 +0800 | [diff] [blame] | 226 | |
| 227 | dev_warn(rs->dev, "spi controller is in busy state!\n"); |
| 228 | } |
| 229 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 230 | static u32 get_fifo_len(struct rockchip_spi *rs) |
| 231 | { |
| 232 | u32 fifo; |
| 233 | |
| 234 | for (fifo = 2; fifo < 32; fifo++) { |
| 235 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); |
| 236 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) |
| 237 | break; |
| 238 | } |
| 239 | |
| 240 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); |
| 241 | |
| 242 | return (fifo == 31) ? 0 : fifo; |
| 243 | } |
| 244 | |
| 245 | static inline u32 tx_max(struct rockchip_spi *rs) |
| 246 | { |
| 247 | u32 tx_left, tx_room; |
| 248 | |
| 249 | tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; |
| 250 | tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); |
| 251 | |
| 252 | return min(tx_left, tx_room); |
| 253 | } |
| 254 | |
| 255 | static inline u32 rx_max(struct rockchip_spi *rs) |
| 256 | { |
| 257 | u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; |
| 258 | u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); |
| 259 | |
| 260 | return min(rx_left, rx_room); |
| 261 | } |
| 262 | |
| 263 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) |
| 264 | { |
| 265 | u32 ser; |
Huibin Hong | b920cc3 | 2016-02-24 18:00:04 +0800 | [diff] [blame] | 266 | struct spi_master *master = spi->master; |
| 267 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 268 | |
| 269 | pm_runtime_get_sync(rs->dev); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 270 | |
| 271 | ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; |
| 272 | |
| 273 | /* |
| 274 | * drivers/spi/spi.c: |
| 275 | * static void spi_set_cs(struct spi_device *spi, bool enable) |
| 276 | * { |
| 277 | * if (spi->mode & SPI_CS_HIGH) |
| 278 | * enable = !enable; |
| 279 | * |
| 280 | * if (spi->cs_gpio >= 0) |
| 281 | * gpio_set_value(spi->cs_gpio, !enable); |
| 282 | * else if (spi->master->set_cs) |
| 283 | * spi->master->set_cs(spi, !enable); |
| 284 | * } |
| 285 | * |
| 286 | * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) |
| 287 | */ |
| 288 | if (!enable) |
| 289 | ser |= 1 << spi->chip_select; |
| 290 | else |
| 291 | ser &= ~(1 << spi->chip_select); |
| 292 | |
| 293 | writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); |
Huibin Hong | b920cc3 | 2016-02-24 18:00:04 +0800 | [diff] [blame] | 294 | |
| 295 | pm_runtime_put_sync(rs->dev); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | static int rockchip_spi_prepare_message(struct spi_master *master, |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 299 | struct spi_message *msg) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 300 | { |
| 301 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 302 | struct spi_device *spi = msg->spi; |
| 303 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 304 | rs->mode = spi->mode; |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
Andy Shevchenko | 2291793 | 2015-02-27 17:34:16 +0200 | [diff] [blame] | 309 | static void rockchip_spi_handle_err(struct spi_master *master, |
| 310 | struct spi_message *msg) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 311 | { |
| 312 | unsigned long flags; |
| 313 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 314 | |
| 315 | spin_lock_irqsave(&rs->lock, flags); |
| 316 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 317 | /* |
| 318 | * For DMA mode, we need terminate DMA channel and flush |
| 319 | * fifo for the next transfer if DMA thansfer timeout. |
Andy Shevchenko | 2291793 | 2015-02-27 17:34:16 +0200 | [diff] [blame] | 320 | * handle_err() was called by core if transfer failed. |
| 321 | * Maybe it is reasonable for error handling here. |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 322 | */ |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 323 | if (rs->use_dma) { |
| 324 | if (rs->state & RXBUSY) { |
Shawn Lin | 557b7ea | 2016-03-09 16:11:23 +0800 | [diff] [blame] | 325 | dmaengine_terminate_async(rs->dma_rx.ch); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 326 | flush_fifo(rs); |
| 327 | } |
| 328 | |
| 329 | if (rs->state & TXBUSY) |
Shawn Lin | 557b7ea | 2016-03-09 16:11:23 +0800 | [diff] [blame] | 330 | dmaengine_terminate_async(rs->dma_tx.ch); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | spin_unlock_irqrestore(&rs->lock, flags); |
Andy Shevchenko | 2291793 | 2015-02-27 17:34:16 +0200 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static int rockchip_spi_unprepare_message(struct spi_master *master, |
| 337 | struct spi_message *msg) |
| 338 | { |
| 339 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 340 | |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 341 | spi_enable_chip(rs, 0); |
| 342 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) |
| 347 | { |
| 348 | u32 max = tx_max(rs); |
| 349 | u32 txw = 0; |
| 350 | |
| 351 | while (max--) { |
| 352 | if (rs->n_bytes == 1) |
| 353 | txw = *(u8 *)(rs->tx); |
| 354 | else |
| 355 | txw = *(u16 *)(rs->tx); |
| 356 | |
| 357 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); |
| 358 | rs->tx += rs->n_bytes; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) |
| 363 | { |
| 364 | u32 max = rx_max(rs); |
| 365 | u32 rxw; |
| 366 | |
| 367 | while (max--) { |
| 368 | rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); |
| 369 | if (rs->n_bytes == 1) |
| 370 | *(u8 *)(rs->rx) = (u8)rxw; |
| 371 | else |
| 372 | *(u16 *)(rs->rx) = (u16)rxw; |
| 373 | rs->rx += rs->n_bytes; |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 374 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) |
| 378 | { |
| 379 | int remain = 0; |
| 380 | |
| 381 | do { |
| 382 | if (rs->tx) { |
| 383 | remain = rs->tx_end - rs->tx; |
| 384 | rockchip_spi_pio_writer(rs); |
| 385 | } |
| 386 | |
| 387 | if (rs->rx) { |
| 388 | remain = rs->rx_end - rs->rx; |
| 389 | rockchip_spi_pio_reader(rs); |
| 390 | } |
| 391 | |
| 392 | cpu_relax(); |
| 393 | } while (remain); |
| 394 | |
Addy Ke | 2df08e7 | 2014-07-11 10:08:24 +0800 | [diff] [blame] | 395 | /* If tx, wait until the FIFO data completely. */ |
| 396 | if (rs->tx) |
| 397 | wait_for_idle(rs); |
| 398 | |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 399 | spi_enable_chip(rs, 0); |
| 400 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | static void rockchip_spi_dma_rxcb(void *data) |
| 405 | { |
| 406 | unsigned long flags; |
| 407 | struct rockchip_spi *rs = data; |
| 408 | |
| 409 | spin_lock_irqsave(&rs->lock, flags); |
| 410 | |
| 411 | rs->state &= ~RXBUSY; |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 412 | if (!(rs->state & TXBUSY)) { |
| 413 | spi_enable_chip(rs, 0); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 414 | spi_finalize_current_transfer(rs->master); |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 415 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 416 | |
| 417 | spin_unlock_irqrestore(&rs->lock, flags); |
| 418 | } |
| 419 | |
| 420 | static void rockchip_spi_dma_txcb(void *data) |
| 421 | { |
| 422 | unsigned long flags; |
| 423 | struct rockchip_spi *rs = data; |
| 424 | |
Addy Ke | 2df08e7 | 2014-07-11 10:08:24 +0800 | [diff] [blame] | 425 | /* Wait until the FIFO data completely. */ |
| 426 | wait_for_idle(rs); |
| 427 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 428 | spin_lock_irqsave(&rs->lock, flags); |
| 429 | |
| 430 | rs->state &= ~TXBUSY; |
Addy Ke | 2c2bc74 | 2014-10-17 09:44:13 +0800 | [diff] [blame] | 431 | if (!(rs->state & RXBUSY)) { |
| 432 | spi_enable_chip(rs, 0); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 433 | spi_finalize_current_transfer(rs->master); |
Addy Ke | 2c2bc74 | 2014-10-17 09:44:13 +0800 | [diff] [blame] | 434 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 435 | |
| 436 | spin_unlock_irqrestore(&rs->lock, flags); |
| 437 | } |
| 438 | |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 439 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 440 | { |
| 441 | unsigned long flags; |
| 442 | struct dma_slave_config rxconf, txconf; |
| 443 | struct dma_async_tx_descriptor *rxdesc, *txdesc; |
| 444 | |
| 445 | spin_lock_irqsave(&rs->lock, flags); |
| 446 | rs->state &= ~RXBUSY; |
| 447 | rs->state &= ~TXBUSY; |
| 448 | spin_unlock_irqrestore(&rs->lock, flags); |
| 449 | |
Arnd Bergmann | 97cf566 | 2015-01-28 14:25:10 +0100 | [diff] [blame] | 450 | rxdesc = NULL; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 451 | if (rs->rx) { |
| 452 | rxconf.direction = rs->dma_rx.direction; |
| 453 | rxconf.src_addr = rs->dma_rx.addr; |
| 454 | rxconf.src_addr_width = rs->n_bytes; |
| 455 | rxconf.src_maxburst = rs->n_bytes; |
| 456 | dmaengine_slave_config(rs->dma_rx.ch, &rxconf); |
| 457 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 458 | rxdesc = dmaengine_prep_slave_sg( |
| 459 | rs->dma_rx.ch, |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 460 | rs->rx_sg.sgl, rs->rx_sg.nents, |
| 461 | rs->dma_rx.direction, DMA_PREP_INTERRUPT); |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 462 | if (!rxdesc) |
| 463 | return -EINVAL; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 464 | |
| 465 | rxdesc->callback = rockchip_spi_dma_rxcb; |
| 466 | rxdesc->callback_param = rs; |
| 467 | } |
| 468 | |
Arnd Bergmann | 97cf566 | 2015-01-28 14:25:10 +0100 | [diff] [blame] | 469 | txdesc = NULL; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 470 | if (rs->tx) { |
| 471 | txconf.direction = rs->dma_tx.direction; |
| 472 | txconf.dst_addr = rs->dma_tx.addr; |
| 473 | txconf.dst_addr_width = rs->n_bytes; |
| 474 | txconf.dst_maxburst = rs->n_bytes; |
| 475 | dmaengine_slave_config(rs->dma_tx.ch, &txconf); |
| 476 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 477 | txdesc = dmaengine_prep_slave_sg( |
| 478 | rs->dma_tx.ch, |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 479 | rs->tx_sg.sgl, rs->tx_sg.nents, |
| 480 | rs->dma_tx.direction, DMA_PREP_INTERRUPT); |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 481 | if (!txdesc) { |
| 482 | if (rxdesc) |
| 483 | dmaengine_terminate_sync(rs->dma_rx.ch); |
| 484 | return -EINVAL; |
| 485 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 486 | |
| 487 | txdesc->callback = rockchip_spi_dma_txcb; |
| 488 | txdesc->callback_param = rs; |
| 489 | } |
| 490 | |
| 491 | /* rx must be started before tx due to spi instinct */ |
Arnd Bergmann | 97cf566 | 2015-01-28 14:25:10 +0100 | [diff] [blame] | 492 | if (rxdesc) { |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 493 | spin_lock_irqsave(&rs->lock, flags); |
| 494 | rs->state |= RXBUSY; |
| 495 | spin_unlock_irqrestore(&rs->lock, flags); |
| 496 | dmaengine_submit(rxdesc); |
| 497 | dma_async_issue_pending(rs->dma_rx.ch); |
| 498 | } |
| 499 | |
Arnd Bergmann | 97cf566 | 2015-01-28 14:25:10 +0100 | [diff] [blame] | 500 | if (txdesc) { |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 501 | spin_lock_irqsave(&rs->lock, flags); |
| 502 | rs->state |= TXBUSY; |
| 503 | spin_unlock_irqrestore(&rs->lock, flags); |
| 504 | dmaengine_submit(txdesc); |
| 505 | dma_async_issue_pending(rs->dma_tx.ch); |
| 506 | } |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 507 | |
| 508 | return 0; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 509 | } |
| 510 | |
| 511 | static void rockchip_spi_config(struct rockchip_spi *rs) |
| 512 | { |
| 513 | u32 div = 0; |
| 514 | u32 dmacr = 0; |
Julius Werner | 76b17e6 | 2015-03-26 16:30:25 -0700 | [diff] [blame] | 515 | int rsd = 0; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 516 | |
| 517 | u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) |
Alexander Kochetkov | 0277e01 | 2016-03-06 13:04:17 +0300 | [diff] [blame] | 518 | | (CR0_SSD_ONE << CR0_SSD_OFFSET) |
| 519 | | (CR0_EM_BIG << CR0_EM_OFFSET); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 520 | |
| 521 | cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); |
| 522 | cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); |
| 523 | cr0 |= (rs->tmode << CR0_XFM_OFFSET); |
| 524 | cr0 |= (rs->type << CR0_FRF_OFFSET); |
| 525 | |
| 526 | if (rs->use_dma) { |
| 527 | if (rs->tx) |
| 528 | dmacr |= TF_DMA_EN; |
| 529 | if (rs->rx) |
| 530 | dmacr |= RF_DMA_EN; |
| 531 | } |
| 532 | |
Addy Ke | f9cfd52 | 2014-10-15 19:25:49 +0800 | [diff] [blame] | 533 | if (WARN_ON(rs->speed > MAX_SCLK_OUT)) |
| 534 | rs->speed = MAX_SCLK_OUT; |
| 535 | |
| 536 | /* the minimum divsor is 2 */ |
| 537 | if (rs->max_freq < 2 * rs->speed) { |
| 538 | clk_set_rate(rs->spiclk, 2 * rs->speed); |
| 539 | rs->max_freq = clk_get_rate(rs->spiclk); |
| 540 | } |
| 541 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 542 | /* div doesn't support odd number */ |
Julius Werner | 754ec43 | 2015-03-26 16:30:24 -0700 | [diff] [blame] | 543 | div = DIV_ROUND_UP(rs->max_freq, rs->speed); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 544 | div = (div + 1) & 0xfffe; |
| 545 | |
Julius Werner | 76b17e6 | 2015-03-26 16:30:25 -0700 | [diff] [blame] | 546 | /* Rx sample delay is expressed in parent clock cycles (max 3) */ |
| 547 | rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), |
| 548 | 1000000000 >> 8); |
| 549 | if (!rsd && rs->rsd_nsecs) { |
| 550 | pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", |
| 551 | rs->max_freq, rs->rsd_nsecs); |
| 552 | } else if (rsd > 3) { |
| 553 | rsd = 3; |
| 554 | pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", |
| 555 | rs->max_freq, rs->rsd_nsecs, |
| 556 | rsd * 1000000000U / rs->max_freq); |
| 557 | } |
| 558 | cr0 |= rsd << CR0_RSD_OFFSET; |
| 559 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 560 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
| 561 | |
| 562 | writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); |
| 563 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); |
| 564 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); |
| 565 | |
| 566 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); |
| 567 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); |
| 568 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); |
| 569 | |
| 570 | spi_set_clk(rs, div); |
| 571 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 572 | dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 573 | } |
| 574 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 575 | static int rockchip_spi_transfer_one( |
| 576 | struct spi_master *master, |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 577 | struct spi_device *spi, |
| 578 | struct spi_transfer *xfer) |
| 579 | { |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 580 | int ret = 1; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 581 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 582 | |
Doug Anderson | 6294617 | 2014-09-03 13:44:26 -0700 | [diff] [blame] | 583 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
| 584 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 585 | |
| 586 | if (!xfer->tx_buf && !xfer->rx_buf) { |
| 587 | dev_err(rs->dev, "No buffer for transfer\n"); |
| 588 | return -EINVAL; |
| 589 | } |
| 590 | |
| 591 | rs->speed = xfer->speed_hz; |
| 592 | rs->bpw = xfer->bits_per_word; |
| 593 | rs->n_bytes = rs->bpw >> 3; |
| 594 | |
| 595 | rs->tx = xfer->tx_buf; |
| 596 | rs->tx_end = rs->tx + xfer->len; |
| 597 | rs->rx = xfer->rx_buf; |
| 598 | rs->rx_end = rs->rx + xfer->len; |
| 599 | rs->len = xfer->len; |
| 600 | |
| 601 | rs->tx_sg = xfer->tx_sg; |
| 602 | rs->rx_sg = xfer->rx_sg; |
| 603 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 604 | if (rs->tx && rs->rx) |
| 605 | rs->tmode = CR0_XFM_TR; |
| 606 | else if (rs->tx) |
| 607 | rs->tmode = CR0_XFM_TO; |
| 608 | else if (rs->rx) |
| 609 | rs->tmode = CR0_XFM_RO; |
| 610 | |
Addy Ke | a24e70c | 2014-09-25 14:59:41 +0800 | [diff] [blame] | 611 | /* we need prepare dma before spi was enabled */ |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 612 | if (master->can_dma && master->can_dma(master, spi, xfer)) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 613 | rs->use_dma = 1; |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 614 | else |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 615 | rs->use_dma = 0; |
| 616 | |
| 617 | rockchip_spi_config(rs); |
| 618 | |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 619 | if (rs->use_dma) { |
| 620 | if (rs->tmode == CR0_XFM_RO) { |
| 621 | /* rx: dma must be prepared first */ |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 622 | ret = rockchip_spi_prepare_dma(rs); |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 623 | spi_enable_chip(rs, 1); |
| 624 | } else { |
| 625 | /* tx or tr: spi must be enabled first */ |
| 626 | spi_enable_chip(rs, 1); |
Shawn Lin | ea98491 | 2016-03-09 16:11:15 +0800 | [diff] [blame] | 627 | ret = rockchip_spi_prepare_dma(rs); |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 628 | } |
| 629 | } else { |
| 630 | spi_enable_chip(rs, 1); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 631 | ret = rockchip_spi_pio_transfer(rs); |
Addy Ke | c28be31 | 2014-10-15 19:26:18 +0800 | [diff] [blame] | 632 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 633 | |
| 634 | return ret; |
| 635 | } |
| 636 | |
| 637 | static bool rockchip_spi_can_dma(struct spi_master *master, |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 638 | struct spi_device *spi, |
| 639 | struct spi_transfer *xfer) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 640 | { |
| 641 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 642 | |
| 643 | return (xfer->len > rs->fifo_len); |
| 644 | } |
| 645 | |
| 646 | static int rockchip_spi_probe(struct platform_device *pdev) |
| 647 | { |
| 648 | int ret = 0; |
| 649 | struct rockchip_spi *rs; |
| 650 | struct spi_master *master; |
| 651 | struct resource *mem; |
Julius Werner | 76b17e6 | 2015-03-26 16:30:25 -0700 | [diff] [blame] | 652 | u32 rsd_nsecs; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 653 | |
| 654 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 655 | if (!master) |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 656 | return -ENOMEM; |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 657 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 658 | platform_set_drvdata(pdev, master); |
| 659 | |
| 660 | rs = spi_master_get_devdata(master); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 661 | |
| 662 | /* Get basic io resource and map it */ |
| 663 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 664 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); |
| 665 | if (IS_ERR(rs->regs)) { |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 666 | ret = PTR_ERR(rs->regs); |
| 667 | goto err_ioremap_resource; |
| 668 | } |
| 669 | |
| 670 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
| 671 | if (IS_ERR(rs->apb_pclk)) { |
| 672 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); |
| 673 | ret = PTR_ERR(rs->apb_pclk); |
| 674 | goto err_ioremap_resource; |
| 675 | } |
| 676 | |
| 677 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); |
| 678 | if (IS_ERR(rs->spiclk)) { |
| 679 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); |
| 680 | ret = PTR_ERR(rs->spiclk); |
| 681 | goto err_ioremap_resource; |
| 682 | } |
| 683 | |
| 684 | ret = clk_prepare_enable(rs->apb_pclk); |
| 685 | if (ret) { |
| 686 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); |
| 687 | goto err_ioremap_resource; |
| 688 | } |
| 689 | |
| 690 | ret = clk_prepare_enable(rs->spiclk); |
| 691 | if (ret) { |
| 692 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); |
| 693 | goto err_spiclk_enable; |
| 694 | } |
| 695 | |
| 696 | spi_enable_chip(rs, 0); |
| 697 | |
| 698 | rs->type = SSI_MOTO_SPI; |
| 699 | rs->master = master; |
| 700 | rs->dev = &pdev->dev; |
| 701 | rs->max_freq = clk_get_rate(rs->spiclk); |
| 702 | |
Julius Werner | 76b17e6 | 2015-03-26 16:30:25 -0700 | [diff] [blame] | 703 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
| 704 | &rsd_nsecs)) |
| 705 | rs->rsd_nsecs = rsd_nsecs; |
| 706 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 707 | rs->fifo_len = get_fifo_len(rs); |
| 708 | if (!rs->fifo_len) { |
| 709 | dev_err(&pdev->dev, "Failed to get fifo length\n"); |
Wei Yongjun | db7e8d9 | 2014-07-20 22:02:04 +0800 | [diff] [blame] | 710 | ret = -EINVAL; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 711 | goto err_get_fifo_len; |
| 712 | } |
| 713 | |
| 714 | spin_lock_init(&rs->lock); |
| 715 | |
| 716 | pm_runtime_set_active(&pdev->dev); |
| 717 | pm_runtime_enable(&pdev->dev); |
| 718 | |
| 719 | master->auto_runtime_pm = true; |
| 720 | master->bus_num = pdev->id; |
Addy Ke | ee78099 | 2014-07-11 10:08:51 +0800 | [diff] [blame] | 721 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 722 | master->num_chipselect = 2; |
| 723 | master->dev.of_node = pdev->dev.of_node; |
| 724 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); |
| 725 | |
| 726 | master->set_cs = rockchip_spi_set_cs; |
| 727 | master->prepare_message = rockchip_spi_prepare_message; |
| 728 | master->unprepare_message = rockchip_spi_unprepare_message; |
| 729 | master->transfer_one = rockchip_spi_transfer_one; |
Andy Shevchenko | 2291793 | 2015-02-27 17:34:16 +0200 | [diff] [blame] | 730 | master->handle_err = rockchip_spi_handle_err; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 731 | |
| 732 | rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); |
Shawn Lin | 61cadcf | 2016-03-09 16:11:32 +0800 | [diff] [blame^] | 733 | if (IS_ERR_OR_NULL(rs->dma_tx.ch)) { |
| 734 | /* Check tx to see if we need defer probing driver */ |
| 735 | if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) { |
| 736 | ret = -EPROBE_DEFER; |
| 737 | goto err_get_fifo_len; |
| 738 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 739 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
Shawn Lin | 61cadcf | 2016-03-09 16:11:32 +0800 | [diff] [blame^] | 740 | } |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 741 | |
| 742 | rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); |
| 743 | if (!rs->dma_rx.ch) { |
| 744 | if (rs->dma_tx.ch) { |
| 745 | dma_release_channel(rs->dma_tx.ch); |
| 746 | rs->dma_tx.ch = NULL; |
| 747 | } |
| 748 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); |
| 749 | } |
| 750 | |
| 751 | if (rs->dma_tx.ch && rs->dma_rx.ch) { |
| 752 | rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); |
| 753 | rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); |
| 754 | rs->dma_tx.direction = DMA_MEM_TO_DEV; |
Addy Ke | 0ac7a49 | 2014-08-20 11:47:42 +0800 | [diff] [blame] | 755 | rs->dma_rx.direction = DMA_DEV_TO_MEM; |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 756 | |
| 757 | master->can_dma = rockchip_spi_can_dma; |
| 758 | master->dma_tx = rs->dma_tx.ch; |
| 759 | master->dma_rx = rs->dma_rx.ch; |
| 760 | } |
| 761 | |
| 762 | ret = devm_spi_register_master(&pdev->dev, master); |
| 763 | if (ret) { |
| 764 | dev_err(&pdev->dev, "Failed to register master\n"); |
| 765 | goto err_register_master; |
| 766 | } |
| 767 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 768 | return 0; |
| 769 | |
| 770 | err_register_master: |
| 771 | if (rs->dma_tx.ch) |
| 772 | dma_release_channel(rs->dma_tx.ch); |
| 773 | if (rs->dma_rx.ch) |
| 774 | dma_release_channel(rs->dma_rx.ch); |
| 775 | err_get_fifo_len: |
| 776 | clk_disable_unprepare(rs->spiclk); |
| 777 | err_spiclk_enable: |
| 778 | clk_disable_unprepare(rs->apb_pclk); |
| 779 | err_ioremap_resource: |
| 780 | spi_master_put(master); |
| 781 | |
| 782 | return ret; |
| 783 | } |
| 784 | |
| 785 | static int rockchip_spi_remove(struct platform_device *pdev) |
| 786 | { |
| 787 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
| 788 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 789 | |
| 790 | pm_runtime_disable(&pdev->dev); |
| 791 | |
| 792 | clk_disable_unprepare(rs->spiclk); |
| 793 | clk_disable_unprepare(rs->apb_pclk); |
| 794 | |
| 795 | if (rs->dma_tx.ch) |
| 796 | dma_release_channel(rs->dma_tx.ch); |
| 797 | if (rs->dma_rx.ch) |
| 798 | dma_release_channel(rs->dma_rx.ch); |
| 799 | |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 800 | return 0; |
| 801 | } |
| 802 | |
| 803 | #ifdef CONFIG_PM_SLEEP |
| 804 | static int rockchip_spi_suspend(struct device *dev) |
| 805 | { |
| 806 | int ret = 0; |
| 807 | struct spi_master *master = dev_get_drvdata(dev); |
| 808 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 809 | |
| 810 | ret = spi_master_suspend(rs->master); |
| 811 | if (ret) |
| 812 | return ret; |
| 813 | |
| 814 | if (!pm_runtime_suspended(dev)) { |
| 815 | clk_disable_unprepare(rs->spiclk); |
| 816 | clk_disable_unprepare(rs->apb_pclk); |
| 817 | } |
| 818 | |
| 819 | return ret; |
| 820 | } |
| 821 | |
| 822 | static int rockchip_spi_resume(struct device *dev) |
| 823 | { |
| 824 | int ret = 0; |
| 825 | struct spi_master *master = dev_get_drvdata(dev); |
| 826 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 827 | |
| 828 | if (!pm_runtime_suspended(dev)) { |
| 829 | ret = clk_prepare_enable(rs->apb_pclk); |
| 830 | if (ret < 0) |
| 831 | return ret; |
| 832 | |
| 833 | ret = clk_prepare_enable(rs->spiclk); |
| 834 | if (ret < 0) { |
| 835 | clk_disable_unprepare(rs->apb_pclk); |
| 836 | return ret; |
| 837 | } |
| 838 | } |
| 839 | |
| 840 | ret = spi_master_resume(rs->master); |
| 841 | if (ret < 0) { |
| 842 | clk_disable_unprepare(rs->spiclk); |
| 843 | clk_disable_unprepare(rs->apb_pclk); |
| 844 | } |
| 845 | |
| 846 | return ret; |
| 847 | } |
| 848 | #endif /* CONFIG_PM_SLEEP */ |
| 849 | |
Rafael J. Wysocki | ec83305 | 2014-12-13 00:41:15 +0100 | [diff] [blame] | 850 | #ifdef CONFIG_PM |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 851 | static int rockchip_spi_runtime_suspend(struct device *dev) |
| 852 | { |
| 853 | struct spi_master *master = dev_get_drvdata(dev); |
| 854 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 855 | |
| 856 | clk_disable_unprepare(rs->spiclk); |
| 857 | clk_disable_unprepare(rs->apb_pclk); |
| 858 | |
| 859 | return 0; |
| 860 | } |
| 861 | |
| 862 | static int rockchip_spi_runtime_resume(struct device *dev) |
| 863 | { |
| 864 | int ret; |
| 865 | struct spi_master *master = dev_get_drvdata(dev); |
| 866 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
| 867 | |
| 868 | ret = clk_prepare_enable(rs->apb_pclk); |
| 869 | if (ret) |
| 870 | return ret; |
| 871 | |
| 872 | ret = clk_prepare_enable(rs->spiclk); |
| 873 | if (ret) |
| 874 | clk_disable_unprepare(rs->apb_pclk); |
| 875 | |
| 876 | return ret; |
| 877 | } |
Rafael J. Wysocki | ec83305 | 2014-12-13 00:41:15 +0100 | [diff] [blame] | 878 | #endif /* CONFIG_PM */ |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 879 | |
| 880 | static const struct dev_pm_ops rockchip_spi_pm = { |
| 881 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) |
| 882 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, |
| 883 | rockchip_spi_runtime_resume, NULL) |
| 884 | }; |
| 885 | |
| 886 | static const struct of_device_id rockchip_spi_dt_match[] = { |
| 887 | { .compatible = "rockchip,rk3066-spi", }, |
Addy Ke | b839b78 | 2014-07-11 10:09:19 +0800 | [diff] [blame] | 888 | { .compatible = "rockchip,rk3188-spi", }, |
| 889 | { .compatible = "rockchip,rk3288-spi", }, |
Xu Jianqun | 9b7a562 | 2016-02-18 19:16:31 +0800 | [diff] [blame] | 890 | { .compatible = "rockchip,rk3399-spi", }, |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 891 | { }, |
| 892 | }; |
| 893 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); |
| 894 | |
| 895 | static struct platform_driver rockchip_spi_driver = { |
| 896 | .driver = { |
| 897 | .name = DRIVER_NAME, |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 898 | .pm = &rockchip_spi_pm, |
| 899 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), |
| 900 | }, |
| 901 | .probe = rockchip_spi_probe, |
| 902 | .remove = rockchip_spi_remove, |
| 903 | }; |
| 904 | |
| 905 | module_platform_driver(rockchip_spi_driver); |
| 906 | |
Addy Ke | 5dcc44e | 2014-07-11 10:07:56 +0800 | [diff] [blame] | 907 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
addy ke | 64e3682 | 2014-07-01 09:03:59 +0800 | [diff] [blame] | 908 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
| 909 | MODULE_LICENSE("GPL v2"); |