John Linn | 61ec901 | 2011-04-30 00:07:43 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * Xilinx PS UART driver |
| 3 | * |
| 4 | * 2011 (c) Xilinx Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it |
| 7 | * and/or modify it under the terms of the GNU General Public |
| 8 | * License as published by the Free Software Foundation; |
| 9 | * either version 2 of the License, or (at your option) any |
| 10 | * later version. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/serial_core.h> |
| 16 | #include <linux/console.h> |
| 17 | #include <linux/serial.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/of.h> |
| 21 | |
| 22 | #define XUARTPS_TTY_NAME "ttyPS" |
| 23 | #define XUARTPS_NAME "xuartps" |
| 24 | #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ |
| 25 | #define XUARTPS_MINOR 0 /* works best with devtmpfs */ |
| 26 | #define XUARTPS_NR_PORTS 2 |
| 27 | #define XUARTPS_FIFO_SIZE 16 /* FIFO size */ |
| 28 | #define XUARTPS_REGISTER_SPACE 0xFFF |
| 29 | |
| 30 | #define xuartps_readl(offset) ioread32(port->membase + offset) |
| 31 | #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) |
| 32 | |
| 33 | /********************************Register Map********************************/ |
| 34 | /** UART |
| 35 | * |
| 36 | * Register offsets for the UART. |
| 37 | * |
| 38 | */ |
| 39 | #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ |
| 40 | #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ |
| 41 | #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ |
| 42 | #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ |
| 43 | #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ |
| 44 | #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ |
| 45 | #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ |
| 46 | #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ |
| 47 | #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ |
| 48 | #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ |
| 49 | #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ |
| 50 | #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ |
| 51 | #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ |
| 52 | #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ |
| 53 | #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ |
| 54 | #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse |
| 55 | Width [15:0] */ |
| 56 | #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse |
| 57 | Width [7:0] */ |
| 58 | #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ |
| 59 | |
| 60 | /** Control Register |
| 61 | * |
| 62 | * The Control register (CR) controls the major functions of the device. |
| 63 | * |
| 64 | * Control Register Bit Definitions |
| 65 | */ |
| 66 | #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ |
| 67 | #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ |
| 68 | #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ |
| 69 | #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ |
| 70 | #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ |
| 71 | #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ |
| 72 | #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ |
| 73 | #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ |
| 74 | #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ |
| 75 | |
| 76 | /** Mode Register |
| 77 | * |
| 78 | * The mode register (MR) defines the mode of transfer as well as the data |
| 79 | * format. If this register is modified during transmission or reception, |
| 80 | * data validity cannot be guaranteed. |
| 81 | * |
| 82 | * Mode Register Bit Definitions |
| 83 | * |
| 84 | */ |
| 85 | #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ |
| 86 | #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ |
| 87 | #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ |
| 88 | |
| 89 | #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ |
| 90 | #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ |
| 91 | |
| 92 | #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
| 93 | #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ |
| 94 | #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ |
| 95 | #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ |
| 96 | #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ |
| 97 | |
| 98 | #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ |
| 99 | #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ |
| 100 | #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ |
| 101 | |
| 102 | /** Interrupt Registers |
| 103 | * |
| 104 | * Interrupt control logic uses the interrupt enable register (IER) and the |
| 105 | * interrupt disable register (IDR) to set the value of the bits in the |
| 106 | * interrupt mask register (IMR). The IMR determines whether to pass an |
| 107 | * interrupt to the interrupt status register (ISR). |
| 108 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an |
| 109 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. |
| 110 | * Reading either IER or IDR returns 0x00. |
| 111 | * |
| 112 | * All four registers have the same bit definitions. |
| 113 | */ |
| 114 | #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ |
| 115 | #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ |
| 116 | #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ |
| 117 | #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ |
| 118 | #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ |
| 119 | #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ |
| 120 | #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ |
| 121 | #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ |
| 122 | #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ |
| 123 | #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ |
| 124 | #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ |
| 125 | |
| 126 | /** Channel Status Register |
| 127 | * |
| 128 | * The channel status register (CSR) is provided to enable the control logic |
| 129 | * to monitor the status of bits in the channel interrupt status register, |
| 130 | * even if these are masked out by the interrupt mask register. |
| 131 | */ |
| 132 | #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
| 133 | #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ |
| 134 | #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ |
| 135 | #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ |
| 136 | |
| 137 | /** |
| 138 | * xuartps_isr - Interrupt handler |
| 139 | * @irq: Irq number |
| 140 | * @dev_id: Id of the port |
| 141 | * |
| 142 | * Returns IRQHANDLED |
| 143 | **/ |
| 144 | static irqreturn_t xuartps_isr(int irq, void *dev_id) |
| 145 | { |
| 146 | struct uart_port *port = (struct uart_port *)dev_id; |
| 147 | struct tty_struct *tty; |
| 148 | unsigned long flags; |
| 149 | unsigned int isrstatus, numbytes; |
| 150 | unsigned int data; |
| 151 | char status = TTY_NORMAL; |
| 152 | |
| 153 | /* Get the tty which could be NULL so don't assume it's valid */ |
| 154 | tty = tty_port_tty_get(&port->state->port); |
| 155 | |
| 156 | spin_lock_irqsave(&port->lock, flags); |
| 157 | |
| 158 | /* Read the interrupt status register to determine which |
| 159 | * interrupt(s) is/are active. |
| 160 | */ |
| 161 | isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); |
| 162 | |
| 163 | /* drop byte with parity error if IGNPAR specified */ |
| 164 | if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) |
| 165 | isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); |
| 166 | |
| 167 | isrstatus &= port->read_status_mask; |
| 168 | isrstatus &= ~port->ignore_status_mask; |
| 169 | |
| 170 | if ((isrstatus & XUARTPS_IXR_TOUT) || |
| 171 | (isrstatus & XUARTPS_IXR_RXTRIG)) { |
| 172 | /* Receive Timeout Interrupt */ |
| 173 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & |
| 174 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { |
| 175 | data = xuartps_readl(XUARTPS_FIFO_OFFSET); |
| 176 | port->icount.rx++; |
| 177 | |
| 178 | if (isrstatus & XUARTPS_IXR_PARITY) { |
| 179 | port->icount.parity++; |
| 180 | status = TTY_PARITY; |
| 181 | } else if (isrstatus & XUARTPS_IXR_FRAMING) { |
| 182 | port->icount.frame++; |
| 183 | status = TTY_FRAME; |
| 184 | } else if (isrstatus & XUARTPS_IXR_OVERRUN) |
| 185 | port->icount.overrun++; |
| 186 | |
| 187 | if (tty) |
| 188 | uart_insert_char(port, isrstatus, |
| 189 | XUARTPS_IXR_OVERRUN, data, |
| 190 | status); |
| 191 | } |
| 192 | spin_unlock(&port->lock); |
| 193 | if (tty) |
| 194 | tty_flip_buffer_push(tty); |
| 195 | spin_lock(&port->lock); |
| 196 | } |
| 197 | |
| 198 | /* Dispatch an appropriate handler */ |
| 199 | if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { |
| 200 | if (uart_circ_empty(&port->state->xmit)) { |
| 201 | xuartps_writel(XUARTPS_IXR_TXEMPTY, |
| 202 | XUARTPS_IDR_OFFSET); |
| 203 | } else { |
| 204 | numbytes = port->fifosize; |
| 205 | /* Break if no more data available in the UART buffer */ |
| 206 | while (numbytes--) { |
| 207 | if (uart_circ_empty(&port->state->xmit)) |
| 208 | break; |
| 209 | /* Get the data from the UART circular buffer |
| 210 | * and write it to the xuartps's TX_FIFO |
| 211 | * register. |
| 212 | */ |
| 213 | xuartps_writel( |
| 214 | port->state->xmit.buf[port->state->xmit. |
| 215 | tail], XUARTPS_FIFO_OFFSET); |
| 216 | |
| 217 | port->icount.tx++; |
| 218 | |
| 219 | /* Adjust the tail of the UART buffer and wrap |
| 220 | * the buffer if it reaches limit. |
| 221 | */ |
| 222 | port->state->xmit.tail = |
| 223 | (port->state->xmit.tail + 1) & \ |
| 224 | (UART_XMIT_SIZE - 1); |
| 225 | } |
| 226 | |
| 227 | if (uart_circ_chars_pending( |
| 228 | &port->state->xmit) < WAKEUP_CHARS) |
| 229 | uart_write_wakeup(port); |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); |
| 234 | |
| 235 | /* be sure to release the lock and tty before leaving */ |
| 236 | spin_unlock_irqrestore(&port->lock, flags); |
| 237 | tty_kref_put(tty); |
| 238 | |
| 239 | return IRQ_HANDLED; |
| 240 | } |
| 241 | |
| 242 | /** |
| 243 | * xuartps_set_baud_rate - Calculate and set the baud rate |
| 244 | * @port: Handle to the uart port structure |
| 245 | * @baud: Baud rate to set |
| 246 | * |
| 247 | * Returns baud rate, requested baud when possible, or actual baud when there |
| 248 | * was too much error |
| 249 | **/ |
| 250 | static unsigned int xuartps_set_baud_rate(struct uart_port *port, |
| 251 | unsigned int baud) |
| 252 | { |
| 253 | unsigned int sel_clk; |
| 254 | unsigned int calc_baud = 0; |
| 255 | unsigned int brgr_val, brdiv_val; |
| 256 | unsigned int bauderror; |
| 257 | |
| 258 | /* Formula to obtain baud rate is |
| 259 | * baud_tx/rx rate = sel_clk/CD * (BDIV + 1) |
| 260 | * input_clk = (Uart User Defined Clock or Apb Clock) |
| 261 | * depends on UCLKEN in MR Reg |
| 262 | * sel_clk = input_clk or input_clk/8; |
| 263 | * depends on CLKS in MR reg |
| 264 | * CD and BDIV depends on values in |
| 265 | * baud rate generate register |
| 266 | * baud rate clock divisor register |
| 267 | */ |
| 268 | sel_clk = port->uartclk; |
| 269 | if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL) |
| 270 | sel_clk = sel_clk / 8; |
| 271 | |
| 272 | /* Find the best values for baud generation */ |
| 273 | for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) { |
| 274 | |
| 275 | brgr_val = sel_clk / (baud * (brdiv_val + 1)); |
| 276 | if (brgr_val < 2 || brgr_val > 65535) |
| 277 | continue; |
| 278 | |
| 279 | calc_baud = sel_clk / (brgr_val * (brdiv_val + 1)); |
| 280 | |
| 281 | if (baud > calc_baud) |
| 282 | bauderror = baud - calc_baud; |
| 283 | else |
| 284 | bauderror = calc_baud - baud; |
| 285 | |
| 286 | /* use the values when percent error is acceptable */ |
| 287 | if (((bauderror * 100) / baud) < 3) { |
| 288 | calc_baud = baud; |
| 289 | break; |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* Set the values for the new baud rate */ |
| 294 | xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET); |
| 295 | xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET); |
| 296 | |
| 297 | return calc_baud; |
| 298 | } |
| 299 | |
| 300 | /*----------------------Uart Operations---------------------------*/ |
| 301 | |
| 302 | /** |
| 303 | * xuartps_start_tx - Start transmitting bytes |
| 304 | * @port: Handle to the uart port structure |
| 305 | * |
| 306 | **/ |
| 307 | static void xuartps_start_tx(struct uart_port *port) |
| 308 | { |
| 309 | unsigned int status, numbytes = port->fifosize; |
| 310 | |
| 311 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) |
| 312 | return; |
| 313 | |
| 314 | status = xuartps_readl(XUARTPS_CR_OFFSET); |
| 315 | /* Set the TX enable bit and clear the TX disable bit to enable the |
| 316 | * transmitter. |
| 317 | */ |
| 318 | xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, |
| 319 | XUARTPS_CR_OFFSET); |
| 320 | |
| 321 | while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) |
| 322 | & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { |
| 323 | |
| 324 | /* Break if no more data available in the UART buffer */ |
| 325 | if (uart_circ_empty(&port->state->xmit)) |
| 326 | break; |
| 327 | |
| 328 | /* Get the data from the UART circular buffer and |
| 329 | * write it to the xuartps's TX_FIFO register. |
| 330 | */ |
| 331 | xuartps_writel( |
| 332 | port->state->xmit.buf[port->state->xmit.tail], |
| 333 | XUARTPS_FIFO_OFFSET); |
| 334 | port->icount.tx++; |
| 335 | |
| 336 | /* Adjust the tail of the UART buffer and wrap |
| 337 | * the buffer if it reaches limit. |
| 338 | */ |
| 339 | port->state->xmit.tail = (port->state->xmit.tail + 1) & |
| 340 | (UART_XMIT_SIZE - 1); |
| 341 | } |
| 342 | |
| 343 | /* Enable the TX Empty interrupt */ |
| 344 | xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); |
| 345 | |
| 346 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) |
| 347 | uart_write_wakeup(port); |
| 348 | } |
| 349 | |
| 350 | /** |
| 351 | * xuartps_stop_tx - Stop TX |
| 352 | * @port: Handle to the uart port structure |
| 353 | * |
| 354 | **/ |
| 355 | static void xuartps_stop_tx(struct uart_port *port) |
| 356 | { |
| 357 | unsigned int regval; |
| 358 | |
| 359 | regval = xuartps_readl(XUARTPS_CR_OFFSET); |
| 360 | regval |= XUARTPS_CR_TX_DIS; |
| 361 | /* Disable the transmitter */ |
| 362 | xuartps_writel(regval, XUARTPS_CR_OFFSET); |
| 363 | } |
| 364 | |
| 365 | /** |
| 366 | * xuartps_stop_rx - Stop RX |
| 367 | * @port: Handle to the uart port structure |
| 368 | * |
| 369 | **/ |
| 370 | static void xuartps_stop_rx(struct uart_port *port) |
| 371 | { |
| 372 | unsigned int regval; |
| 373 | |
| 374 | regval = xuartps_readl(XUARTPS_CR_OFFSET); |
| 375 | regval |= XUARTPS_CR_RX_DIS; |
| 376 | /* Disable the receiver */ |
| 377 | xuartps_writel(regval, XUARTPS_CR_OFFSET); |
| 378 | } |
| 379 | |
| 380 | /** |
| 381 | * xuartps_tx_empty - Check whether TX is empty |
| 382 | * @port: Handle to the uart port structure |
| 383 | * |
| 384 | * Returns TIOCSER_TEMT on success, 0 otherwise |
| 385 | **/ |
| 386 | static unsigned int xuartps_tx_empty(struct uart_port *port) |
| 387 | { |
| 388 | unsigned int status; |
| 389 | |
| 390 | status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; |
| 391 | return status ? TIOCSER_TEMT : 0; |
| 392 | } |
| 393 | |
| 394 | /** |
| 395 | * xuartps_break_ctl - Based on the input ctl we have to start or stop |
| 396 | * transmitting char breaks |
| 397 | * @port: Handle to the uart port structure |
| 398 | * @ctl: Value based on which start or stop decision is taken |
| 399 | * |
| 400 | **/ |
| 401 | static void xuartps_break_ctl(struct uart_port *port, int ctl) |
| 402 | { |
| 403 | unsigned int status; |
| 404 | unsigned long flags; |
| 405 | |
| 406 | spin_lock_irqsave(&port->lock, flags); |
| 407 | |
| 408 | status = xuartps_readl(XUARTPS_CR_OFFSET); |
| 409 | |
| 410 | if (ctl == -1) |
| 411 | xuartps_writel(XUARTPS_CR_STARTBRK | status, |
| 412 | XUARTPS_CR_OFFSET); |
| 413 | else { |
| 414 | if ((status & XUARTPS_CR_STOPBRK) == 0) |
| 415 | xuartps_writel(XUARTPS_CR_STOPBRK | status, |
| 416 | XUARTPS_CR_OFFSET); |
| 417 | } |
| 418 | spin_unlock_irqrestore(&port->lock, flags); |
| 419 | } |
| 420 | |
| 421 | /** |
| 422 | * xuartps_set_termios - termios operations, handling data length, parity, |
| 423 | * stop bits, flow control, baud rate |
| 424 | * @port: Handle to the uart port structure |
| 425 | * @termios: Handle to the input termios structure |
| 426 | * @old: Values of the previously saved termios structure |
| 427 | * |
| 428 | **/ |
| 429 | static void xuartps_set_termios(struct uart_port *port, |
| 430 | struct ktermios *termios, struct ktermios *old) |
| 431 | { |
| 432 | unsigned int cval = 0; |
| 433 | unsigned int baud; |
| 434 | unsigned long flags; |
| 435 | unsigned int ctrl_reg, mode_reg; |
| 436 | |
| 437 | spin_lock_irqsave(&port->lock, flags); |
| 438 | |
| 439 | /* Empty the receive FIFO 1st before making changes */ |
| 440 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & |
| 441 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { |
| 442 | xuartps_readl(XUARTPS_FIFO_OFFSET); |
| 443 | } |
| 444 | |
| 445 | /* Disable the TX and RX to set baud rate */ |
| 446 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | |
| 447 | (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), |
| 448 | XUARTPS_CR_OFFSET); |
| 449 | |
| 450 | /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */ |
| 451 | baud = uart_get_baud_rate(port, termios, old, 0, 10000000); |
| 452 | baud = xuartps_set_baud_rate(port, baud); |
| 453 | if (tty_termios_baud_rate(termios)) |
| 454 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 455 | |
| 456 | /* |
| 457 | * Update the per-port timeout. |
| 458 | */ |
| 459 | uart_update_timeout(port, termios->c_cflag, baud); |
| 460 | |
| 461 | /* Set TX/RX Reset */ |
| 462 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | |
| 463 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), |
| 464 | XUARTPS_CR_OFFSET); |
| 465 | |
| 466 | ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); |
| 467 | |
| 468 | /* Clear the RX disable and TX disable bits and then set the TX enable |
| 469 | * bit and RX enable bit to enable the transmitter and receiver. |
| 470 | */ |
| 471 | xuartps_writel( |
| 472 | (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
| 473 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), |
| 474 | XUARTPS_CR_OFFSET); |
| 475 | |
| 476 | xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); |
| 477 | |
| 478 | port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | |
| 479 | XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; |
| 480 | port->ignore_status_mask = 0; |
| 481 | |
| 482 | if (termios->c_iflag & INPCK) |
| 483 | port->read_status_mask |= XUARTPS_IXR_PARITY | |
| 484 | XUARTPS_IXR_FRAMING; |
| 485 | |
| 486 | if (termios->c_iflag & IGNPAR) |
| 487 | port->ignore_status_mask |= XUARTPS_IXR_PARITY | |
| 488 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; |
| 489 | |
| 490 | /* ignore all characters if CREAD is not set */ |
| 491 | if ((termios->c_cflag & CREAD) == 0) |
| 492 | port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | |
| 493 | XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | |
| 494 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; |
| 495 | |
| 496 | mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); |
| 497 | |
| 498 | /* Handling Data Size */ |
| 499 | switch (termios->c_cflag & CSIZE) { |
| 500 | case CS6: |
| 501 | cval |= XUARTPS_MR_CHARLEN_6_BIT; |
| 502 | break; |
| 503 | case CS7: |
| 504 | cval |= XUARTPS_MR_CHARLEN_7_BIT; |
| 505 | break; |
| 506 | default: |
| 507 | case CS8: |
| 508 | cval |= XUARTPS_MR_CHARLEN_8_BIT; |
| 509 | termios->c_cflag &= ~CSIZE; |
| 510 | termios->c_cflag |= CS8; |
| 511 | break; |
| 512 | } |
| 513 | |
| 514 | /* Handling Parity and Stop Bits length */ |
| 515 | if (termios->c_cflag & CSTOPB) |
| 516 | cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ |
| 517 | else |
| 518 | cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ |
| 519 | |
| 520 | if (termios->c_cflag & PARENB) { |
| 521 | /* Mark or Space parity */ |
| 522 | if (termios->c_cflag & CMSPAR) { |
| 523 | if (termios->c_cflag & PARODD) |
| 524 | cval |= XUARTPS_MR_PARITY_MARK; |
| 525 | else |
| 526 | cval |= XUARTPS_MR_PARITY_SPACE; |
| 527 | } else if (termios->c_cflag & PARODD) |
| 528 | cval |= XUARTPS_MR_PARITY_ODD; |
| 529 | else |
| 530 | cval |= XUARTPS_MR_PARITY_EVEN; |
| 531 | } else |
| 532 | cval |= XUARTPS_MR_PARITY_NONE; |
| 533 | xuartps_writel(cval , XUARTPS_MR_OFFSET); |
| 534 | |
| 535 | spin_unlock_irqrestore(&port->lock, flags); |
| 536 | } |
| 537 | |
| 538 | /** |
| 539 | * xuartps_startup - Called when an application opens a xuartps port |
| 540 | * @port: Handle to the uart port structure |
| 541 | * |
| 542 | * Returns 0 on success, negative error otherwise |
| 543 | **/ |
| 544 | static int xuartps_startup(struct uart_port *port) |
| 545 | { |
| 546 | unsigned int retval = 0, status = 0; |
| 547 | |
| 548 | retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, |
| 549 | (void *)port); |
| 550 | if (retval) |
| 551 | return retval; |
| 552 | |
| 553 | /* Disable the TX and RX */ |
| 554 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, |
| 555 | XUARTPS_CR_OFFSET); |
| 556 | |
| 557 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, |
| 558 | * no break chars. |
| 559 | */ |
| 560 | xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, |
| 561 | XUARTPS_CR_OFFSET); |
| 562 | |
| 563 | status = xuartps_readl(XUARTPS_CR_OFFSET); |
| 564 | |
| 565 | /* Clear the RX disable and TX disable bits and then set the TX enable |
| 566 | * bit and RX enable bit to enable the transmitter and receiver. |
| 567 | */ |
| 568 | xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
| 569 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | |
| 570 | XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); |
| 571 | |
| 572 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, |
| 573 | * no parity. |
| 574 | */ |
| 575 | xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT |
| 576 | | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, |
| 577 | XUARTPS_MR_OFFSET); |
| 578 | |
| 579 | /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */ |
| 580 | xuartps_writel(14, XUARTPS_RXWM_OFFSET); |
| 581 | |
| 582 | /* Receive Timeout register is enabled with value of 10 */ |
| 583 | xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); |
| 584 | |
| 585 | |
| 586 | /* Set the Interrupt Registers with desired interrupts */ |
| 587 | xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | |
| 588 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | |
| 589 | XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); |
| 590 | xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | |
| 591 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | |
| 592 | XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET); |
| 593 | |
| 594 | return retval; |
| 595 | } |
| 596 | |
| 597 | /** |
| 598 | * xuartps_shutdown - Called when an application closes a xuartps port |
| 599 | * @port: Handle to the uart port structure |
| 600 | * |
| 601 | **/ |
| 602 | static void xuartps_shutdown(struct uart_port *port) |
| 603 | { |
| 604 | int status; |
| 605 | |
| 606 | /* Disable interrupts */ |
| 607 | status = xuartps_readl(XUARTPS_IMR_OFFSET); |
| 608 | xuartps_writel(status, XUARTPS_IDR_OFFSET); |
| 609 | |
| 610 | /* Disable the TX and RX */ |
| 611 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, |
| 612 | XUARTPS_CR_OFFSET); |
| 613 | free_irq(port->irq, port); |
| 614 | } |
| 615 | |
| 616 | /** |
| 617 | * xuartps_type - Set UART type to xuartps port |
| 618 | * @port: Handle to the uart port structure |
| 619 | * |
| 620 | * Returns string on success, NULL otherwise |
| 621 | **/ |
| 622 | static const char *xuartps_type(struct uart_port *port) |
| 623 | { |
| 624 | return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; |
| 625 | } |
| 626 | |
| 627 | /** |
| 628 | * xuartps_verify_port - Verify the port params |
| 629 | * @port: Handle to the uart port structure |
| 630 | * @ser: Handle to the structure whose members are compared |
| 631 | * |
| 632 | * Returns 0 if success otherwise -EINVAL |
| 633 | **/ |
| 634 | static int xuartps_verify_port(struct uart_port *port, |
| 635 | struct serial_struct *ser) |
| 636 | { |
| 637 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) |
| 638 | return -EINVAL; |
| 639 | if (port->irq != ser->irq) |
| 640 | return -EINVAL; |
| 641 | if (ser->io_type != UPIO_MEM) |
| 642 | return -EINVAL; |
| 643 | if (port->iobase != ser->port) |
| 644 | return -EINVAL; |
| 645 | if (ser->hub6 != 0) |
| 646 | return -EINVAL; |
| 647 | return 0; |
| 648 | } |
| 649 | |
| 650 | /** |
| 651 | * xuartps_request_port - Claim the memory region attached to xuartps port, |
| 652 | * called when the driver adds a xuartps port via |
| 653 | * uart_add_one_port() |
| 654 | * @port: Handle to the uart port structure |
| 655 | * |
| 656 | * Returns 0, -ENOMEM if request fails |
| 657 | **/ |
| 658 | static int xuartps_request_port(struct uart_port *port) |
| 659 | { |
| 660 | if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, |
| 661 | XUARTPS_NAME)) { |
| 662 | return -ENOMEM; |
| 663 | } |
| 664 | |
| 665 | port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); |
| 666 | if (!port->membase) { |
| 667 | dev_err(port->dev, "Unable to map registers\n"); |
| 668 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); |
| 669 | return -ENOMEM; |
| 670 | } |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | /** |
| 675 | * xuartps_release_port - Release the memory region attached to a xuartps |
| 676 | * port, called when the driver removes a xuartps |
| 677 | * port via uart_remove_one_port(). |
| 678 | * @port: Handle to the uart port structure |
| 679 | * |
| 680 | **/ |
| 681 | static void xuartps_release_port(struct uart_port *port) |
| 682 | { |
| 683 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); |
| 684 | iounmap(port->membase); |
| 685 | port->membase = NULL; |
| 686 | } |
| 687 | |
| 688 | /** |
| 689 | * xuartps_config_port - Configure xuartps, called when the driver adds a |
| 690 | * xuartps port |
| 691 | * @port: Handle to the uart port structure |
| 692 | * @flags: If any |
| 693 | * |
| 694 | **/ |
| 695 | static void xuartps_config_port(struct uart_port *port, int flags) |
| 696 | { |
| 697 | if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) |
| 698 | port->type = PORT_XUARTPS; |
| 699 | } |
| 700 | |
| 701 | /** |
| 702 | * xuartps_get_mctrl - Get the modem control state |
| 703 | * |
| 704 | * @port: Handle to the uart port structure |
| 705 | * |
| 706 | * Returns the modem control state |
| 707 | * |
| 708 | **/ |
| 709 | static unsigned int xuartps_get_mctrl(struct uart_port *port) |
| 710 | { |
| 711 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; |
| 712 | } |
| 713 | |
| 714 | static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 715 | { |
| 716 | /* N/A */ |
| 717 | } |
| 718 | |
| 719 | static void xuartps_enable_ms(struct uart_port *port) |
| 720 | { |
| 721 | /* N/A */ |
| 722 | } |
| 723 | |
| 724 | /** The UART operations structure |
| 725 | */ |
| 726 | static struct uart_ops xuartps_ops = { |
| 727 | .set_mctrl = xuartps_set_mctrl, |
| 728 | .get_mctrl = xuartps_get_mctrl, |
| 729 | .enable_ms = xuartps_enable_ms, |
| 730 | |
| 731 | .start_tx = xuartps_start_tx, /* Start transmitting */ |
| 732 | .stop_tx = xuartps_stop_tx, /* Stop transmission */ |
| 733 | .stop_rx = xuartps_stop_rx, /* Stop reception */ |
| 734 | .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ |
| 735 | .break_ctl = xuartps_break_ctl, /* Start/stop |
| 736 | * transmitting break |
| 737 | */ |
| 738 | .set_termios = xuartps_set_termios, /* Set termios */ |
| 739 | .startup = xuartps_startup, /* App opens xuartps */ |
| 740 | .shutdown = xuartps_shutdown, /* App closes xuartps */ |
| 741 | .type = xuartps_type, /* Set UART type */ |
| 742 | .verify_port = xuartps_verify_port, /* Verification of port |
| 743 | * params |
| 744 | */ |
| 745 | .request_port = xuartps_request_port, /* Claim resources |
| 746 | * associated with a |
| 747 | * xuartps port |
| 748 | */ |
| 749 | .release_port = xuartps_release_port, /* Release resources |
| 750 | * associated with a |
| 751 | * xuartps port |
| 752 | */ |
| 753 | .config_port = xuartps_config_port, /* Configure when driver |
| 754 | * adds a xuartps port |
| 755 | */ |
| 756 | }; |
| 757 | |
| 758 | static struct uart_port xuartps_port[2]; |
| 759 | |
| 760 | /** |
| 761 | * xuartps_get_port - Configure the port from the platform device resource |
| 762 | * info |
| 763 | * |
| 764 | * Returns a pointer to a uart_port or NULL for failure |
| 765 | **/ |
| 766 | static struct uart_port *xuartps_get_port(void) |
| 767 | { |
| 768 | struct uart_port *port; |
| 769 | int id; |
| 770 | |
| 771 | /* Find the next unused port */ |
| 772 | for (id = 0; id < XUARTPS_NR_PORTS; id++) |
| 773 | if (xuartps_port[id].mapbase == 0) |
| 774 | break; |
| 775 | |
| 776 | if (id >= XUARTPS_NR_PORTS) |
| 777 | return NULL; |
| 778 | |
| 779 | port = &xuartps_port[id]; |
| 780 | |
| 781 | /* At this point, we've got an empty uart_port struct, initialize it */ |
| 782 | spin_lock_init(&port->lock); |
| 783 | port->membase = NULL; |
| 784 | port->iobase = 1; /* mark port in use */ |
| 785 | port->irq = 0; |
| 786 | port->type = PORT_UNKNOWN; |
| 787 | port->iotype = UPIO_MEM32; |
| 788 | port->flags = UPF_BOOT_AUTOCONF; |
| 789 | port->ops = &xuartps_ops; |
| 790 | port->fifosize = XUARTPS_FIFO_SIZE; |
| 791 | port->line = id; |
| 792 | port->dev = NULL; |
| 793 | return port; |
| 794 | } |
| 795 | |
| 796 | /*-----------------------Console driver operations--------------------------*/ |
| 797 | |
| 798 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
| 799 | /** |
| 800 | * xuartps_console_wait_tx - Wait for the TX to be full |
| 801 | * @port: Handle to the uart port structure |
| 802 | * |
| 803 | **/ |
| 804 | static void xuartps_console_wait_tx(struct uart_port *port) |
| 805 | { |
| 806 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) |
| 807 | != XUARTPS_SR_TXEMPTY) |
| 808 | barrier(); |
| 809 | } |
| 810 | |
| 811 | /** |
| 812 | * xuartps_console_putchar - write the character to the FIFO buffer |
| 813 | * @port: Handle to the uart port structure |
| 814 | * @ch: Character to be written |
| 815 | * |
| 816 | **/ |
| 817 | static void xuartps_console_putchar(struct uart_port *port, int ch) |
| 818 | { |
| 819 | xuartps_console_wait_tx(port); |
| 820 | xuartps_writel(ch, XUARTPS_FIFO_OFFSET); |
| 821 | } |
| 822 | |
| 823 | /** |
| 824 | * xuartps_console_write - perform write operation |
| 825 | * @port: Handle to the uart port structure |
| 826 | * @s: Pointer to character array |
| 827 | * @count: No of characters |
| 828 | **/ |
| 829 | static void xuartps_console_write(struct console *co, const char *s, |
| 830 | unsigned int count) |
| 831 | { |
| 832 | struct uart_port *port = &xuartps_port[co->index]; |
| 833 | unsigned long flags; |
| 834 | unsigned int imr; |
| 835 | int locked = 1; |
| 836 | |
| 837 | if (oops_in_progress) |
| 838 | locked = spin_trylock_irqsave(&port->lock, flags); |
| 839 | else |
| 840 | spin_lock_irqsave(&port->lock, flags); |
| 841 | |
| 842 | /* save and disable interrupt */ |
| 843 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); |
| 844 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); |
| 845 | |
| 846 | uart_console_write(port, s, count, xuartps_console_putchar); |
| 847 | xuartps_console_wait_tx(port); |
| 848 | |
| 849 | /* restore interrupt state, it seems like there may be a h/w bug |
| 850 | * in that the interrupt enable register should not need to be |
| 851 | * written based on the data sheet |
| 852 | */ |
| 853 | xuartps_writel(~imr, XUARTPS_IDR_OFFSET); |
| 854 | xuartps_writel(imr, XUARTPS_IER_OFFSET); |
| 855 | |
| 856 | if (locked) |
| 857 | spin_unlock_irqrestore(&port->lock, flags); |
| 858 | } |
| 859 | |
| 860 | /** |
| 861 | * xuartps_console_setup - Initialize the uart to default config |
| 862 | * @co: Console handle |
| 863 | * @options: Initial settings of uart |
| 864 | * |
| 865 | * Returns 0, -ENODEV if no device |
| 866 | **/ |
| 867 | static int __init xuartps_console_setup(struct console *co, char *options) |
| 868 | { |
| 869 | struct uart_port *port = &xuartps_port[co->index]; |
| 870 | int baud = 9600; |
| 871 | int bits = 8; |
| 872 | int parity = 'n'; |
| 873 | int flow = 'n'; |
| 874 | |
| 875 | if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) |
| 876 | return -EINVAL; |
| 877 | |
| 878 | if (!port->mapbase) { |
| 879 | pr_debug("console on ttyPS%i not present\n", co->index); |
| 880 | return -ENODEV; |
| 881 | } |
| 882 | |
| 883 | if (options) |
| 884 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 885 | |
| 886 | return uart_set_options(port, co, baud, parity, bits, flow); |
| 887 | } |
| 888 | |
| 889 | static struct uart_driver xuartps_uart_driver; |
| 890 | |
| 891 | static struct console xuartps_console = { |
| 892 | .name = XUARTPS_TTY_NAME, |
| 893 | .write = xuartps_console_write, |
| 894 | .device = uart_console_device, |
| 895 | .setup = xuartps_console_setup, |
| 896 | .flags = CON_PRINTBUFFER, |
| 897 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ |
| 898 | .data = &xuartps_uart_driver, |
| 899 | }; |
| 900 | |
| 901 | /** |
| 902 | * xuartps_console_init - Initialization call |
| 903 | * |
| 904 | * Returns 0 on success, negative error otherwise |
| 905 | **/ |
| 906 | static int __init xuartps_console_init(void) |
| 907 | { |
| 908 | register_console(&xuartps_console); |
| 909 | return 0; |
| 910 | } |
| 911 | |
| 912 | console_initcall(xuartps_console_init); |
| 913 | |
| 914 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ |
| 915 | |
| 916 | /** Structure Definitions |
| 917 | */ |
| 918 | static struct uart_driver xuartps_uart_driver = { |
| 919 | .owner = THIS_MODULE, /* Owner */ |
| 920 | .driver_name = XUARTPS_NAME, /* Driver name */ |
| 921 | .dev_name = XUARTPS_TTY_NAME, /* Node name */ |
| 922 | .major = XUARTPS_MAJOR, /* Major number */ |
| 923 | .minor = XUARTPS_MINOR, /* Minor number */ |
| 924 | .nr = XUARTPS_NR_PORTS, /* Number of UART ports */ |
| 925 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
| 926 | .cons = &xuartps_console, /* Console */ |
| 927 | #endif |
| 928 | }; |
| 929 | |
| 930 | /* --------------------------------------------------------------------- |
| 931 | * Platform bus binding |
| 932 | */ |
| 933 | /** |
| 934 | * xuartps_probe - Platform driver probe |
| 935 | * @pdev: Pointer to the platform device structure |
| 936 | * |
| 937 | * Returns 0 on success, negative error otherwise |
| 938 | **/ |
| 939 | static int __devinit xuartps_probe(struct platform_device *pdev) |
| 940 | { |
| 941 | int rc; |
| 942 | struct uart_port *port; |
| 943 | struct resource *res, *res2; |
| 944 | int clk = 0; |
| 945 | |
| 946 | #ifdef CONFIG_OF |
| 947 | const unsigned int *prop; |
| 948 | |
| 949 | prop = of_get_property(pdev->dev.of_node, "clock", NULL); |
| 950 | if (prop) |
| 951 | clk = be32_to_cpup(prop); |
| 952 | #else |
| 953 | clk = *((unsigned int *)(pdev->dev.platform_data)); |
| 954 | #endif |
| 955 | if (!clk) { |
| 956 | dev_err(&pdev->dev, "no clock specified\n"); |
| 957 | return -ENODEV; |
| 958 | } |
| 959 | |
| 960 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 961 | if (!res) |
| 962 | return -ENODEV; |
| 963 | |
| 964 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 965 | if (!res2) |
| 966 | return -ENODEV; |
| 967 | |
| 968 | /* Initialize the port structure */ |
| 969 | port = xuartps_get_port(); |
| 970 | |
| 971 | if (!port) { |
| 972 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); |
| 973 | return -ENODEV; |
| 974 | } else { |
| 975 | /* Register the port. |
| 976 | * This function also registers this device with the tty layer |
| 977 | * and triggers invocation of the config_port() entry point. |
| 978 | */ |
| 979 | port->mapbase = res->start; |
| 980 | port->irq = res2->start; |
| 981 | port->dev = &pdev->dev; |
| 982 | port->uartclk = clk; |
| 983 | dev_set_drvdata(&pdev->dev, port); |
| 984 | rc = uart_add_one_port(&xuartps_uart_driver, port); |
| 985 | if (rc) { |
| 986 | dev_err(&pdev->dev, |
| 987 | "uart_add_one_port() failed; err=%i\n", rc); |
| 988 | dev_set_drvdata(&pdev->dev, NULL); |
| 989 | return rc; |
| 990 | } |
| 991 | return 0; |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | /** |
| 996 | * xuartps_remove - called when the platform driver is unregistered |
| 997 | * @pdev: Pointer to the platform device structure |
| 998 | * |
| 999 | * Returns 0 on success, negative error otherwise |
| 1000 | **/ |
| 1001 | static int __devexit xuartps_remove(struct platform_device *pdev) |
| 1002 | { |
| 1003 | struct uart_port *port = dev_get_drvdata(&pdev->dev); |
| 1004 | int rc = 0; |
| 1005 | |
| 1006 | /* Remove the xuartps port from the serial core */ |
| 1007 | if (port) { |
| 1008 | rc = uart_remove_one_port(&xuartps_uart_driver, port); |
| 1009 | dev_set_drvdata(&pdev->dev, NULL); |
| 1010 | port->mapbase = 0; |
| 1011 | } |
| 1012 | return rc; |
| 1013 | } |
| 1014 | |
| 1015 | /** |
| 1016 | * xuartps_suspend - suspend event |
| 1017 | * @pdev: Pointer to the platform device structure |
| 1018 | * @state: State of the device |
| 1019 | * |
| 1020 | * Returns 0 |
| 1021 | **/ |
| 1022 | static int xuartps_suspend(struct platform_device *pdev, pm_message_t state) |
| 1023 | { |
| 1024 | /* Call the API provided in serial_core.c file which handles |
| 1025 | * the suspend. |
| 1026 | */ |
| 1027 | uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]); |
| 1028 | return 0; |
| 1029 | } |
| 1030 | |
| 1031 | /** |
| 1032 | * xuartps_resume - Resume after a previous suspend |
| 1033 | * @pdev: Pointer to the platform device structure |
| 1034 | * |
| 1035 | * Returns 0 |
| 1036 | **/ |
| 1037 | static int xuartps_resume(struct platform_device *pdev) |
| 1038 | { |
| 1039 | uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]); |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
| 1043 | /* Match table for of_platform binding */ |
| 1044 | |
| 1045 | #ifdef CONFIG_OF |
| 1046 | static struct of_device_id xuartps_of_match[] __devinitdata = { |
| 1047 | { .compatible = "xlnx,xuartps", }, |
| 1048 | {} |
| 1049 | }; |
| 1050 | MODULE_DEVICE_TABLE(of, xuartps_of_match); |
| 1051 | #else |
| 1052 | #define xuartps_of_match NULL |
| 1053 | #endif |
| 1054 | |
| 1055 | static struct platform_driver xuartps_platform_driver = { |
| 1056 | .probe = xuartps_probe, /* Probe method */ |
| 1057 | .remove = __exit_p(xuartps_remove), /* Detach method */ |
| 1058 | .suspend = xuartps_suspend, /* Suspend */ |
| 1059 | .resume = xuartps_resume, /* Resume after a suspend */ |
| 1060 | .driver = { |
| 1061 | .owner = THIS_MODULE, |
| 1062 | .name = XUARTPS_NAME, /* Driver name */ |
| 1063 | .of_match_table = xuartps_of_match, |
| 1064 | }, |
| 1065 | }; |
| 1066 | |
| 1067 | /* --------------------------------------------------------------------- |
| 1068 | * Module Init and Exit |
| 1069 | */ |
| 1070 | /** |
| 1071 | * xuartps_init - Initial driver registration call |
| 1072 | * |
| 1073 | * Returns whether the registration was successful or not |
| 1074 | **/ |
| 1075 | static int __init xuartps_init(void) |
| 1076 | { |
| 1077 | int retval = 0; |
| 1078 | |
| 1079 | /* Register the xuartps driver with the serial core */ |
| 1080 | retval = uart_register_driver(&xuartps_uart_driver); |
| 1081 | if (retval) |
| 1082 | return retval; |
| 1083 | |
| 1084 | /* Register the platform driver */ |
| 1085 | retval = platform_driver_register(&xuartps_platform_driver); |
| 1086 | if (retval) |
| 1087 | uart_unregister_driver(&xuartps_uart_driver); |
| 1088 | |
| 1089 | return retval; |
| 1090 | } |
| 1091 | |
| 1092 | /** |
| 1093 | * xuartps_exit - Driver unregistration call |
| 1094 | **/ |
| 1095 | static void __exit xuartps_exit(void) |
| 1096 | { |
| 1097 | /* The order of unregistration is important. Unregister the |
| 1098 | * UART driver before the platform driver crashes the system. |
| 1099 | */ |
| 1100 | |
| 1101 | /* Unregister the platform driver */ |
| 1102 | platform_driver_unregister(&xuartps_platform_driver); |
| 1103 | |
| 1104 | /* Unregister the xuartps driver */ |
| 1105 | uart_unregister_driver(&xuartps_uart_driver); |
| 1106 | } |
| 1107 | |
| 1108 | module_init(xuartps_init); |
| 1109 | module_exit(xuartps_exit); |
| 1110 | |
| 1111 | MODULE_DESCRIPTION("Driver for PS UART"); |
| 1112 | MODULE_AUTHOR("Xilinx Inc."); |
| 1113 | MODULE_LICENSE("GPL"); |