blob: 96897242fcc22958c59340830a74e589ae00aa63 [file] [log] [blame]
Terje Bergstrom75471682013-03-22 16:34:01 +02001/*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/module.h>
20#include <linux/list.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#define CREATE_TRACE_POINTS
28#include <trace/events/host1x.h>
29
30#include "dev.h"
Terje Bergstrom7ede0b02013-03-22 16:34:02 +020031#include "intr.h"
Terje Bergstrom65793242013-03-22 16:34:03 +020032#include "channel.h"
Terje Bergstrom62364512013-03-22 16:34:04 +020033#include "debug.h"
Terje Bergstrom75471682013-03-22 16:34:01 +020034#include "hw/host1x01.h"
35
36void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
37{
38 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
39
40 writel(v, sync_regs + r);
41}
42
43u32 host1x_sync_readl(struct host1x *host1x, u32 r)
44{
45 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
46
47 return readl(sync_regs + r);
48}
49
Terje Bergstrom65793242013-03-22 16:34:03 +020050void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
51{
52 writel(v, ch->regs + r);
53}
54
55u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
56{
57 return readl(ch->regs + r);
58}
59
Terje Bergstrom75471682013-03-22 16:34:01 +020060static const struct host1x_info host1x01_info = {
61 .nb_channels = 8,
62 .nb_pts = 32,
63 .nb_mlocks = 16,
64 .nb_bases = 8,
65 .init = host1x01_init,
66 .sync_offset = 0x3000,
67};
68
69static struct of_device_id host1x_of_match[] = {
70 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
71 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
72 { },
73};
74MODULE_DEVICE_TABLE(of, host1x_of_match);
75
76static int host1x_probe(struct platform_device *pdev)
77{
78 const struct of_device_id *id;
79 struct host1x *host;
80 struct resource *regs;
81 int syncpt_irq;
82 int err;
83
84 id = of_match_device(host1x_of_match, &pdev->dev);
85 if (!id)
86 return -EINVAL;
87
88 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
89 if (!regs) {
90 dev_err(&pdev->dev, "failed to get registers\n");
91 return -ENXIO;
92 }
93
94 syncpt_irq = platform_get_irq(pdev, 0);
95 if (syncpt_irq < 0) {
96 dev_err(&pdev->dev, "failed to get IRQ\n");
97 return -ENXIO;
98 }
99
100 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
101 if (!host)
102 return -ENOMEM;
103
104 host->dev = &pdev->dev;
105 host->info = id->data;
106
107 /* set common host1x device data */
108 platform_set_drvdata(pdev, host);
109
110 host->regs = devm_ioremap_resource(&pdev->dev, regs);
111 if (IS_ERR(host->regs))
112 return PTR_ERR(host->regs);
113
114 if (host->info->init) {
115 err = host->info->init(host);
116 if (err)
117 return err;
118 }
119
120 host->clk = devm_clk_get(&pdev->dev, NULL);
121 if (IS_ERR(host->clk)) {
122 dev_err(&pdev->dev, "failed to get clock\n");
123 err = PTR_ERR(host->clk);
124 return err;
125 }
126
Terje Bergstrom65793242013-03-22 16:34:03 +0200127 err = host1x_channel_list_init(host);
128 if (err) {
129 dev_err(&pdev->dev, "failed to initialize channel list\n");
130 return err;
131 }
132
Terje Bergstrom75471682013-03-22 16:34:01 +0200133 err = clk_prepare_enable(host->clk);
134 if (err < 0) {
135 dev_err(&pdev->dev, "failed to enable clock\n");
136 return err;
137 }
138
139 err = host1x_syncpt_init(host);
140 if (err) {
141 dev_err(&pdev->dev, "failed to initialize syncpts\n");
142 return err;
143 }
144
Terje Bergstrom7ede0b02013-03-22 16:34:02 +0200145 err = host1x_intr_init(host, syncpt_irq);
146 if (err) {
147 dev_err(&pdev->dev, "failed to initialize interrupts\n");
148 goto fail_deinit_syncpt;
149 }
150
Terje Bergstrom62364512013-03-22 16:34:04 +0200151 host1x_debug_init(host);
152
Terje Bergstrom75471682013-03-22 16:34:01 +0200153 return 0;
Terje Bergstrom7ede0b02013-03-22 16:34:02 +0200154
155fail_deinit_syncpt:
156 host1x_syncpt_deinit(host);
157 return err;
Terje Bergstrom75471682013-03-22 16:34:01 +0200158}
159
160static int __exit host1x_remove(struct platform_device *pdev)
161{
162 struct host1x *host = platform_get_drvdata(pdev);
163
Terje Bergstrom7ede0b02013-03-22 16:34:02 +0200164 host1x_intr_deinit(host);
Terje Bergstrom75471682013-03-22 16:34:01 +0200165 host1x_syncpt_deinit(host);
166 clk_disable_unprepare(host->clk);
167
168 return 0;
169}
170
171static struct platform_driver platform_driver = {
172 .probe = host1x_probe,
173 .remove = __exit_p(host1x_remove),
174 .driver = {
175 .owner = THIS_MODULE,
176 .name = "tegra-host1x",
177 .of_match_table = host1x_of_match,
178 },
179};
180
181module_platform_driver(platform_driver);
182
183MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
184MODULE_DESCRIPTION("Host1x driver for Tegra products");
185MODULE_LICENSE("GPL");