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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070035#include <linux/io-mapping.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070044#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Jesse Barnes317c35d2008-08-25 15:11:06 -070046enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
Jesse Barnes80824002009-09-10 15:28:06 -070051enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
Keith Packard52440212008-11-18 09:30:25 -080056#define I915_NUM_PIPE 2
57
Linus Torvalds1da177e2005-04-16 15:20:36 -070058/* Interface history:
59 *
60 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110061 * 1.2: Add Power Management
62 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110063 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100064 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100065 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 */
68#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100069#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#define DRIVER_PATCHLEVEL 0
71
Eric Anholt673a3942008-07-30 12:06:12 -070072#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
Dave Airlie71acb5e2008-12-30 20:31:46 +100080#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092typedef struct _drm_i915_ring_buffer {
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
Eric Anholt673a3942008-07-30 12:06:12 -070099 struct drm_gem_object *ring_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108};
109
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
Dave Airlie7c1c2872008-11-28 14:22:24 +1000123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000132
yakui_zhao9b9d1722009-05-31 17:17:17 +0800133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000153 u64 bbaddr;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700154 struct timeval time;
Chris Wilson9df30792010-02-18 10:24:56 +0000155 struct drm_i915_error_object {
156 int page_count;
157 u32 gtt_offset;
158 u32 *pages[0];
159 } *ringbuffer, *batchbuffer[2];
160 struct drm_i915_error_buffer {
161 size_t size;
162 u32 name;
163 u32 seqno;
164 u32 gtt_offset;
165 u32 read_domains;
166 u32 write_domain;
167 u32 fence_reg;
168 s32 pinned:2;
169 u32 tiling:2;
170 u32 dirty:1;
171 u32 purgeable:1;
172 } *active_bo;
173 u32 active_bo_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700174};
175
Jesse Barnese70236a2009-09-21 10:42:27 -0700176struct drm_i915_display_funcs {
177 void (*dpms)(struct drm_crtc *crtc, int mode);
178 bool (*fbc_enabled)(struct drm_crtc *crtc);
179 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
180 void (*disable_fbc)(struct drm_device *dev);
181 int (*get_display_clock_speed)(struct drm_device *dev);
182 int (*get_fifo_size)(struct drm_device *dev, int plane);
183 void (*update_wm)(struct drm_device *dev, int planea_clock,
184 int planeb_clock, int sr_hdisplay, int pixel_size);
185 /* clock updates for mode set */
186 /* cursor updates */
187 /* render clock increase/decrease */
188 /* display clock increase/decrease */
189 /* pll clock increase/decrease */
190 /* clock gating init */
191};
192
Daniel Vetter02e792f2009-09-15 22:57:34 +0200193struct intel_overlay;
194
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195struct intel_device_info {
196 u8 is_mobile : 1;
197 u8 is_i8xx : 1;
198 u8 is_i915g : 1;
199 u8 is_i9xx : 1;
200 u8 is_i945gm : 1;
201 u8 is_i965g : 1;
202 u8 is_i965gm : 1;
203 u8 is_g33 : 1;
204 u8 need_gfx_hws : 1;
205 u8 is_g4x : 1;
206 u8 is_pineview : 1;
207 u8 is_ironlake : 1;
Zhenyu Wang59f2d0f2010-03-09 23:37:07 +0800208 u8 is_gen6 : 1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500209 u8 has_fbc : 1;
210 u8 has_rc6 : 1;
211 u8 has_pipe_cxsr : 1;
212 u8 has_hotplug : 1;
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500213 u8 cursor_needs_physical : 1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500214};
215
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800216enum no_fbc_reason {
217 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
218 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
219 FBC_MODE_TOO_LARGE, /* mode too large for compression */
220 FBC_BAD_PLANE, /* fbc not supported on plane */
221 FBC_NOT_TILED, /* buffer not tiled */
222};
223
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800224enum intel_pch {
225 PCH_IBX, /* Ibexpeak PCH */
226 PCH_CPT, /* Cougarpoint PCH */
227};
228
Dave Airlie8be48d92010-03-30 05:34:14 +0000229struct intel_fbdev;
Dave Airlie38651672010-03-30 05:34:13 +0000230
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231typedef struct drm_i915_private {
Eric Anholt673a3942008-07-30 12:06:12 -0700232 struct drm_device *dev;
233
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500234 const struct intel_device_info *info;
235
Dave Airlieac5c4e72008-12-19 15:38:34 +1000236 int has_gem;
237
Eric Anholt3043c602008-10-02 12:24:47 -0700238 void __iomem *regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
Dave Airlieec2a4c32009-08-04 11:43:41 +1000240 struct pci_dev *bridge_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 drm_i915_ring_buffer_t ring;
242
Dave Airlie9c8da5e2005-07-10 15:38:56 +1000243 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 dma_addr_t dma_status_page;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700246 uint32_t counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000247 unsigned int status_gfx_addr;
248 drm_local_map_t hws_map;
Eric Anholt673a3942008-07-30 12:06:12 -0700249 struct drm_gem_object *hws_obj;
Jesse Barnes97f5ab62009-10-08 10:16:48 -0700250 struct drm_gem_object *pwrctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
Jesse Barnesd7658982009-06-05 14:41:29 +0000252 struct resource mch_res;
253
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000254 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 int back_offset;
256 int front_offset;
257 int current_page;
258 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260 wait_queue_head_t irq_queue;
261 atomic_t irq_received;
Eric Anholted4cb412008-07-29 12:10:39 -0700262 /** Protects user_irq_refcount and irq_mask_reg */
263 spinlock_t user_irq_lock;
264 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
265 int user_irq_refcount;
Chris Wilson9d34e5d2009-09-24 05:26:06 +0100266 u32 trace_irq_seqno;
Eric Anholted4cb412008-07-29 12:10:39 -0700267 /** Cached value of IMR to avoid reads in updating the bitfield */
268 u32 irq_mask_reg;
Keith Packard7c463582008-11-04 02:03:27 -0800269 u32 pipestat[2];
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500270 /** splitted irq regs for graphics and display engine on Ironlake,
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800271 irq_mask_reg is still used for display irq. */
272 u32 gt_irq_mask_reg;
273 u32 gt_irq_enable_reg;
274 u32 de_irq_enable_reg;
Zhenyu Wangc6501562009-11-03 18:57:21 +0000275 u32 pch_irq_mask_reg;
276 u32 pch_irq_enable_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277
Jesse Barnes5ca58282009-03-31 14:11:15 -0700278 u32 hotplug_supported_mask;
279 struct work_struct hotplug_work;
280
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 int tex_lru_log_granularity;
282 int allow_batchbuffer;
283 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100284 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000285 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000286
Ben Gamarif65d9422009-09-14 17:48:44 -0400287 /* For hangcheck timer */
288#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
289 struct timer_list hangcheck_timer;
290 int hangcheck_count;
291 uint32_t last_acthd;
292
Jesse Barnes79e53942008-11-07 14:24:08 -0800293 struct drm_mm vram;
294
Jesse Barnes80824002009-09-10 15:28:06 -0700295 unsigned long cfb_size;
296 unsigned long cfb_pitch;
297 int cfb_fence;
298 int cfb_plane;
299
Jesse Barnes79e53942008-11-07 14:24:08 -0800300 int irq_enabled;
301
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100302 struct intel_opregion opregion;
303
Daniel Vetter02e792f2009-09-15 22:57:34 +0200304 /* overlay */
305 struct intel_overlay *overlay;
306
Jesse Barnes79e53942008-11-07 14:24:08 -0800307 /* LVDS info */
308 int backlight_duty_cycle; /* restore backlight to this value */
309 bool panel_wants_dither;
310 struct drm_display_mode *panel_fixed_mode;
Ma Ling88631702009-05-13 11:19:55 +0800311 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
312 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
Jesse Barnes79e53942008-11-07 14:24:08 -0800313
314 /* Feature bits from the VBIOS */
Hannes Eder95281e32008-12-18 15:09:00 +0100315 unsigned int int_tv_support:1;
316 unsigned int lvds_dither:1;
317 unsigned int lvds_vbt:1;
318 unsigned int int_crt_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500319 unsigned int lvds_use_ssc:1;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800320 unsigned int edp_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500321 int lvds_ssc_freq;
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800322 int edp_bpp;
Jesse Barnes79e53942008-11-07 14:24:08 -0800323
Jesse Barnesc1c7af62009-09-10 15:28:03 -0700324 struct notifier_block lid_notifier;
325
Shaohua Li29874f42009-11-18 15:15:02 +0800326 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
Jesse Barnesde151cf2008-11-12 10:03:55 -0800327 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
328 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
329 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
330
Shaohua Li7662c8b2009-06-26 11:23:55 +0800331 unsigned int fsb_freq, mem_freq;
332
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700333 spinlock_t error_lock;
334 struct drm_i915_error_state *first_error;
Jesse Barnes8a905232009-07-11 16:48:03 -0400335 struct work_struct error_work;
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700336 struct workqueue_struct *wq;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700337
Jesse Barnese70236a2009-09-21 10:42:27 -0700338 /* Display functions */
339 struct drm_i915_display_funcs display;
340
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800341 /* PCH chipset type */
342 enum intel_pch pch_type;
343
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000344 /* Register state */
Linus Torvaldsc9354c82009-11-02 09:29:55 -0800345 bool modeset_on_lid;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000346 u8 saveLBB;
347 u32 saveDSPACNTR;
348 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000349 u32 saveDSPARB;
Peng Li461cba22008-11-18 12:39:02 +0800350 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000351 u32 savePIPEACONF;
352 u32 savePIPEBCONF;
353 u32 savePIPEASRC;
354 u32 savePIPEBSRC;
355 u32 saveFPA0;
356 u32 saveFPA1;
357 u32 saveDPLL_A;
358 u32 saveDPLL_A_MD;
359 u32 saveHTOTAL_A;
360 u32 saveHBLANK_A;
361 u32 saveHSYNC_A;
362 u32 saveVTOTAL_A;
363 u32 saveVBLANK_A;
364 u32 saveVSYNC_A;
365 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000366 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800367 u32 saveTRANS_HTOTAL_A;
368 u32 saveTRANS_HBLANK_A;
369 u32 saveTRANS_HSYNC_A;
370 u32 saveTRANS_VTOTAL_A;
371 u32 saveTRANS_VBLANK_A;
372 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000373 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000374 u32 saveDSPASTRIDE;
375 u32 saveDSPASIZE;
376 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700377 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000378 u32 saveDSPASURF;
379 u32 saveDSPATILEOFF;
380 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700381 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000382 u32 saveBLC_PWM_CTL;
383 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800384 u32 saveBLC_CPU_PWM_CTL;
385 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000386 u32 saveFPB0;
387 u32 saveFPB1;
388 u32 saveDPLL_B;
389 u32 saveDPLL_B_MD;
390 u32 saveHTOTAL_B;
391 u32 saveHBLANK_B;
392 u32 saveHSYNC_B;
393 u32 saveVTOTAL_B;
394 u32 saveVBLANK_B;
395 u32 saveVSYNC_B;
396 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000397 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800398 u32 saveTRANS_HTOTAL_B;
399 u32 saveTRANS_HBLANK_B;
400 u32 saveTRANS_HSYNC_B;
401 u32 saveTRANS_VTOTAL_B;
402 u32 saveTRANS_VBLANK_B;
403 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000404 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000405 u32 saveDSPBSTRIDE;
406 u32 saveDSPBSIZE;
407 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700408 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000409 u32 saveDSPBSURF;
410 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700411 u32 saveVGA0;
412 u32 saveVGA1;
413 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000414 u32 saveVGACNTRL;
415 u32 saveADPA;
416 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700417 u32 savePP_ON_DELAYS;
418 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000419 u32 saveDVOA;
420 u32 saveDVOB;
421 u32 saveDVOC;
422 u32 savePP_ON;
423 u32 savePP_OFF;
424 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700425 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000426 u32 savePFIT_CONTROL;
427 u32 save_palette_a[256];
428 u32 save_palette_b[256];
Jesse Barnes06027f92009-10-05 13:47:26 -0700429 u32 saveDPFC_CB_BASE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000430 u32 saveFBC_CFB_BASE;
431 u32 saveFBC_LL_BASE;
432 u32 saveFBC_CONTROL;
433 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000434 u32 saveIER;
435 u32 saveIIR;
436 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800437 u32 saveDEIER;
438 u32 saveDEIMR;
439 u32 saveGTIER;
440 u32 saveGTIMR;
441 u32 saveFDI_RXA_IMR;
442 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800443 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800444 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000445 u32 saveSWF0[16];
446 u32 saveSWF1[16];
447 u32 saveSWF2[3];
448 u8 saveMSR;
449 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800450 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000451 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000452 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000453 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000454 u8 saveCR[37];
Keith Packard79f11c12009-04-30 14:43:44 -0700455 uint64_t saveFENCE[16];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000456 u32 saveCURACNTR;
457 u32 saveCURAPOS;
458 u32 saveCURABASE;
459 u32 saveCURBCNTR;
460 u32 saveCURBPOS;
461 u32 saveCURBBASE;
462 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700463 u32 saveDP_B;
464 u32 saveDP_C;
465 u32 saveDP_D;
466 u32 savePIPEA_GMCH_DATA_M;
467 u32 savePIPEB_GMCH_DATA_M;
468 u32 savePIPEA_GMCH_DATA_N;
469 u32 savePIPEB_GMCH_DATA_N;
470 u32 savePIPEA_DP_LINK_M;
471 u32 savePIPEB_DP_LINK_M;
472 u32 savePIPEA_DP_LINK_N;
473 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800474 u32 saveFDI_RXA_CTL;
475 u32 saveFDI_TXA_CTL;
476 u32 saveFDI_RXB_CTL;
477 u32 saveFDI_TXB_CTL;
478 u32 savePFA_CTL_1;
479 u32 savePFB_CTL_1;
480 u32 savePFA_WIN_SZ;
481 u32 savePFB_WIN_SZ;
482 u32 savePFA_WIN_POS;
483 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000484 u32 savePCH_DREF_CONTROL;
485 u32 saveDISP_ARB_CTL;
486 u32 savePIPEA_DATA_M1;
487 u32 savePIPEA_DATA_N1;
488 u32 savePIPEA_LINK_M1;
489 u32 savePIPEA_LINK_N1;
490 u32 savePIPEB_DATA_M1;
491 u32 savePIPEB_DATA_N1;
492 u32 savePIPEB_LINK_M1;
493 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000494 u32 saveMCHBAR_RENDER_STANDBY;
Eric Anholt673a3942008-07-30 12:06:12 -0700495
496 struct {
497 struct drm_mm gtt_space;
498
Keith Packard0839ccb2008-10-30 19:38:48 -0700499 struct io_mapping *gtt_mapping;
Eric Anholtab657db12009-01-23 12:57:47 -0800500 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700501
Eric Anholt673a3942008-07-30 12:06:12 -0700502 /**
Chris Wilson31169712009-09-14 16:50:28 +0100503 * Membership on list of all loaded devices, used to evict
504 * inactive buffers under memory pressure.
505 *
506 * Modifications should only be done whilst holding the
507 * shrink_list_lock spinlock.
508 */
509 struct list_head shrink_list;
510
511 /**
Eric Anholt673a3942008-07-30 12:06:12 -0700512 * List of objects currently involved in rendering from the
513 * ringbuffer.
514 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800515 * Includes buffers having the contents of their GPU caches
516 * flushed, not necessarily primitives. last_rendering_seqno
517 * represents when the rendering involved will be completed.
518 *
Eric Anholt673a3942008-07-30 12:06:12 -0700519 * A reference is held on the buffer while on this list.
520 */
Carl Worth5e118f42009-03-20 11:54:25 -0700521 spinlock_t active_list_lock;
Eric Anholt673a3942008-07-30 12:06:12 -0700522 struct list_head active_list;
523
524 /**
525 * List of objects which are not in the ringbuffer but which
526 * still have a write_domain which needs to be flushed before
527 * unbinding.
528 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800529 * last_rendering_seqno is 0 while an object is in this list.
530 *
Eric Anholt673a3942008-07-30 12:06:12 -0700531 * A reference is held on the buffer while on this list.
532 */
533 struct list_head flushing_list;
534
535 /**
Daniel Vetter99fcb762010-02-07 16:20:18 +0100536 * List of objects currently pending a GPU write flush.
537 *
538 * All elements on this list will belong to either the
539 * active_list or flushing_list, last_rendering_seqno can
540 * be used to differentiate between the two elements.
541 */
542 struct list_head gpu_write_list;
543
544 /**
Eric Anholt673a3942008-07-30 12:06:12 -0700545 * LRU list of objects which are not in the ringbuffer and
546 * are ready to unbind, but are still in the GTT.
547 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800548 * last_rendering_seqno is 0 while an object is in this list.
549 *
Eric Anholt673a3942008-07-30 12:06:12 -0700550 * A reference is not held on the buffer while on this list,
551 * as merely being GTT-bound shouldn't prevent its being
552 * freed, and we'll pull it off the list in the free path.
553 */
554 struct list_head inactive_list;
555
Eric Anholta09ba7f2009-08-29 12:49:51 -0700556 /** LRU list of objects with fence regs on them. */
557 struct list_head fence_list;
558
Eric Anholt673a3942008-07-30 12:06:12 -0700559 /**
560 * List of breadcrumbs associated with GPU requests currently
561 * outstanding.
562 */
563 struct list_head request_list;
564
565 /**
566 * We leave the user IRQ off as much as possible,
567 * but this means that requests will finish and never
568 * be retired once the system goes idle. Set a timer to
569 * fire periodically while the ring is running. When it
570 * fires, go retire requests.
571 */
572 struct delayed_work retire_work;
573
574 uint32_t next_gem_seqno;
575
576 /**
577 * Waiting sequence number, if any
578 */
579 uint32_t waiting_gem_seqno;
580
581 /**
582 * Last seq seen at irq time
583 */
584 uint32_t irq_gem_seqno;
585
586 /**
587 * Flag if the X Server, and thus DRM, is not currently in
588 * control of the device.
589 *
590 * This is set between LeaveVT and EnterVT. It needs to be
591 * replaced with a semaphore. It also needs to be
592 * transitioned away from for kernel modesetting.
593 */
594 int suspended;
595
596 /**
597 * Flag if the hardware appears to be wedged.
598 *
599 * This is set when attempts to idle the device timeout.
600 * It prevents command submission from occuring and makes
601 * every pending request fail
602 */
Ben Gamariba1234d2009-09-14 17:48:47 -0400603 atomic_t wedged;
Eric Anholt673a3942008-07-30 12:06:12 -0700604
605 /** Bit 6 swizzling required for X tiling */
606 uint32_t bit_6_swizzle_x;
607 /** Bit 6 swizzling required for Y tiling */
608 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000609
610 /* storage for physical objects */
611 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Eric Anholt673a3942008-07-30 12:06:12 -0700612 } mm;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800613 struct sdvo_device_mapping sdvo_mappings[2];
Zhao Yakuia3e17eb2009-10-10 10:42:37 +0800614 /* indicate whether the LVDS_BORDER should be enabled or not */
615 unsigned int lvds_border_bits;
Jesse Barnes652c3932009-08-17 13:31:43 -0700616
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500617 struct drm_crtc *plane_to_crtc_mapping[2];
618 struct drm_crtc *pipe_to_crtc_mapping[2];
619 wait_queue_head_t pending_flip_queue;
620
Jesse Barnes652c3932009-08-17 13:31:43 -0700621 /* Reclocking support */
622 bool render_reclock_avail;
623 bool lvds_downclock_avail;
Zhao Yakuibfac4d62010-04-07 17:11:22 +0800624 /* indicate whether the LVDS EDID is OK */
625 bool lvds_edid_good;
Zhao Yakui18f9ed12009-11-20 03:24:16 +0000626 /* indicates the reduced downclock for LVDS*/
627 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -0700628 struct work_struct idle_work;
629 struct timer_list idle_timer;
630 bool busy;
631 u16 orig_clock;
Zhao Yakui6363ee62009-11-24 09:48:44 +0800632 int child_dev_num;
633 struct child_device_config *child_dev;
Zhao Yakuia2565372009-12-11 09:26:11 +0800634 struct drm_connector *int_lvds_connector;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800635
Zhenyu Wangc48044112009-12-17 14:48:43 +0800636 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800637
638 u8 cur_delay;
639 u8 min_delay;
640 u8 max_delay;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800641
642 enum no_fbc_reason no_fbc_reason;
Dave Airlie38651672010-03-30 05:34:13 +0000643
Dave Airlie8be48d92010-03-30 05:34:14 +0000644 /* list of fbdev register on this device */
645 struct intel_fbdev *fbdev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646} drm_i915_private_t;
647
Eric Anholt673a3942008-07-30 12:06:12 -0700648/** driver private structure attached to each drm_gem_object */
649struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +0000650 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -0700651 struct drm_gem_object *obj;
652
653 /** Current space allocated to this object in the GTT, if any. */
654 struct drm_mm_node *gtt_space;
655
656 /** This object's place on the active/flushing/inactive lists */
657 struct list_head list;
Daniel Vetter99fcb762010-02-07 16:20:18 +0100658 /** This object's place on GPU write list */
659 struct list_head gpu_write_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700660
Eric Anholta09ba7f2009-08-29 12:49:51 -0700661 /** This object's place on the fenced object LRU */
662 struct list_head fence_list;
663
Eric Anholt673a3942008-07-30 12:06:12 -0700664 /**
665 * This is set if the object is on the active or flushing lists
666 * (has pending rendering), and is not set if it's on inactive (ready
667 * to be unbound).
668 */
669 int active;
670
671 /**
672 * This is set if the object has been written to since last bound
673 * to the GTT
674 */
675 int dirty;
676
677 /** AGP memory structure for our GTT binding. */
678 DRM_AGP_MEM *agp_mem;
679
Eric Anholt856fa192009-03-19 14:10:50 -0700680 struct page **pages;
681 int pages_refcount;
Eric Anholt673a3942008-07-30 12:06:12 -0700682
683 /**
684 * Current offset of the object in GTT space.
685 *
686 * This is the same as gtt_space->start
687 */
688 uint32_t gtt_offset;
Chris Wilsone67b8ce2009-09-14 16:50:26 +0100689
Jesse Barnesde151cf2008-11-12 10:03:55 -0800690 /**
691 * Fake offset for use by mmap(2)
692 */
693 uint64_t mmap_offset;
694
695 /**
696 * Fence register bits (if any) for this object. Will be set
697 * as needed when mapped into the GTT.
698 * Protected by dev->struct_mutex.
699 */
700 int fence_reg;
Eric Anholt673a3942008-07-30 12:06:12 -0700701
Eric Anholt673a3942008-07-30 12:06:12 -0700702 /** How many users have pinned this object in GTT space */
703 int pin_count;
704
705 /** Breadcrumb of last rendering to the buffer. */
706 uint32_t last_rendering_seqno;
707
708 /** Current tiling mode for the object. */
709 uint32_t tiling_mode;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800710 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700711
Eric Anholt280b7132009-03-12 16:56:27 -0700712 /** Record of address bit 17 of each page at last unbind. */
713 long *bit_17;
714
Keith Packardba1eb1d2008-10-14 19:55:10 -0700715 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
716 uint32_t agp_type;
717
Eric Anholt673a3942008-07-30 12:06:12 -0700718 /**
Eric Anholte47c68e2008-11-14 13:35:19 -0800719 * If present, while GEM_DOMAIN_CPU is in the read domain this array
720 * flags which individual pages are valid.
Eric Anholt673a3942008-07-30 12:06:12 -0700721 */
722 uint8_t *page_cpu_valid;
Jesse Barnes79e53942008-11-07 14:24:08 -0800723
724 /** User space pin count and filp owning the pin */
725 uint32_t user_pin_count;
726 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000727
728 /** for phy allocated objects */
729 struct drm_i915_gem_phys_object *phys_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -0500730
731 /**
732 * Used for checking the object doesn't appear more than once
733 * in an execbuffer object list.
734 */
735 int in_execbuffer;
Chris Wilson3ef94da2009-09-14 16:50:29 +0100736
737 /**
738 * Advice: are the backing pages purgeable?
739 */
740 int madv;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500741
742 /**
743 * Number of crtcs where this object is currently the fb, but
744 * will be page flipped away on the next vblank. When it
745 * reaches 0, dev_priv->pending_flip_queue will be woken up.
746 */
747 atomic_t pending_flip;
Eric Anholt673a3942008-07-30 12:06:12 -0700748};
749
Daniel Vetter62b8b212010-04-09 19:05:08 +0000750#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +0100751
Eric Anholt673a3942008-07-30 12:06:12 -0700752/**
753 * Request queue structure.
754 *
755 * The request queue allows us to note sequence numbers that have been emitted
756 * and may be associated with active buffers to be retired.
757 *
758 * By keeping this list, we can avoid having to do questionable
759 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
760 * an emission time with seqnos for tracking how far ahead of the GPU we are.
761 */
762struct drm_i915_gem_request {
763 /** GEM sequence number associated with this request. */
764 uint32_t seqno;
765
766 /** Time at which this request was emitted, in jiffies. */
767 unsigned long emitted_jiffies;
768
Eric Anholtb9624422009-06-03 07:27:35 +0000769 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -0700770 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +0000771
772 /** file_priv list entry for this request */
773 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700774};
775
776struct drm_i915_file_private {
777 struct {
Eric Anholtb9624422009-06-03 07:27:35 +0000778 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700779 } mm;
780};
781
Jesse Barnes79e53942008-11-07 14:24:08 -0800782enum intel_chip_family {
783 CHIP_I8XX = 0x01,
784 CHIP_I9XX = 0x02,
785 CHIP_I915 = 0x04,
786 CHIP_I965 = 0x08,
787};
788
Eric Anholtc153f452007-09-03 12:06:45 +1000789extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000790extern int i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800791extern unsigned int i915_fbpercrtc;
Jesse Barnes652c3932009-08-17 13:31:43 -0700792extern unsigned int i915_powersave;
Jesse Barnes33814342010-01-14 20:48:02 +0000793extern unsigned int i915_lvds_downclock;
Dave Airlieb3a83632005-09-30 18:37:36 +1000794
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000795extern int i915_suspend(struct drm_device *dev, pm_message_t state);
796extern int i915_resume(struct drm_device *dev);
Ben Gamari1341d652009-09-14 17:48:42 -0400797extern void i915_save_display(struct drm_device *dev);
798extern void i915_restore_display(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000799extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
800extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
801
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000803extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100804extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000805extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -0700806extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000807extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000808extern void i915_driver_preclose(struct drm_device *dev,
809 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700810extern void i915_driver_postclose(struct drm_device *dev,
811 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000812extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100813extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
814 unsigned long arg);
Eric Anholt673a3942008-07-30 12:06:12 -0700815extern int i915_emit_box(struct drm_device *dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700816 struct drm_clip_rect *boxes,
Eric Anholt673a3942008-07-30 12:06:12 -0700817 int i, int DR1, int DR4);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400818extern int i965_reset(struct drm_device *dev, u8 flags);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000819
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820/* i915_irq.c */
Ben Gamarif65d9422009-09-14 17:48:44 -0400821void i915_hangcheck_elapsed(unsigned long data);
Chris Wilson9df30792010-02-18 10:24:56 +0000822void i915_destroy_error_state(struct drm_device *dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000823extern int i915_irq_emit(struct drm_device *dev, void *data,
824 struct drm_file *file_priv);
825extern int i915_irq_wait(struct drm_device *dev, void *data,
826 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700827void i915_user_irq_get(struct drm_device *dev);
Chris Wilson9d34e5d2009-09-24 05:26:06 +0100828void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
Eric Anholt673a3942008-07-30 12:06:12 -0700829void i915_user_irq_put(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800830extern void i915_enable_interrupt (struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831
832extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000833extern void i915_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700834extern int i915_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000835extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000836extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
837 struct drm_file *file_priv);
838extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
839 struct drm_file *file_priv);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700840extern int i915_enable_vblank(struct drm_device *dev, int crtc);
841extern void i915_disable_vblank(struct drm_device *dev, int crtc);
842extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800843extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
Eric Anholtc153f452007-09-03 12:06:45 +1000844extern int i915_vblank_swap(struct drm_device *dev, void *data,
845 struct drm_file *file_priv);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100846extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
Keith Packard7c463582008-11-04 02:03:27 -0800848void
849i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
850
851void
852i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
853
Zhao Yakui01c66882009-10-28 05:10:00 +0000854void intel_enable_asle (struct drm_device *dev);
855
Keith Packard7c463582008-11-04 02:03:27 -0800856
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000858extern int i915_mem_alloc(struct drm_device *dev, void *data,
859 struct drm_file *file_priv);
860extern int i915_mem_free(struct drm_device *dev, void *data,
861 struct drm_file *file_priv);
862extern int i915_mem_init_heap(struct drm_device *dev, void *data,
863 struct drm_file *file_priv);
864extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
865 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000867extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000868 struct drm_file *file_priv, struct mem_block *heap);
Eric Anholt673a3942008-07-30 12:06:12 -0700869/* i915_gem.c */
870int i915_gem_init_ioctl(struct drm_device *dev, void *data,
871 struct drm_file *file_priv);
872int i915_gem_create_ioctl(struct drm_device *dev, void *data,
873 struct drm_file *file_priv);
874int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
875 struct drm_file *file_priv);
876int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
877 struct drm_file *file_priv);
878int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
879 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800880int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
881 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700882int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
883 struct drm_file *file_priv);
884int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
885 struct drm_file *file_priv);
886int i915_gem_execbuffer(struct drm_device *dev, void *data,
887 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -0500888int i915_gem_execbuffer2(struct drm_device *dev, void *data,
889 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700890int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
891 struct drm_file *file_priv);
892int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
893 struct drm_file *file_priv);
894int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
895 struct drm_file *file_priv);
896int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
897 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +0100898int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
899 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700900int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *file_priv);
902int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
903 struct drm_file *file_priv);
904int i915_gem_set_tiling(struct drm_device *dev, void *data,
905 struct drm_file *file_priv);
906int i915_gem_get_tiling(struct drm_device *dev, void *data,
907 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -0700908int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
909 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700910void i915_gem_load(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700911int i915_gem_init_object(struct drm_gem_object *obj);
Daniel Vetterac52bc52010-04-09 19:05:06 +0000912struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
913 size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -0700914void i915_gem_free_object(struct drm_gem_object *obj);
915int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
916void i915_gem_object_unpin(struct drm_gem_object *obj);
Jesse Barnes0f973f22009-01-26 17:10:45 -0800917int i915_gem_object_unbind(struct drm_gem_object *obj);
Eric Anholtd05ca302009-07-10 13:02:26 -0700918void i915_gem_release_mmap(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700919void i915_gem_lastclose(struct drm_device *dev);
920uint32_t i915_get_gem_seqno(struct drm_device *dev);
Ben Gamari22be1722009-09-14 17:48:43 -0400921bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100922int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +0100923int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700924void i915_gem_retire_requests(struct drm_device *dev);
925void i915_gem_retire_work_handler(struct work_struct *work);
926void i915_gem_clflush_object(struct drm_gem_object *obj);
Jesse Barnes79e53942008-11-07 14:24:08 -0800927int i915_gem_object_set_domain(struct drm_gem_object *obj,
928 uint32_t read_domains,
929 uint32_t write_domain);
930int i915_gem_init_ringbuffer(struct drm_device *dev);
931void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
932int i915_gem_do_init(struct drm_device *dev, unsigned long start,
933 unsigned long end);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800934int i915_gem_idle(struct drm_device *dev);
Daniel Vetter5a5a0c62009-09-15 22:57:36 +0200935uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
936 uint32_t flush_domains);
937int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800938int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Jesse Barnes79e53942008-11-07 14:24:08 -0800939int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
940 int write);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +0800941int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +1000942int i915_gem_attach_phys_object(struct drm_device *dev,
943 struct drm_gem_object *obj, int id);
944void i915_gem_detach_phys_object(struct drm_device *dev,
945 struct drm_gem_object *obj);
946void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilson4bdadb92010-01-27 13:36:32 +0000947int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
Ben Gamari6911a9b2009-04-02 11:24:54 -0700948void i915_gem_object_put_pages(struct drm_gem_object *obj);
Eric Anholt1fd1c622009-06-03 07:26:58 +0000949void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500950void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700951
Chris Wilson31169712009-09-14 16:50:28 +0100952void i915_gem_shrinker_init(void);
953void i915_gem_shrinker_exit(void);
954
Eric Anholt673a3942008-07-30 12:06:12 -0700955/* i915_gem_tiling.c */
956void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -0700957void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
958void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
Jesse Barnes76446ca2009-12-17 22:05:42 -0500959bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
960 int tiling_mode);
Owain Ainsworthf590d272010-02-18 15:33:00 +0000961bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
962 int tiling_mode);
Eric Anholt673a3942008-07-30 12:06:12 -0700963
964/* i915_gem_debug.c */
965void i915_gem_dump_object(struct drm_gem_object *obj, int len,
966 const char *where, uint32_t mark);
967#if WATCH_INACTIVE
968void i915_verify_inactive(struct drm_device *dev, char *file, int line);
969#else
970#define i915_verify_inactive(dev, file, line)
971#endif
972void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
973void i915_gem_dump_object(struct drm_gem_object *obj, int len,
974 const char *where, uint32_t mark);
975void i915_dump_lru(struct drm_device *dev, const char *where);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976
Ben Gamari20172632009-02-17 20:08:50 -0500977/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -0400978int i915_debugfs_init(struct drm_minor *minor);
979void i915_debugfs_cleanup(struct drm_minor *minor);
Ben Gamari20172632009-02-17 20:08:50 -0500980
Jesse Barnes317c35d2008-08-25 15:11:06 -0700981/* i915_suspend.c */
982extern int i915_save_state(struct drm_device *dev);
983extern int i915_restore_state(struct drm_device *dev);
984
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700985/* i915_suspend.c */
986extern int i915_save_state(struct drm_device *dev);
987extern int i915_restore_state(struct drm_device *dev);
988
Len Brown65e082c2008-10-24 17:18:10 -0400989#ifdef CONFIG_ACPI
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100990/* i915_opregion.c */
Matthew Garrett74a365b2009-03-19 21:35:39 +0000991extern int intel_opregion_init(struct drm_device *dev, int resume);
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100992extern void intel_opregion_free(struct drm_device *dev, int suspend);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100993extern void opregion_asle_intr(struct drm_device *dev);
Zhao Yakui01c66882009-10-28 05:10:00 +0000994extern void ironlake_opregion_gse_intr(struct drm_device *dev);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100995extern void opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -0400996#else
Len Brown03ae61d2009-03-28 01:41:14 -0400997static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100998static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
Len Brown65e082c2008-10-24 17:18:10 -0400999static inline void opregion_asle_intr(struct drm_device *dev) { return; }
Zhao Yakui01c66882009-10-28 05:10:00 +00001000static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
Len Brown65e082c2008-10-24 17:18:10 -04001001static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1002#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001003
Jesse Barnes79e53942008-11-07 14:24:08 -08001004/* modesetting */
1005extern void intel_modeset_init(struct drm_device *dev);
1006extern void intel_modeset_cleanup(struct drm_device *dev);
Dave Airlie28d52042009-09-21 14:33:58 +10001007extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Jesse Barnes80824002009-09-10 15:28:06 -07001008extern void i8xx_disable_fbc(struct drm_device *dev);
Jesse Barnes74dff282009-09-14 15:39:40 -07001009extern void g4x_disable_fbc(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001010
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001011extern void intel_detect_pch (struct drm_device *dev);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001012extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001013
Eric Anholt546b0972008-09-01 16:45:29 -07001014/**
1015 * Lock test for when it's just for synchronization of ring access.
1016 *
1017 * In that case, we don't need to do it when GEM is initialized as nobody else
1018 * has access to the ring.
1019 */
1020#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1021 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
1022 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1023} while (0)
1024
Eric Anholt3043c602008-10-02 12:24:47 -07001025#define I915_READ(reg) readl(dev_priv->regs + (reg))
1026#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1027#define I915_READ16(reg) readw(dev_priv->regs + (reg))
1028#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1029#define I915_READ8(reg) readb(dev_priv->regs + (reg))
1030#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
Jesse Barnesde151cf2008-11-12 10:03:55 -08001031#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
Keith Packard049ef7e2009-04-30 14:43:43 -07001032#define I915_READ64(reg) readq(dev_priv->regs + (reg))
Eric Anholt7d573822009-01-02 13:33:00 -08001033#define POSTING_READ(reg) (void)I915_READ(reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034
1035#define I915_VERBOSE 0
1036
Chris Wilson0ef82af2009-09-05 18:07:06 +01001037#define RING_LOCALS volatile unsigned int *ring_virt__;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038
Chris Wilson0ef82af2009-09-05 18:07:06 +01001039#define BEGIN_LP_RING(n) do { \
1040 int bytes__ = 4*(n); \
1041 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1042 /* a wrap must occur between instructions so pad beforehand */ \
1043 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
1044 i915_wrap_ring(dev); \
1045 if (unlikely (dev_priv->ring.space < bytes__)) \
1046 i915_wait_ring(dev, bytes__, __func__); \
1047 ring_virt__ = (unsigned int *) \
1048 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
1049 dev_priv->ring.tail += bytes__; \
1050 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
1051 dev_priv->ring.space -= bytes__; \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052} while (0)
1053
Chris Wilson0ef82af2009-09-05 18:07:06 +01001054#define OUT_RING(n) do { \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Chris Wilson0ef82af2009-09-05 18:07:06 +01001056 *ring_virt__++ = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057} while (0)
1058
1059#define ADVANCE_LP_RING() do { \
Chris Wilson0ef82af2009-09-05 18:07:06 +01001060 if (I915_VERBOSE) \
1061 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
1062 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063} while(0)
1064
Jesse Barnes585fb112008-07-29 11:54:06 -07001065/**
1066 * Reads a dword out of the status page, which is written to from the command
1067 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1068 * MI_STORE_DATA_IMM.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001069 *
Jesse Barnes585fb112008-07-29 11:54:06 -07001070 * The following dwords have a reserved meaning:
Keith Packard0cdad7e2008-10-14 17:19:38 -07001071 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1072 * 0x04: ring 0 head pointer
1073 * 0x05: ring 1 head pointer (915-class)
1074 * 0x06: ring 2 head pointer (915-class)
1075 * 0x10-0x1b: Context status DWords (GM45)
1076 * 0x1f: Last written status offset. (GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07001077 *
Keith Packard0cdad7e2008-10-14 17:19:38 -07001078 * The area from dword 0x20 to 0x3ff is available for driver usage.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001079 */
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001080#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
Keith Packard0baf8232008-11-08 11:44:14 +10001081#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
Keith Packard0cdad7e2008-10-14 17:19:38 -07001082#define I915_GEM_HWS_INDEX 0x20
Keith Packard0baf8232008-11-08 11:44:14 +10001083#define I915_BREADCRUMB_INDEX 0x21
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001084
Chris Wilson0ef82af2009-09-05 18:07:06 +01001085extern int i915_wrap_ring(struct drm_device * dev);
Jesse Barnes585fb112008-07-29 11:54:06 -07001086extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001087
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001088#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001089
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001090#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1091#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1092#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1093#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
Eric Anholtbad720f2009-10-22 16:11:14 -07001094#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001095#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1096#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1097#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1098#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1099#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1100#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1101#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1102#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1103#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1104#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1105#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1106#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001107#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1108#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001109#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1110#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
Zhenyu Wang59f2d0f2010-03-09 23:37:07 +08001111#define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001112#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Zhenyu Wang280da222009-06-05 15:38:37 +08001113
Eric Anholtbad720f2009-10-22 16:11:14 -07001114#define IS_GEN3(dev) (IS_I915G(dev) || \
1115 IS_I915GM(dev) || \
1116 IS_I945G(dev) || \
1117 IS_I945GM(dev) || \
1118 IS_G33(dev) || \
1119 IS_PINEVIEW(dev))
1120#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1121 (dev)->pci_device == 0x2982 || \
1122 (dev)->pci_device == 0x2992 || \
1123 (dev)->pci_device == 0x29A2 || \
1124 (dev)->pci_device == 0x2A02 || \
1125 (dev)->pci_device == 0x2A12 || \
1126 (dev)->pci_device == 0x2E02 || \
1127 (dev)->pci_device == 0x2E12 || \
1128 (dev)->pci_device == 0x2E22 || \
1129 (dev)->pci_device == 0x2E32 || \
1130 (dev)->pci_device == 0x2A42 || \
1131 (dev)->pci_device == 0x2E42)
1132
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001133#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001134
Jesse Barnes0f973f22009-01-26 17:10:45 -08001135/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1136 * rows, which changed the alignment requirements and fence programming.
1137 */
1138#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1139 IS_I915GM(dev)))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001140#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1141#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1142#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1143#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
Zhenyu Wang103a1962009-11-27 11:44:36 +08001144#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
Zhenyu Wang7da9f6c2010-04-07 16:15:52 +08001145 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1146 !IS_GEN6(dev))
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001147#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001148/* dsparb controlled by hw only */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001149#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
Zhenyu Wangb39d50e2008-02-19 20:59:09 +10001150
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001151#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05001152#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1153#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1154#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
Jesse Barnes652c3932009-08-17 13:31:43 -07001155
Eric Anholtbad720f2009-10-22 16:11:14 -07001156#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1157 IS_GEN6(dev))
1158
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001159#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1160#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1161
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001162#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +11001163
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164#endif